STM32U575

• 0x46022000EXTI// External interrupt/event controller

  • 0x46022000EXTI_RTSR1// EXTI rising trigger selection register

    • [0]RT0 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [1]RT1 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [2]RT2 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [3]RT3 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [4]RT4 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [5]RT5 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [6]RT6 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [7]RT7 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [8]RT8 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [9]RT9 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [10]RT10 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [11]RT11 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [12]RT12 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [13]RT13 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [14]RT14 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [15]RT15 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [16]RT16 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [17]RT17 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [18]RT18 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [19]RT19 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [20]RT20 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [21]RT21 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [22]RT22 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [23]RT23 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [24]RT24 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [25]RT25 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
  • 0x46022004EXTI_FTSR1// EXTI falling trigger selection register

    • [0]FT0 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [1]FT1 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [2]FT2 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [3]FT3 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [4]FT4 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [5]FT5 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [6]FT6 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [7]FT7 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [8]FT8 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [9]FT9 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [10]FT10 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [11]FT11 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [12]FT12 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [13]FT13 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [14]FT14 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [15]FT15 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [16]FT16 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [17]FT17 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [18]FT18 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [19]FT19 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [20]FT20 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [21]FT21 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [22]FT22 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [23]FT23 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [24]FT24 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [25]FT25 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
  • 0x46022008EXTI_SWIER1// EXTI software interrupt event register

    • [0]SWI0 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [1]SWI1 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [2]SWI2 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [3]SWI3 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [4]SWI4 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [5]SWI5 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [6]SWI6 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [7]SWI7 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [8]SWI8 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [9]SWI9 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [10]SWI10 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [11]SWI11 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [12]SWI12 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [13]SWI13 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [14]SWI14 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [15]SWI15 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [16]SWI16 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [17]SWI17 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [18]SWI18 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [19]SWI19 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [20]SWI20 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [21]SWI21 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [22]SWI22 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [23]SWI23 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [24]SWI24 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [25]SWI25 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
  • 0x4602200CEXTI_RPR1// EXTI rising edge pending register

    • [0]RPIF0 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [1]RPIF1 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [2]RPIF2 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [3]RPIF3 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [4]RPIF4 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [5]RPIF5 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [6]RPIF6 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [7]RPIF7 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [8]RPIF8 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [9]RPIF9 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [10]RPIF10 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [11]RPIF11 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [12]RPIF12 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [13]RPIF13 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [14]RPIF14 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [15]RPIF15 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [16]RPIF16 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [17]RPIF17 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [18]RPIF18 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [19]RPIF19 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [20]RPIF20 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [21]RPIF21 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [22]RPIF22 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [23]RPIF23 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [24]RPIF24 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [25]RPIF25 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
  • 0x46022010EXTI_FPR1// EXTI falling edge pending register

    • [0]FPIF0 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [1]FPIF1 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [2]FPIF2 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [3]FPIF3 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [4]FPIF4 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [5]FPIF5 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [6]FPIF6 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [7]FPIF7 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [8]FPIF8 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [9]FPIF9 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [10]FPIF10 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [11]FPIF11 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [12]FPIF12 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [13]FPIF13 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [14]FPIF14 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [15]FPIF15 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [16]FPIF16 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [17]FPIF17 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [18]FPIF18 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [19]FPIF19 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [20]FPIF20 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [21]FPIF21 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [22]FPIF22 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [23]FPIF23 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [24]FPIF24 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [25]FPIF25 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
  • 0x46022014EXTI_SECCFGR1// EXTI security configuration register

    • [0]SEC0 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [1]SEC1 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [2]SEC2 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [3]SEC3 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [4]SEC4 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [5]SEC5 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [6]SEC6 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [7]SEC7 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [8]SEC8 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [9]SEC9 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [10]SEC10 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [11]SEC11 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [12]SEC12 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [13]SEC13 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [14]SEC14 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [15]SEC15 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [16]SEC16 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [17]SEC17 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [18]SEC18 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [19]SEC19 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [20]SEC20 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [21]SEC21 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [22]SEC22 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [23]SEC23 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [24]SEC24 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [25]SEC25 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
  • 0x46022018EXTI_PRIVCFGR1// EXTI privilege configuration register

    • [0]PRIV0 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [1]PRIV1 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [2]PRIV2 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [3]PRIV3 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [4]PRIV4 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [5]PRIV5 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [6]PRIV6 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [7]PRIV7 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [8]PRIV8 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [9]PRIV9 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [10]PRIV10 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [11]PRIV11 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [12]PRIV12 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [13]PRIV13 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [14]PRIV14 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [15]PRIV15 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [16]PRIV16 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [17]PRIV17 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [18]PRIV18 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [19]PRIV19 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [20]PRIV20 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [21]PRIV21 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [22]PRIV22 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [23]PRIV23 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [24]PRIV24 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [25]PRIV25 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
  • 0x46022060EXTI_EXTICR1// EXTI external interrupt selection register

    • [0:7]EXTI0 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI1 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI2 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI3 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x46022064EXTI_EXTICR2// EXTI external interrupt selection register

    • [0:7]EXTI4 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI5 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI6 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI7 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x46022068EXTI_EXTICR3// EXTI external interrupt selection register

    • [0:7]EXTI8 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI9 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI10 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI11 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x4602206CEXTI_EXTICR4// EXTI external interrupt selection register

    • [0:7]EXTI12 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI13 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI14 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI15 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x46022070EXTI_LOCKR// EXTI lock register

    • [0]LOCK (def=0x0) // Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bi
  • 0x46022080EXTI_IMR1// EXTI CPU wake-up with interrupt mask register

    • [0]IM0 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [1]IM1 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [2]IM2 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [3]IM3 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [4]IM4 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [5]IM5 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [6]IM6 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [7]IM7 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [8]IM8 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [9]IM9 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [10]IM10 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [11]IM11 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [12]IM12 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [13]IM13 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [14]IM14 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [15]IM15 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [16]IM16 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [17]IM17 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [18]IM18 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [19]IM19 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [20]IM20 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [21]IM21 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [22]IM22 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [23]IM23 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [24]IM24 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [25]IM25 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
  • 0x46022084EXTI_EMR1// EXTI CPU wake-up with event mask register

    • [0]EM0 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [1]EM1 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [2]EM2 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [3]EM3 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [4]EM4 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [5]EM5 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [6]EM6 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [7]EM7 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [8]EM8 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [9]EM9 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [10]EM10 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [11]EM11 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [12]EM12 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [13]EM13 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [14]EM14 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [15]EM15 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [16]EM16 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [17]EM17 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [18]EM18 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [19]EM19 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [20]EM20 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [21]EM21 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [22]EM22 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [23]EM23 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [24]EM24 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [25]EM25 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
  interrupts:
  • [1] PVD_PVM // Power voltage monitor/Analog voltage monitor
  • [9] EXTI0 // EXTI line0 interrupt
  • [10] EXTI1 // EXTI line1 interrupt
  • [11] EXTI2 // EXTI line2 interrupt
  • [12] EXTI3 // EXTI line3 interrupt
  • [13] EXTI4 // EXTI line4 interrupt
  • [14] EXTI5 // EXTI line5 interrupt
  • [15] EXTI6 // EXTI line6 interrupt
  • [1] EXTI7 // EXTI line7 interrupt
  • [1] EXTI8 // EXTI line8 interrupt
  • [16] EXTI9 // EXTI line9 interrupt
  • [17] EXTI10 // EXTI line10 interrupt
  • [18] EXTI11 // EXTI line11 interrupt
  • [19] EXTI12 // EXTI line12 interrupt
  • [20] EXTI13 // EXTI line13 interrupt
  • [21] EXTI14 // EXTI line14 interrupt
  • [22] EXTI15 // EXTI line15 interrupt
  • [95] FPU // Floating point interrupt
  • [125] LSECSSD // LSECSSD interrupt
  • [132] GPU2D_IRQ // GPU2D interrupt
  • [133] GPU2D_IRQSYS // GPU2D system interrupt
• 0x56022000SEC_EXTI//

  • 0x56022000EXTI_RTSR1// EXTI rising trigger selection register

    • [0]RT0 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [1]RT1 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [2]RT2 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [3]RT3 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [4]RT4 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [5]RT5 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [6]RT6 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [7]RT7 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [8]RT8 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [9]RT9 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [10]RT10 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [11]RT11 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [12]RT12 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [13]RT13 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [14]RT14 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [15]RT15 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [16]RT16 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [17]RT17 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [18]RT18 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [19]RT19 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [20]RT20 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [21]RT21 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [22]RT22 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [23]RT23 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [24]RT24 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
    • [25]RT25 (def=0x0) // Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disa
  • 0x56022004EXTI_FTSR1// EXTI falling trigger selection register

    • [0]FT0 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [1]FT1 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [2]FT2 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [3]FT3 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [4]FT4 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [5]FT5 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [6]FT6 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [7]FT7 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [8]FT8 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [9]FT9 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [10]FT10 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [11]FT11 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [12]FT12 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [13]FT13 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [14]FT14 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [15]FT15 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [16]FT16 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [17]FT17 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [18]FT18 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [19]FT19 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [20]FT20 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [21]FT21 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [22]FT22 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [23]FT23 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [24]FT24 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
    • [25]FT25 (def=0x0) // Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is dis
  • 0x56022008EXTI_SWIER1// EXTI software interrupt event register

    • [0]SWI0 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [1]SWI1 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [2]SWI2 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [3]SWI3 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [4]SWI4 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [5]SWI5 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [6]SWI6 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [7]SWI7 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [8]SWI8 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [9]SWI9 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [10]SWI10 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [11]SWI11 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [12]SWI12 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [13]SWI13 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [14]SWI14 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [15]SWI15 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [16]SWI16 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [17]SWI17 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [18]SWI18 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [19]SWI19 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [20]SWI20 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [21]SWI21 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [22]SWI22 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [23]SWI23 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [24]SWI24 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
    • [25]SWI25 (def=0x0) // Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-sec
  • 0x5602200CEXTI_RPR1// EXTI rising edge pending register

    • [0]RPIF0 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [1]RPIF1 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [2]RPIF2 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [3]RPIF3 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [4]RPIF4 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [5]RPIF5 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [6]RPIF6 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [7]RPIF7 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [8]RPIF8 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [9]RPIF9 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [10]RPIF10 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [11]RPIF11 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [12]RPIF12 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [13]RPIF13 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [14]RPIF14 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [15]RPIF15 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [16]RPIF16 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [17]RPIF17 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [18]RPIF18 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [19]RPIF19 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [20]RPIF20 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [21]RPIF21 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [22]RPIF22 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [23]RPIF23 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [24]RPIF24 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
    • [25]RPIF25 (def=0x0) // configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can b
  • 0x56022010EXTI_FPR1// EXTI falling edge pending register

    • [0]FPIF0 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [1]FPIF1 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [2]FPIF2 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [3]FPIF3 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [4]FPIF4 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [5]FPIF5 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [6]FPIF6 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [7]FPIF7 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [8]FPIF8 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [9]FPIF9 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [10]FPIF10 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [11]FPIF11 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [12]FPIF12 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [13]FPIF13 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [14]FPIF14 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [15]FPIF15 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [16]FPIF16 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [17]FPIF17 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [18]FPIF18 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [19]FPIF19 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [20]FPIF20 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [21]FPIF21 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [22]FPIF22 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [23]FPIF23 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [24]FPIF24 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
    • [25]FPIF25 (def=0x0) // configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can
  • 0x56022014EXTI_SECCFGR1// EXTI security configuration register

    • [0]SEC0 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [1]SEC1 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [2]SEC2 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [3]SEC3 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [4]SEC4 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [5]SEC5 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [6]SEC6 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [7]SEC7 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [8]SEC8 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [9]SEC9 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [10]SEC10 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [11]SEC11 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [12]SEC12 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [13]SEC13 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [14]SEC14 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [15]SEC15 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [16]SEC16 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [17]SEC17 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [18]SEC18 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [19]SEC19 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [20]SEC20 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [21]SEC21 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [22]SEC22 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [23]SEC23 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [24]SEC24 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
    • [25]SEC25 (def=0x0) // Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with pr
  • 0x56022018EXTI_PRIVCFGR1// EXTI privilege configuration register

    • [0]PRIV0 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [1]PRIV1 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [2]PRIV2 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [3]PRIV3 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [4]PRIV4 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [5]PRIV5 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [6]PRIV6 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [7]PRIV7 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [8]PRIV8 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [9]PRIV9 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [10]PRIV10 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [11]PRIV11 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [12]PRIV12 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [13]PRIV13 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [14]PRIV14 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [15]PRIV15 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [16]PRIV16 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [17]PRIV17 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [18]PRIV18 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [19]PRIV19 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [20]PRIV20 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [21]PRIV21 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [22]PRIV22 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [23]PRIV23 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [24]PRIV24 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
    • [25]PRIV25 (def=0x0) // Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with sec
  • 0x56022060EXTI_EXTICR1// EXTI external interrupt selection register

    • [0:7]EXTI0 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI1 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI2 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI3 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x56022064EXTI_EXTICR2// EXTI external interrupt selection register

    • [0:7]EXTI4 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI5 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI6 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI7 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x56022068EXTI_EXTICR3// EXTI external interrupt selection register

    • [0:7]EXTI8 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI9 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI10 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI11 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x5602206CEXTI_EXTICR4// EXTI external interrupt selection register

    • [0:7]EXTI12 (def=0x0) // EXTIm GPIO port selection
    • [8:15]EXTI13 (def=0x0) // EXTIm+1 GPIO port selection
    • [16:23]EXTI14 (def=0x0) // EXTIm+2 GPIO port selection
    • [24:31]EXTI15 (def=0x0) // EXTIm+3 GPIO port selection
  • 0x56022070EXTI_LOCKR// EXTI lock register

    • [0]LOCK (def=0x0) // Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bi
  • 0x56022080EXTI_IMR1// EXTI CPU wake-up with interrupt mask register

    • [0]IM0 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [1]IM1 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [2]IM2 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [3]IM3 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [4]IM4 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [5]IM5 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [6]IM6 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [7]IM7 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [8]IM8 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [9]IM9 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [10]IM10 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [11]IM11 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [12]IM12 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [13]IM13 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [14]IM14 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [15]IM15 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [16]IM16 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [17]IM17 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [18]IM18 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [19]IM19 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [20]IM20 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [21]IM21 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [22]IM22 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [23]IM23 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [24]IM24 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
    • [25]IM25 (def=0x0) // CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be acc
  • 0x56022084EXTI_EMR1// EXTI CPU wake-up with event mask register

    • [0]EM0 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [1]EM1 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [2]EM2 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [3]EM3 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [4]EM4 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [5]EM5 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [6]EM6 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [7]EM7 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [8]EM8 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [9]EM9 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [10]EM10 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [11]EM11 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [12]EM12 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [13]EM13 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [14]EM14 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [15]EM15 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [16]EM16 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [17]EM17 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [18]EM18 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [19]EM19 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [20]EM20 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [21]EM21 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [22]EM22 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [23]EM23 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [24]EM24 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
    • [25]EM25 (def=0x0) // CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can
• 0x40022000FLASH// Flash

  • 0x40022000FLASH_ACR// FLASH access control register

    • [0:3]LATENCY (def=0x0) // Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory acc
    • [8]PRFTEN (def=0x0) // Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory.
    • [11]LPM (def=0x0) // Low-power read mode This bit puts the Flash memory in low-power read mode.
    • [12]PDREQ1 (def=0x0) // Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests ba
    • [13]PDREQ2 (def=0x0) // Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests ba
    • [14]SLEEP_PD (def=0x0) // Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in p
  • 0x40022008FLASH_NSKEYR// FLASH non-secure key register

    • [0:31]NSKEY (def=0x0) // Flash memory non-secure key
  • 0x4002200CFLASH_SECKEYR// FLASH secure key register

    • [0:31]SECKEY (def=0x0) // Flash memory secure key
  • 0x40022010FLASH_OPTKEYR// FLASH option key register

    • [0:31]OPTKEY (def=0x0) // Option byte key
  • 0x40022018FLASH_PDKEY1R// FLASH bank 1 power-down key register

    • [0:31]PDKEY1 (def=0x0) // Bank 1 power-down key
  • 0x4002201CFLASH_PDKEY2R// FLASH bank 2 power-down key register

    • [0:31]PDKEY2 (def=0x0) // Bank 2 power-down key
  • 0x40022020FLASH_NSSR// FLASH non-secure status register

    • [0]EOP (def=0x0) // Non-secure end of operation
    • [1]OPERR (def=0x0) // Non-secure operation error
    • [3]PROGERR (def=0x0) // Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be
    • [4]WRPERR (def=0x0) // Non-secure write protection error This bit is set by hardware when an non-secure address to be eras
    • [5]PGAERR (def=0x0) // Non-secure programming alignment error This bit is set by hardware when the first word to be progra
    • [6]SIZERR (def=0x0) // Non-secure size error This bit is set by hardware when the size of the access is a byte or half-wor
    • [7]PGSERR (def=0x0) // Non-secure programming sequence error This bit is set by hardware when programming sequence is not
    • [13]OPTWERR (def=0x0) // Option write error This bit is set by hardware when the options bytes are written with an invalid c
    • [16]BSY (def=0x0) // Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. T
    • [17]WDW (def=0x0) // Non-secure wait data to write This bit indicates that the Flash memory write buffer has been writte
    • [18]OEM1LOCK (def=0x0) // OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the
    • [19]OEM2LOCK (def=0x0) // OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the
    • [20]PD1 (def=0x0) // Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. I
    • [21]PD2 (def=0x0) // Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. I
  • 0x40022024FLASH_SECSR// FLASH secure status register

    • [0]EOP (def=0x0) // Secure end of operation This bit is set by hardware when one or more Flash memory secure operation
    • [1]OPERR (def=0x0) // Secure operation error This bit is set by hardware when a Flash memory secure operation (program/er
    • [3]PROGERR (def=0x0) // Secure programming error This bit is set by hardware when a secure quad-word address to be programm
    • [4]WRPERR (def=0x0) // Secure write protection error This bit is set by hardware when an secure address to be erased/progr
    • [5]PGAERR (def=0x0) // Secure programming alignment error This bit is set by hardware when the first word to be programmed
    • [6]SIZERR (def=0x0) // Secure size error This bit is set by hardware when the size of the access is a byte or half-word du
    • [7]PGSERR (def=0x0) // Secure programming sequence error This bit is set by hardware when programming sequence is not corr
    • [16]BSY (def=0x0) // Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. T
    • [17]WDW (def=0x0) // Secure wait data to write This bit indicates that the Flash memory write buffer has been written by
  • 0x40022028FLASH_NSCR// FLASH non-secure control register

    • [0]PG (def=0x0) // Non-secure programming
    • [1]PER (def=0x0) // Non-secure page erase
    • [2]MER1 (def=0x0) // Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pa
    • [3:9]PNB (def=0x0) // Non-secure page number selection These bits select the page to erase. ...
    • [11]BKER (def=0x0) // Non-secure bank selection for page erase
    • [14]BWR (def=0x0) // Non-secure burst write programming mode When set, this bit selects the burst write programming mode
    • [15]MER2 (def=0x0) // Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pa
    • [16]STRT (def=0x0) // Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bit
    • [17]OPTSTRT (def=0x0) // Options modification start This bit triggers an options operation when set. It can not be written i
    • [24]EOPIE (def=0x0) // Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP
    • [25]ERRIE (def=0x0) // Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in t
    • [27]OBL_LAUNCH (def=0x0) // Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is
    • [30]OPTLOCK (def=0x1) // Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register
    • [31]LOCK (def=0x1) // Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by
  • 0x4002202CFLASH_SECCR// FLASH secure control register

    • [0]PG (def=0x0) // Secure programming
    • [1]PER (def=0x0) // Secure page erase
    • [2]MER1 (def=0x0) // Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) whe
    • [3:9]PNB (def=0x0) // Secure page number selection These bits select the page to erase: ...
    • [11]BKER (def=0x0) // Secure bank selection for page erase
    • [14]BWR (def=0x0) // Secure burst write programming mode When set, this bit selects the burst write programming mode.
    • [15]MER2 (def=0x0) // Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) whe
    • [16]STRT (def=0x0) // Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are re
    • [24]EOPIE (def=0x0) // Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit
    • [25]ERRIE (def=0x0) // Secure error interrupt enable
    • [26]RDERRIE (def=0x0) // Secure PCROP read error interrupt enable
    • [29]INV (def=0x0) // Flash memory security state invert This bit inverts the Flash memory security state.
    • [31]LOCK (def=0x1) // Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by ha
  • 0x40022030FLASH_ECCR// FLASH ECC register

    • [0:19]ADDR_ECC (def=0x0) // ECC fail address
    • [21]BK_ECC (def=0x0) // ECC fail bank
    • [22]SYSF_ECC (def=0x0) // System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error d
    • [24]ECCIE (def=0x0) // ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the
    • [30]ECCC (def=0x0) // ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only
    • [31]ECCD (def=0x0) // ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and
  • 0x40022034FLASH_OPSR// FLASH operation status register

    • [0:19]ADDR_OP (def=0x0) // Interrupted operation address This field indicates which address in the Flash memory was accessed w
    • [21]BK_OP (def=0x0) // Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occur
    • [22]SYSF_OP (def=0x0) // Operation in system Flash memory interrupted This bit indicates that the reset occurred during an o
    • [29:31]CODE_OP (def=0x0) // Flash memory operation code This field indicates which Flash memory operation has been interrupted
  • 0x40022040FLASH_OPTR// FLASH option register

    • [0:7]RDP (def=0x0) // Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for m
    • [8:10]BOR_LEV (def=0x0) // BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset
    • [12]nRST_STOP (def=0x0) // Reset generation in Stop mode
    • [13]nRST_STDBY (def=0x0) // Reset generation in Standby mode
    • [14]nRST_SHDW (def=0x0) // Reset generation in Shutdown mode
    • [15]SRAM1345_RST (def=0x0) // SRAM1, SRAM3 and SRAM4 erase upon system reset
    • [16]IWDG_SW (def=0x0) // Independent watchdog selection
    • [17]IWDG_STOP (def=0x0) // Independent watchdog counter freeze in Stop mode
    • [18]IWDG_STDBY (def=0x0) // Independent watchdog counter freeze in Standby mode
    • [19]WWDG_SW (def=0x0) // Window watchdog selection
    • [20]SWAP_BANK (def=0x0) // Swap banks
    • [21]DUALBANK (def=0x0) // Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices
    • [22]BKPRAM_ECC (def=0x0) // Backup RAM ECC detection and correction enable
    • [23]SRAM3_ECC (def=0x0) // SRAM3 ECC detection and correction enable
    • [24]SRAM2_ECC (def=0x0) // SRAM2 ECC detection and correction enable
    • [25]SRAM2_RST (def=0x0) // SRAM2 erase when system reset
    • [26]nSWBOOT0 (def=0x0) // Software BOOT0
    • [27]nBOOT0 (def=0x0) // nBOOT0 option bit
    • [28]PA15_PUPEN (def=0x0) // PA15 pull-up enable
    • [29]IO_VDD_HSLV (def=0x0) // High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V
    • [30]IO_VDDIO2_HSLV (def=0x0) // High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.
    • [31]TZEN (def=0x0) // Global TrustZone security enable
  • 0x40022044FLASH_NSBOOTADD0R// FLASH non-secure boot address 0 register

    • [7:31]NSBOOTADD0 (def=0x0) // Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address
  • 0x40022048FLASH_NSBOOTADD1R// FLASH non-secure boot address 1 register

    • [7:31]NSBOOTADD1 (def=0x0) // Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in th
  • 0x4002204CFLASH_SECBOOTADD0R// FLASH secure boot address 0 register

    • [0]BOOT_LOCK (def=0x0) // Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0]
    • [7:31]SECBOOTADD0 (def=0x0) // Secure boot base address 0 The secure boot memory address can be programmed to any address in the v
  • 0x40022050FLASH_SECWM1R1// FLASH secure watermark1 register 1

    • [0:6]SECWM1_PSTRT (def=0x0) // Start page of first secure area This field contains the first page of the secure area in bank 1.
    • [16:22]SECWM1_PEND (def=0x0) // End page of first secure area This field contains the last page of the secure area in bank 1.
  • 0x40022054FLASH_SECWM1R2// FLASH secure watermark1 register 2

    • [16:22]HDP1_PEND (def=0x0) // End page of first hide protection area This field contains the last page of the HDP area in bank 1.
    • [31]HDP1EN (def=0x0) // Hide protection first area enable
  • 0x40022058FLASH_WRP1AR// FLASH WRP1 area A address register

    • [0:6]WRP1A_PSTRT (def=0x0) // bank 1 WPR first area A start page This field contains the first page of the first WPR area for ban
    • [16:22]WRP1A_PEND (def=0x0) // Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1.
    • [31]UNLOCK (def=0x0) // Bank 1 WPR first area A unlock
  • 0x4002205CFLASH_WRP1BR// FLASH WRP1 area B address register

    • [0:6]WRP1B_PSTRT (def=0x0) // Bank 1 WRP second area B start page This field contains the first page of the second WRP area for b
    • [16:22]WRP1B_PEND (def=0x0) // Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank
    • [31]UNLOCK (def=0x0) // Bank 1 WPR second area B unlock
  • 0x40022060FLASH_SECWM2R1// FLASH secure watermark2 register 1

    • [0:6]SECWM2_PSTRT (def=0x0) // Start page of second secure area This field contains the first page of the secure area in bank 2.
    • [16:22]SECWM2_PEND (def=0x0) // End page of second secure area This field contains the last page of the secure area in bank 2.
  • 0x40022064FLASH_SECWM2R2// FLASH secure watermark2 register 2

    • [16:22]HDP2_PEND (def=0x0) // End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2.
    • [31]HDP2EN (def=0x0) // Hide protection second area enable
  • 0x40022068FLASH_WRP2AR// FLASH WPR2 area A address register

    • [0:6]WRP2A_PSTRT (def=0x0) // Bank 2 WPR first area A start page This field contains the first page of the first WRP area for ban
    • [16:22]WRP2A_PEND (def=0x0) // Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2.
    • [31]UNLOCK (def=0x0) // Bank 2 WPR first area A unlock
  • 0x4002206CFLASH_WRP2BR// FLASH WPR2 area B address register

    • [0:6]WRP2B_PSTRT (def=0x0) // Bank 2 WPR second area B start page This field contains the first page of the second WRP area for b
    • [16:22]WRP2B_PEND (def=0x0) // Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank
    • [31]UNLOCK (def=0x0) // Bank 2 WPR second area B unlock
  • 0x40022070FLASH_OEM1KEYR1// FLASH OEM1 key register 1

    • [0:31]OEM1KEY (def=0x0) // OEM1 least significant bytes key
  • 0x40022074FLASH_OEM1KEYR2// FLASH OEM1 key register 2

    • [0:31]OEM1KEY (def=0x0) // OEM1 most significant bytes key
  • 0x40022078FLASH_OEM2KEYR1// FLASH OEM2 key register 1

    • [0:31]OEM2KEY (def=0x0) // OEM2 least significant bytes key
  • 0x4002207CFLASH_OEM2KEYR2// FLASH OEM2 key register 2

    • [0:31]OEM2KEY (def=0x0) // OEM2 most significant bytes key
  • 0x40022080FLASH_SEC1BBR1// FLASH secure block based bank 1 register 1

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x40022084FLASH_SEC1BBR2// FLASH secure block based bank 1 register 2

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x40022088FLASH_SEC1BBR3// FLASH secure block based bank 1 register 3

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x4002208CFLASH_SEC1BBR4// FLASH secure block based bank 1 register 4

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x400220A0FLASH_SEC2BBR1// FLASH secure block based bank 2 register 1

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x400220A4FLASH_SEC2BBR2// FLASH secure block based bank 2 register 2

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x400220A8FLASH_SEC2BBR3// FLASH secure block based bank 2 register 3

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x400220ACFLASH_SEC2BBR4// FLASH secure block based bank 2 register 4

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x400220C0FLASH_SECHDPCR// FLASH secure HDP control register

    • [0]HDP1_ACCDIS (def=0x0) // HDP1 area access disable When set, this bit is only cleared by a system reset.
    • [1]HDP2_ACCDIS (def=0x0) // HDP2 area access disable When set, this bit is only cleared by a system reset.
  • 0x400220C4FLASH_PRIVCFGR// FLASH privilege configuration register

    • [0]SPRIV (def=0x0) // Privileged protection for secure registers This bit can be accessed only when TrustZone is enabled
    • [1]NSPRIV (def=0x0) // Privileged protection for non-secure registers This bit can be read by both privileged or unprivile
  • 0x400220D0FLASH_PRIV1BBR1// FLASH privilege block based bank 1 register 1

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220D4FLASH_PRIV1BBR2// FLASH privilege block based bank 1 register 2

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220D8FLASH_PRIV1BBR3// FLASH privilege block based bank 1 register 3

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220DCFLASH_PRIV1BBR4// FLASH privilege block based bank 1 register 4

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220F0FLASH_PRIV2BBR1// FLASH privilege block based bank 2 register 1

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220F4FLASH_PRIV2BBR2// FLASH privilege block based bank 2 register 2

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220F8FLASH_PRIV2BBR3// FLASH privilege block based bank 2 register 3

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x400220FCFLASH_PRIV2BBR4// FLASH privilege block based bank 2 register 4

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  interrupts:
  • [6] FLASH // Flash memory non-secure global interrupt
  • [7] FLASH_S // Flash memory secure global interrupt
• 0x50022000SEC_FLASH//

  • 0x50022000FLASH_ACR// FLASH access control register

    • [0:3]LATENCY (def=0x0) // Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory acc
    • [8]PRFTEN (def=0x0) // Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory.
    • [11]LPM (def=0x0) // Low-power read mode This bit puts the Flash memory in low-power read mode.
    • [12]PDREQ1 (def=0x0) // Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests ba
    • [13]PDREQ2 (def=0x0) // Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests ba
    • [14]SLEEP_PD (def=0x0) // Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in p
  • 0x50022008FLASH_NSKEYR// FLASH non-secure key register

    • [0:31]NSKEY (def=0x0) // Flash memory non-secure key
  • 0x5002200CFLASH_SECKEYR// FLASH secure key register

    • [0:31]SECKEY (def=0x0) // Flash memory secure key
  • 0x50022010FLASH_OPTKEYR// FLASH option key register

    • [0:31]OPTKEY (def=0x0) // Option byte key
  • 0x50022018FLASH_PDKEY1R// FLASH bank 1 power-down key register

    • [0:31]PDKEY1 (def=0x0) // Bank 1 power-down key
  • 0x5002201CFLASH_PDKEY2R// FLASH bank 2 power-down key register

    • [0:31]PDKEY2 (def=0x0) // Bank 2 power-down key
  • 0x50022020FLASH_NSSR// FLASH non-secure status register

    • [0]EOP (def=0x0) // Non-secure end of operation
    • [1]OPERR (def=0x0) // Non-secure operation error
    • [3]PROGERR (def=0x0) // Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be
    • [4]WRPERR (def=0x0) // Non-secure write protection error This bit is set by hardware when an non-secure address to be eras
    • [5]PGAERR (def=0x0) // Non-secure programming alignment error This bit is set by hardware when the first word to be progra
    • [6]SIZERR (def=0x0) // Non-secure size error This bit is set by hardware when the size of the access is a byte or half-wor
    • [7]PGSERR (def=0x0) // Non-secure programming sequence error This bit is set by hardware when programming sequence is not
    • [13]OPTWERR (def=0x0) // Option write error This bit is set by hardware when the options bytes are written with an invalid c
    • [16]BSY (def=0x0) // Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. T
    • [17]WDW (def=0x0) // Non-secure wait data to write This bit indicates that the Flash memory write buffer has been writte
    • [18]OEM1LOCK (def=0x0) // OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the
    • [19]OEM2LOCK (def=0x0) // OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the
    • [20]PD1 (def=0x0) // Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. I
    • [21]PD2 (def=0x0) // Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. I
  • 0x50022024FLASH_SECSR// FLASH secure status register

    • [0]EOP (def=0x0) // Secure end of operation This bit is set by hardware when one or more Flash memory secure operation
    • [1]OPERR (def=0x0) // Secure operation error This bit is set by hardware when a Flash memory secure operation (program/er
    • [3]PROGERR (def=0x0) // Secure programming error This bit is set by hardware when a secure quad-word address to be programm
    • [4]WRPERR (def=0x0) // Secure write protection error This bit is set by hardware when an secure address to be erased/progr
    • [5]PGAERR (def=0x0) // Secure programming alignment error This bit is set by hardware when the first word to be programmed
    • [6]SIZERR (def=0x0) // Secure size error This bit is set by hardware when the size of the access is a byte or half-word du
    • [7]PGSERR (def=0x0) // Secure programming sequence error This bit is set by hardware when programming sequence is not corr
    • [16]BSY (def=0x0) // Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. T
    • [17]WDW (def=0x0) // Secure wait data to write This bit indicates that the Flash memory write buffer has been written by
  • 0x50022028FLASH_NSCR// FLASH non-secure control register

    • [0]PG (def=0x0) // Non-secure programming
    • [1]PER (def=0x0) // Non-secure page erase
    • [2]MER1 (def=0x0) // Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pa
    • [3:9]PNB (def=0x0) // Non-secure page number selection These bits select the page to erase. ...
    • [11]BKER (def=0x0) // Non-secure bank selection for page erase
    • [14]BWR (def=0x0) // Non-secure burst write programming mode When set, this bit selects the burst write programming mode
    • [15]MER2 (def=0x0) // Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pa
    • [16]STRT (def=0x0) // Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bit
    • [17]OPTSTRT (def=0x0) // Options modification start This bit triggers an options operation when set. It can not be written i
    • [24]EOPIE (def=0x0) // Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP
    • [25]ERRIE (def=0x0) // Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in t
    • [27]OBL_LAUNCH (def=0x0) // Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is
    • [30]OPTLOCK (def=0x1) // Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register
    • [31]LOCK (def=0x1) // Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by
  • 0x5002202CFLASH_SECCR// FLASH secure control register

    • [0]PG (def=0x0) // Secure programming
    • [1]PER (def=0x0) // Secure page erase
    • [2]MER1 (def=0x0) // Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) whe
    • [3:9]PNB (def=0x0) // Secure page number selection These bits select the page to erase: ...
    • [11]BKER (def=0x0) // Secure bank selection for page erase
    • [14]BWR (def=0x0) // Secure burst write programming mode When set, this bit selects the burst write programming mode.
    • [15]MER2 (def=0x0) // Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) whe
    • [16]STRT (def=0x0) // Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are re
    • [24]EOPIE (def=0x0) // Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit
    • [25]ERRIE (def=0x0) // Secure error interrupt enable
    • [26]RDERRIE (def=0x0) // Secure PCROP read error interrupt enable
    • [29]INV (def=0x0) // Flash memory security state invert This bit inverts the Flash memory security state.
    • [31]LOCK (def=0x1) // Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by ha
  • 0x50022030FLASH_ECCR// FLASH ECC register

    • [0:19]ADDR_ECC (def=0x0) // ECC fail address
    • [21]BK_ECC (def=0x0) // ECC fail bank
    • [22]SYSF_ECC (def=0x0) // System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error d
    • [24]ECCIE (def=0x0) // ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the
    • [30]ECCC (def=0x0) // ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only
    • [31]ECCD (def=0x0) // ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and
  • 0x50022034FLASH_OPSR// FLASH operation status register

    • [0:19]ADDR_OP (def=0x0) // Interrupted operation address This field indicates which address in the Flash memory was accessed w
    • [21]BK_OP (def=0x0) // Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occur
    • [22]SYSF_OP (def=0x0) // Operation in system Flash memory interrupted This bit indicates that the reset occurred during an o
    • [29:31]CODE_OP (def=0x0) // Flash memory operation code This field indicates which Flash memory operation has been interrupted
  • 0x50022040FLASH_OPTR// FLASH option register

    • [0:7]RDP (def=0x0) // Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for m
    • [8:10]BOR_LEV (def=0x0) // BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset
    • [12]nRST_STOP (def=0x0) // Reset generation in Stop mode
    • [13]nRST_STDBY (def=0x0) // Reset generation in Standby mode
    • [14]nRST_SHDW (def=0x0) // Reset generation in Shutdown mode
    • [15]SRAM1345_RST (def=0x0) // SRAM1, SRAM3 and SRAM4 erase upon system reset
    • [16]IWDG_SW (def=0x0) // Independent watchdog selection
    • [17]IWDG_STOP (def=0x0) // Independent watchdog counter freeze in Stop mode
    • [18]IWDG_STDBY (def=0x0) // Independent watchdog counter freeze in Standby mode
    • [19]WWDG_SW (def=0x0) // Window watchdog selection
    • [20]SWAP_BANK (def=0x0) // Swap banks
    • [21]DUALBANK (def=0x0) // Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices
    • [22]BKPRAM_ECC (def=0x0) // Backup RAM ECC detection and correction enable
    • [23]SRAM3_ECC (def=0x0) // SRAM3 ECC detection and correction enable
    • [24]SRAM2_ECC (def=0x0) // SRAM2 ECC detection and correction enable
    • [25]SRAM2_RST (def=0x0) // SRAM2 erase when system reset
    • [26]nSWBOOT0 (def=0x0) // Software BOOT0
    • [27]nBOOT0 (def=0x0) // nBOOT0 option bit
    • [28]PA15_PUPEN (def=0x0) // PA15 pull-up enable
    • [29]IO_VDD_HSLV (def=0x0) // High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V
    • [30]IO_VDDIO2_HSLV (def=0x0) // High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.
    • [31]TZEN (def=0x0) // Global TrustZone security enable
  • 0x50022044FLASH_NSBOOTADD0R// FLASH non-secure boot address 0 register

    • [7:31]NSBOOTADD0 (def=0x0) // Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address
  • 0x50022048FLASH_NSBOOTADD1R// FLASH non-secure boot address 1 register

    • [7:31]NSBOOTADD1 (def=0x0) // Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in th
  • 0x5002204CFLASH_SECBOOTADD0R// FLASH secure boot address 0 register

    • [0]BOOT_LOCK (def=0x0) // Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0]
    • [7:31]SECBOOTADD0 (def=0x0) // Secure boot base address 0 The secure boot memory address can be programmed to any address in the v
  • 0x50022050FLASH_SECWM1R1// FLASH secure watermark1 register 1

    • [0:6]SECWM1_PSTRT (def=0x0) // Start page of first secure area This field contains the first page of the secure area in bank 1.
    • [16:22]SECWM1_PEND (def=0x0) // End page of first secure area This field contains the last page of the secure area in bank 1.
  • 0x50022054FLASH_SECWM1R2// FLASH secure watermark1 register 2

    • [16:22]HDP1_PEND (def=0x0) // End page of first hide protection area This field contains the last page of the HDP area in bank 1.
    • [31]HDP1EN (def=0x0) // Hide protection first area enable
  • 0x50022058FLASH_WRP1AR// FLASH WRP1 area A address register

    • [0:6]WRP1A_PSTRT (def=0x0) // bank 1 WPR first area A start page This field contains the first page of the first WPR area for ban
    • [16:22]WRP1A_PEND (def=0x0) // Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1.
    • [31]UNLOCK (def=0x0) // Bank 1 WPR first area A unlock
  • 0x5002205CFLASH_WRP1BR// FLASH WRP1 area B address register

    • [0:6]WRP1B_PSTRT (def=0x0) // Bank 1 WRP second area B start page This field contains the first page of the second WRP area for b
    • [16:22]WRP1B_PEND (def=0x0) // Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank
    • [31]UNLOCK (def=0x0) // Bank 1 WPR second area B unlock
  • 0x50022060FLASH_SECWM2R1// FLASH secure watermark2 register 1

    • [0:6]SECWM2_PSTRT (def=0x0) // Start page of second secure area This field contains the first page of the secure area in bank 2.
    • [16:22]SECWM2_PEND (def=0x0) // End page of second secure area This field contains the last page of the secure area in bank 2.
  • 0x50022064FLASH_SECWM2R2// FLASH secure watermark2 register 2

    • [16:22]HDP2_PEND (def=0x0) // End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2.
    • [31]HDP2EN (def=0x0) // Hide protection second area enable
  • 0x50022068FLASH_WRP2AR// FLASH WPR2 area A address register

    • [0:6]WRP2A_PSTRT (def=0x0) // Bank 2 WPR first area A start page This field contains the first page of the first WRP area for ban
    • [16:22]WRP2A_PEND (def=0x0) // Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2.
    • [31]UNLOCK (def=0x0) // Bank 2 WPR first area A unlock
  • 0x5002206CFLASH_WRP2BR// FLASH WPR2 area B address register

    • [0:6]WRP2B_PSTRT (def=0x0) // Bank 2 WPR second area B start page This field contains the first page of the second WRP area for b
    • [16:22]WRP2B_PEND (def=0x0) // Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank
    • [31]UNLOCK (def=0x0) // Bank 2 WPR second area B unlock
  • 0x50022070FLASH_OEM1KEYR1// FLASH OEM1 key register 1

    • [0:31]OEM1KEY (def=0x0) // OEM1 least significant bytes key
  • 0x50022074FLASH_OEM1KEYR2// FLASH OEM1 key register 2

    • [0:31]OEM1KEY (def=0x0) // OEM1 most significant bytes key
  • 0x50022078FLASH_OEM2KEYR1// FLASH OEM2 key register 1

    • [0:31]OEM2KEY (def=0x0) // OEM2 least significant bytes key
  • 0x5002207CFLASH_OEM2KEYR2// FLASH OEM2 key register 2

    • [0:31]OEM2KEY (def=0x0) // OEM2 most significant bytes key
  • 0x50022080FLASH_SEC1BBR1// FLASH secure block based bank 1 register 1

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x50022084FLASH_SEC1BBR2// FLASH secure block based bank 1 register 2

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x50022088FLASH_SEC1BBR3// FLASH secure block based bank 1 register 3

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x5002208CFLASH_SEC1BBR4// FLASH secure block based bank 1 register 4

    • [0]SEC1BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC1BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC1BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC1BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC1BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC1BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC1BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC1BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC1BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC1BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC1BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC1BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC1BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC1BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC1BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC1BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC1BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC1BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC1BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC1BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC1BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC1BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC1BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC1BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC1BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC1BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC1BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC1BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC1BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC1BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC1BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC1BB31 (def=0x0) // page secure/non-secure attribution
  • 0x500220A0FLASH_SEC2BBR1// FLASH secure block based bank 2 register 1

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x500220A4FLASH_SEC2BBR2// FLASH secure block based bank 2 register 2

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x500220A8FLASH_SEC2BBR3// FLASH secure block based bank 2 register 3

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x500220ACFLASH_SEC2BBR4// FLASH secure block based bank 2 register 4

    • [0]SEC2BB0 (def=0x0) // page secure/non-secure attribution
    • [1]SEC2BB1 (def=0x0) // page secure/non-secure attribution
    • [2]SEC2BB2 (def=0x0) // page secure/non-secure attribution
    • [3]SEC2BB3 (def=0x0) // page secure/non-secure attribution
    • [4]SEC2BB4 (def=0x0) // page secure/non-secure attribution
    • [5]SEC2BB5 (def=0x0) // page secure/non-secure attribution
    • [6]SEC2BB6 (def=0x0) // page secure/non-secure attribution
    • [7]SEC2BB7 (def=0x0) // page secure/non-secure attribution
    • [8]SEC2BB8 (def=0x0) // page secure/non-secure attribution
    • [9]SEC2BB9 (def=0x0) // page secure/non-secure attribution
    • [10]SEC2BB10 (def=0x0) // page secure/non-secure attribution
    • [11]SEC2BB11 (def=0x0) // page secure/non-secure attribution
    • [12]SEC2BB12 (def=0x0) // page secure/non-secure attribution
    • [13]SEC2BB13 (def=0x0) // page secure/non-secure attribution
    • [14]SEC2BB14 (def=0x0) // page secure/non-secure attribution
    • [15]SEC2BB15 (def=0x0) // page secure/non-secure attribution
    • [16]SEC2BB16 (def=0x0) // page secure/non-secure attribution
    • [17]SEC2BB17 (def=0x0) // page secure/non-secure attribution
    • [18]SEC2BB18 (def=0x0) // page secure/non-secure attribution
    • [19]SEC2BB19 (def=0x0) // page secure/non-secure attribution
    • [20]SEC2BB20 (def=0x0) // page secure/non-secure attribution
    • [21]SEC2BB21 (def=0x0) // page secure/non-secure attribution
    • [22]SEC2BB22 (def=0x0) // page secure/non-secure attribution
    • [23]SEC2BB23 (def=0x0) // page secure/non-secure attribution
    • [24]SEC2BB24 (def=0x0) // page secure/non-secure attribution
    • [25]SEC2BB25 (def=0x0) // page secure/non-secure attribution
    • [26]SEC2BB26 (def=0x0) // page secure/non-secure attribution
    • [27]SEC2BB27 (def=0x0) // page secure/non-secure attribution
    • [28]SEC2BB28 (def=0x0) // page secure/non-secure attribution
    • [29]SEC2BB29 (def=0x0) // page secure/non-secure attribution
    • [30]SEC2BB30 (def=0x0) // page secure/non-secure attribution
    • [31]SEC2BB31 (def=0x0) // page secure/non-secure attribution
  • 0x500220C0FLASH_SECHDPCR// FLASH secure HDP control register

    • [0]HDP1_ACCDIS (def=0x0) // HDP1 area access disable When set, this bit is only cleared by a system reset.
    • [1]HDP2_ACCDIS (def=0x0) // HDP2 area access disable When set, this bit is only cleared by a system reset.
  • 0x500220C4FLASH_PRIVCFGR// FLASH privilege configuration register

    • [0]SPRIV (def=0x0) // Privileged protection for secure registers This bit can be accessed only when TrustZone is enabled
    • [1]NSPRIV (def=0x0) // Privileged protection for non-secure registers This bit can be read by both privileged or unprivile
  • 0x500220D0FLASH_PRIV1BBR1// FLASH privilege block based bank 1 register 1

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220D4FLASH_PRIV1BBR2// FLASH privilege block based bank 1 register 2

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220D8FLASH_PRIV1BBR3// FLASH privilege block based bank 1 register 3

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220DCFLASH_PRIV1BBR4// FLASH privilege block based bank 1 register 4

    • [0]PRIV1BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV1BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV1BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV1BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV1BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV1BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV1BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV1BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV1BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV1BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV1BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV1BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV1BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV1BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV1BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV1BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV1BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV1BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV1BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV1BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV1BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV1BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV1BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV1BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV1BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV1BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV1BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV1BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV1BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV1BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV1BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV1BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220F0FLASH_PRIV2BBR1// FLASH privilege block based bank 2 register 1

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220F4FLASH_PRIV2BBR2// FLASH privilege block based bank 2 register 2

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220F8FLASH_PRIV2BBR3// FLASH privilege block based bank 2 register 3

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
  • 0x500220FCFLASH_PRIV2BBR4// FLASH privilege block based bank 2 register 4

    • [0]PRIV2BB0 (def=0x0) // page privileged/unprivileged attribution
    • [1]PRIV2BB1 (def=0x0) // page privileged/unprivileged attribution
    • [2]PRIV2BB2 (def=0x0) // page privileged/unprivileged attribution
    • [3]PRIV2BB3 (def=0x0) // page privileged/unprivileged attribution
    • [4]PRIV2BB4 (def=0x0) // page privileged/unprivileged attribution
    • [5]PRIV2BB5 (def=0x0) // page privileged/unprivileged attribution
    • [6]PRIV2BB6 (def=0x0) // page privileged/unprivileged attribution
    • [7]PRIV2BB7 (def=0x0) // page privileged/unprivileged attribution
    • [8]PRIV2BB8 (def=0x0) // page privileged/unprivileged attribution
    • [9]PRIV2BB9 (def=0x0) // page privileged/unprivileged attribution
    • [10]PRIV2BB10 (def=0x0) // page privileged/unprivileged attribution
    • [11]PRIV2BB11 (def=0x0) // page privileged/unprivileged attribution
    • [12]PRIV2BB12 (def=0x0) // page privileged/unprivileged attribution
    • [13]PRIV2BB13 (def=0x0) // page privileged/unprivileged attribution
    • [14]PRIV2BB14 (def=0x0) // page privileged/unprivileged attribution
    • [15]PRIV2BB15 (def=0x0) // page privileged/unprivileged attribution
    • [16]PRIV2BB16 (def=0x0) // page privileged/unprivileged attribution
    • [17]PRIV2BB17 (def=0x0) // page privileged/unprivileged attribution
    • [18]PRIV2BB18 (def=0x0) // page privileged/unprivileged attribution
    • [19]PRIV2BB19 (def=0x0) // page privileged/unprivileged attribution
    • [20]PRIV2BB20 (def=0x0) // page privileged/unprivileged attribution
    • [21]PRIV2BB21 (def=0x0) // page privileged/unprivileged attribution
    • [22]PRIV2BB22 (def=0x0) // page privileged/unprivileged attribution
    • [23]PRIV2BB23 (def=0x0) // page privileged/unprivileged attribution
    • [24]PRIV2BB24 (def=0x0) // page privileged/unprivileged attribution
    • [25]PRIV2BB25 (def=0x0) // page privileged/unprivileged attribution
    • [26]PRIV2BB26 (def=0x0) // page privileged/unprivileged attribution
    • [27]PRIV2BB27 (def=0x0) // page privileged/unprivileged attribution
    • [28]PRIV2BB28 (def=0x0) // page privileged/unprivileged attribution
    • [29]PRIV2BB29 (def=0x0) // page privileged/unprivileged attribution
    • [30]PRIV2BB30 (def=0x0) // page privileged/unprivileged attribution
    • [31]PRIV2BB31 (def=0x0) // page privileged/unprivileged attribution
• 0x42020000GPIOA// General-purpose I/Os

  • 0x42020000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42020004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42020008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202000CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42020010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42020014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42020018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202001CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42020020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42020024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42020028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202002CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42020030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52020000SEC_GPIOA//

  • 0x52020000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52020004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52020008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202000CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52020010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52020014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52020018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202001CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52020020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52020024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52020028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202002CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52020030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42020400GPIOB// General-purpose I/Os

  • 0x42020400GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42020404GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42020408GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202040CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42020410GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42020414GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42020418GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202041CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42020420GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42020424GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42020428GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202042CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42020430GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52020400SEC_GPIOB//

  • 0x52020400GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x2) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52020404GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52020408GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202040CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x1) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52020410GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52020414GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52020418GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202041CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52020420GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52020424GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52020428GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202042CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52020430GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42020800GPIOC// General-purpose I/Os

  • 0x42020800GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42020804GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42020808GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202080CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42020810GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42020814GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42020818GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202081CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42020820GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42020824GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42020828GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202082CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42020830GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52020800SEC_GPIOC//

  • 0x52020800GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52020804GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52020808GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202080CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52020810GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52020814GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52020818GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202081CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52020820GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52020824GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52020828GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202082CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52020830GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42020C00GPIOD//

  • 0x42020C00GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42020C04GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42020C08GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x42020C0CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42020C10GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42020C14GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42020C18GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x42020C1CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42020C20GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42020C24GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42020C28GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x42020C2CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42020C30GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52020C00SEC_GPIOD//

  • 0x52020C00GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52020C04GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52020C08GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x52020C0CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52020C10GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52020C14GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52020C18GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x52020C1CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52020C20GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52020C24GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52020C28GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x52020C2CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52020C30GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42021000GPIOE//

  • 0x42021000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42021004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42021008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202100CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42021010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42021014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42021018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202101CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42021020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42021024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42021028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202102CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42021030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52021000SEC_GPIOE//

  • 0x52021000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52021004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52021008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202100CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52021010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52021014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52021018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202101CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52021020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52021024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52021028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202102CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52021030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42021400GPIOF//

  • 0x42021400GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42021404GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42021408GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202140CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42021410GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42021414GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42021418GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202141CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42021420GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42021424GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42021428GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202142CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42021430GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52021400SEC_GPIOF//

  • 0x52021400GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52021404GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52021408GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202140CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52021410GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52021414GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52021418GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202141CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52021420GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52021424GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52021428GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202142CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52021430GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42021800GPIOG//

  • 0x42021800GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42021804GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42021808GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202180CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42021810GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42021814GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42021818GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202181CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42021820GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42021824GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42021828GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202182CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42021830GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52021800SEC_GPIOG//

  • 0x52021800GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52021804GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52021808GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202180CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52021810GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52021814GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52021818GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202181CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52021820GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52021824GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52021828GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202182CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52021830GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42021C00GPIOH// General-purpose I/Os

  • 0x42021C00GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42021C04GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42021C08GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x42021C0CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42021C10GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42021C14GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42021C18GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x42021C1CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42021C20GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42021C24GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42021C28GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x42021C2CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42021C30GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52021C00SEC_GPIOH//

  • 0x52021C00GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52021C04GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52021C08GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x52021C0CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52021C10GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52021C14GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52021C18GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x52021C1CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52021C20GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52021C24GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52021C28GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x52021C2CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52021C30GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x42022000GPIOI// General-purpose I/Os

  • 0x42022000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x42022004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x42022008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x4202200CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x42022010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x42022014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x42022018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x4202201CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x42022020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x42022024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x42022028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x4202202CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x42022030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x52022000SEC_GPIOI//

  • 0x52022000GPIO_MODER// GPIO port mode register

    • [0:1]MODE0 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [2:3]MODE1 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [4:5]MODE2 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [6:7]MODE3 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [8:9]MODE4 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [10:11]MODE5 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [12:13]MODE6 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [14:15]MODE7 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [16:17]MODE8 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [18:19]MODE9 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [20:21]MODE10 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [22:23]MODE11 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [24:25]MODE12 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [26:27]MODE13 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [28:29]MODE14 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
    • [30:31]MODE15 (def=0x3) // Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note:
  • 0x52022004GPIO_OTYPER// GPIO port output type register

    • [0]OT0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [1]OT1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [2]OT2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [3]OT3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [4]OT4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [5]OT5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [6]OT6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [7]OT7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [8]OT8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [9]OT9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [10]OT10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [11]OT11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [12]OT12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [13]OT13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [14]OT14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
    • [15]OT15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output type.
  • 0x52022008GPIO_OSPEEDR// GPIO port output speed register

    • [0:1]OSPEED0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [2:3]OSPEED1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [4:5]OSPEED2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [6:7]OSPEED3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [8:9]OSPEED4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [10:11]OSPEED5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [12:13]OSPEED6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [14:15]OSPEED7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [16:17]OSPEED8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [18:19]OSPEED9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [20:21]OSPEED10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [22:23]OSPEED11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [24:25]OSPEED12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [26:27]OSPEED13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [28:29]OSPEED14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
    • [30:31]OSPEED15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O output speed
  • 0x5202200CGPIO_PUPDR// GPIO port pull-up/pull-down register

    • [0:1]PUPD0 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [2:3]PUPD1 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [4:5]PUPD2 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [6:7]PUPD3 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [8:9]PUPD4 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [10:11]PUPD5 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [12:13]PUPD6 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [14:15]PUPD7 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [16:17]PUPD8 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [18:19]PUPD9 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [20:21]PUPD10 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [22:23]PUPD11 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [24:25]PUPD12 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [26:27]PUPD13 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [28:29]PUPD14 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
    • [30:31]PUPD15 (def=0x0) // Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or p
  • 0x52022010GPIO_IDR// GPIO port input data register

    • [0]ID0 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [1]ID1 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [2]ID2 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [3]ID3 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [4]ID4 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [5]ID5 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [6]ID6 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [7]ID7 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [8]ID8 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [9]ID9 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [10]ID10 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [11]ID11 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [12]ID12 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [13]ID13 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [14]ID14 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
    • [15]ID15 (def=0x0) // Port x input data I/O pin y These bits are read-only. They contain the input value of the correspon
  • 0x52022014GPIO_ODR// GPIO port output data register

    • [0]OD0 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [1]OD1 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [2]OD2 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [3]OD3 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [4]OD4 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [5]OD5 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [6]OD6 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [7]OD7 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [8]OD8 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [9]OD9 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [10]OD10 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [11]OD11 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [12]OD12 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [13]OD13 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [14]OD14 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
    • [15]OD15 (def=0x0) // Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set
  • 0x52022018GPIO_BSRR// GPIO port bit set/reset register

    • [0]BS0 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [1]BS1 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [2]BS2 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [3]BS3 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [4]BS4 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [5]BS5 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [6]BS6 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [7]BS7 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [8]BS8 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [9]BS9 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [10]BS10 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [11]BS11 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [12]BS12 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [13]BS13 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [14]BS14 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [15]BS15 (def=0x0) // Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note
    • [16]BR0 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [17]BR1 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [18]BR2 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [19]BR3 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [20]BR4 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [21]BR5 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [22]BR6 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [23]BR7 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [24]BR8 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [25]BR9 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [26]BR10 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [27]BR11 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [28]BR12 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [29]BR13 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [30]BR14 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
    • [31]BR15 (def=0x0) // Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. No
  • 0x5202201CGPIO_LCKR// GPIO port configuration lock register

    • [0]LCK0 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [1]LCK1 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [2]LCK2 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [3]LCK3 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [4]LCK4 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [5]LCK5 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [6]LCK6 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [7]LCK7 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [8]LCK8 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [9]LCK9 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [10]LCK10 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [11]LCK11 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [12]LCK12 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [13]LCK13 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [14]LCK14 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [15]LCK15 (def=0x0) // Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note
    • [16]LCKK (def=0x0) // Lock key This bit can be read any time. It can only be modified using the lock key write sequence.
  • 0x52022020GPIO_AFRL// GPIO alternate function low register

    • [0:3]AFSEL0 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [4:7]AFSEL1 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [8:11]AFSEL2 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [12:15]AFSEL3 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [16:19]AFSEL4 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [20:23]AFSEL5 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [24:27]AFSEL6 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
    • [28:31]AFSEL7 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by software to configure a
  • 0x52022024GPIO_AFRH// GPIO alternate function high register

    • [0:3]AFSEL8 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [4:7]AFSEL9 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [8:11]AFSEL10 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [12:15]AFSEL11 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [16:19]AFSEL12 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [20:23]AFSEL13 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [24:27]AFSEL14 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
    • [28:31]AFSEL15 (def=0x0) // Alternate function selection for port x I/O pin y These bits are written by the software to configu
  • 0x52022028GPIO_BRR// GPIO port bit reset register

    • [0]BR0 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [1]BR1 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [2]BR2 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [3]BR3 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [4]BR4 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [5]BR5 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [6]BR6 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [7]BR7 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [8]BR8 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [9]BR9 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [10]BR10 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [11]BR11 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [12]BR12 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [13]BR13 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [14]BR14 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
    • [15]BR15 (def=0x0) // Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Not
  • 0x5202202CGPIO_HSLVR// GPIO high-speed low-voltage register

    • [0]HSLV0 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [1]HSLV1 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [2]HSLV2 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [3]HSLV3 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [4]HSLV4 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [5]HSLV5 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [6]HSLV6 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [7]HSLV7 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [8]HSLV8 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [9]HSLV9 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [10]HSLV10 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [11]HSLV11 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [12]HSLV12 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [13]HSLV13 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [14]HSLV14 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
    • [15]HSLV15 (def=0x0) // Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O
  • 0x52022030GPIO_SECCFGR// GPIO secure configuration register

    • [0]SEC0 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [1]SEC1 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [2]SEC2 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [3]SEC3 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [4]SEC4 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [5]SEC5 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [6]SEC6 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [7]SEC7 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [8]SEC8 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [9]SEC9 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [10]SEC10 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [11]SEC11 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [12]SEC12 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [13]SEC13 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [14]SEC14 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
    • [15]SEC15 (def=0x1) // I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I
• 0x40005400I2C1// Inter-integrated circuit

  • 0x40005400CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x40005404CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x40005408OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x4000540COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x40005410TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x40005414TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x40005418ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x4000541CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x40005420PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x40005424RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x40005428TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x4000542CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
  interrupts:
  • [45] I2C1_EV // I2C1 event interrupt
  • [46] I2C1_ER // I2C1 error interrupt
• 0x50005400SEC_I2C1//

  • 0x50005400CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x50005404CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x50005408OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x5000540COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x50005410TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x50005414TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x50005418ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x5000541CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x50005420PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x50005424RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x50005428TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x5000542CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
• 0x40005800I2C2//

  • 0x40005800CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x40005804CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x40005808OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x4000580COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x40005810TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x40005814TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x40005818ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x4000581CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x40005820PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x40005824RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x40005828TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x4000582CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
  interrupts:
  • [47] I2C2_EV // I2C2 event interrupt
  • [5] I2C2_ER // I2C2 error interrupt
• 0x50005800SEC_I2C2//

  • 0x50005800CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x50005804CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x50005808OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x5000580COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x50005810TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x50005814TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x50005818ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x5000581CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x50005820PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x50005824RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x50005828TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x5000582CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
• 0x46002800I2C3//

  • 0x46002800CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x46002804CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x46002808OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x4600280COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x46002810TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x46002814TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x46002818ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x4600281CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x46002820PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x46002824RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x46002828TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x4600282CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
  interrupts:
  • [0] I2C3_EV // I2C3 event interrupt
  • [0] I2C3_ER // I2C3 error interrupt
• 0x56002800SEC_I2C3//

  • 0x56002800CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x56002804CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x56002808OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x5600280COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x56002810TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x56002814TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x56002818ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x5600281CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x56002820PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x56002824RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x56002828TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x5600282CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
• 0x40008400I2C4//

  • 0x40008400CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x40008404CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x40008408OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x4000840COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x40008410TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x40008414TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x40008418ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x4000841CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x40008420PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x40008424RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x40008428TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x4000842CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
  interrupts:
  • [100] I2C4_ER // I2C4 error interrupt
  • [101] I2C4_EV // I2C4 event interrupt
• 0x50008400SEC_I2C4//

  • 0x50008400CR1// Control register 1

    • [0]PE (def=0x0) // Peripheral enable
    • [1]TXIE (def=0x0) // TX Interrupt enable
    • [2]RXIE (def=0x0) // RX Interrupt enable
    • [3]ADDRIE (def=0x0) // Address match interrupt enable (slave only)
    • [4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
    • [5]STOPIE (def=0x0) // STOP detection Interrupt enable
    • [6]TCIE (def=0x0) // Transfer Complete interrupt enable
    • [7]ERRIE (def=0x0) // Error interrupts enable
    • [8:11]DNF (def=0x0) // Digital noise filter
    • [12]ANFOFF (def=0x0) // Analog noise filter OFF
    • [14]TXDMAEN (def=0x0) // DMA transmission requests enable
    • [15]RXDMAEN (def=0x0) // DMA reception requests enable
    • [16]SBC (def=0x0) // Slave byte control
    • [17]NOSTRETCH (def=0x0) // Clock stretching disable
    • [18]WUPEN (def=0x0) // Wakeup from STOP enable
    • [19]GCEN (def=0x0) // General call enable
    • [20]SMBHEN (def=0x0) // SMBus Host address enable
    • [21]SMBDEN (def=0x0) // SMBus Device Default address enable
    • [22]ALERTEN (def=0x0) // SMBUS alert enable
    • [23]PECEN (def=0x0) // PEC enable
    • [24]FMP (def=0x0) // Fast-mode Plus 20 mA drive enable
    • [30]ADDRACLR (def=0x0) // Address match flag (ADDR) automatic clear
    • [31]STOPFACLR (def=0x0) // STOP detection flag (STOPF) automatic clear
  • 0x50008404CR2// Control register 2

    • [26]PECBYTE (def=0x0) // Packet error checking byte
    • [25]AUTOEND (def=0x0) // Automatic end mode (master mode)
    • [24]RELOAD (def=0x0) // NBYTES reload mode
    • [16:23]NBYTES (def=0x0) // Number of bytes
    • [15]NACK (def=0x0) // NACK generation (slave mode)
    • [14]STOP (def=0x0) // Stop generation (master mode)
    • [13]START (def=0x0) // Start generation
    • [12]HEAD10R (def=0x0) // 10-bit address header only read direction (master receiver mode)
    • [11]ADD10 (def=0x0) // 10-bit addressing mode (master mode)
    • [10]RD_WRN (def=0x0) // Transfer direction (master mode)
    • [0:9]SADD (def=0x0) // Slave address bit (master mode)
  • 0x50008408OAR1// Own address register 1

    • [0:9]OA1 (def=0x0) // Interface address
    • [10]OA1MODE (def=0x0) // Own Address 1 10-bit mode
    • [15]OA1EN (def=0x0) // Own Address 1 enable
  • 0x5000840COAR2// Own address register 2

    • [1:7]OA2 (def=0x0) // Interface address
    • [8:10]OA2MSK (def=0x0) // Own Address 2 masks
    • [15]OA2EN (def=0x0) // Own Address 2 enable
  • 0x50008410TIMINGR// Timing register

    • [0:7]SCLL (def=0x0) // SCL low period (master mode)
    • [8:15]SCLH (def=0x0) // SCL high period (master mode)
    • [16:19]SDADEL (def=0x0) // Data hold time
    • [20:23]SCLDEL (def=0x0) // Data setup time
    • [28:31]PRESC (def=0x0) // Timing prescaler
  • 0x50008414TIMEOUTR// Status register 1

    • [0:11]TIMEOUTA (def=0x0) // Bus timeout A
    • [12]TIDLE (def=0x0) // Idle clock timeout detection
    • [15]TIMOUTEN (def=0x0) // Clock timeout enable
    • [16:27]TIMEOUTB (def=0x0) // Bus timeout B
    • [31]TEXTEN (def=0x0) // Extended clock timeout enable
  • 0x50008418ISR// Interrupt and Status register

    • [17:23]ADDCODE (def=0x0) // Address match code (Slave mode)
    • [16]DIR (def=0x0) // Transfer direction (Slave mode)
    • [15]BUSY (def=0x0) // Bus busy
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]TIMEOUT (def=0x0) // Timeout or t_low detection flag
    • [11]PECERR (def=0x0) // PEC Error in reception
    • [10]OVR (def=0x0) // Overrun/Underrun (slave mode)
    • [9]ARLO (def=0x0) // Arbitration lost
    • [8]BERR (def=0x0) // Bus error
    • [7]TCR (def=0x0) // Transfer Complete Reload
    • [6]TC (def=0x0) // Transfer Complete (master mode)
    • [5]STOPF (def=0x0) // Stop detection flag
    • [4]NACKF (def=0x0) // Not acknowledge received flag
    • [3]ADDR (def=0x0) // Address matched (slave mode)
    • [2]RXNE (def=0x0) // Receive data register not empty (receivers)
    • [1]TXIS (def=0x0) // Transmit interrupt status (transmitters)
    • [0]TXE (def=0x1) // Transmit data register empty (transmitters)
  • 0x5000841CICR// Interrupt clear register

    • [13]ALERTCF (def=0x0) // Alert flag clear
    • [12]TIMOUTCF (def=0x0) // Timeout detection flag clear
    • [11]PECCF (def=0x0) // PEC Error flag clear
    • [10]OVRCF (def=0x0) // Overrun/Underrun flag clear
    • [9]ARLOCF (def=0x0) // Arbitration lost flag clear
    • [8]BERRCF (def=0x0) // Bus error flag clear
    • [5]STOPCF (def=0x0) // Stop detection flag clear
    • [4]NACKCF (def=0x0) // Not Acknowledge flag clear
    • [3]ADDRCF (def=0x0) // Address Matched flag clear
  • 0x50008420PECR// PEC register

    • [0:7]PEC (def=0x0) // Packet error checking register
  • 0x50008424RXDR// Receive data register

    • [0:7]RXDATA (def=0x0) // 8-bit receive data
  • 0x50008428TXDR// Transmit data register

    • [0:7]TXDATA (def=0x0) // 8-bit transmit data
  • 0x5000842CI2C_AUTOCR// I2C Autonomous mode control register

    • [6]TCDMAEN (def=0x0) // DMA request enable on Transfer Complete event
    • [7]TCRDMAEN (def=0x0) // DMA request enable on Transfer Complete Reload event
    • [16:19]TRIGSEL (def=0x0) // Trigger selection
    • [20]TRIGPOL (def=0x0) // Trigger polarity
    • [21]TRIGEN (def=0x0) // Trigger enable
• 0x40030400ICache// ICache

  • 0x40030400ICACHE_CR// ICACHE control register

    • [0]EN (def=0x0) // EN
    • [1]CACHEINV (def=0x0) // CACHEINV
    • [2]WAYSEL (def=0x1) // WAYSEL
    • [16]HITMEN (def=0x0) // HITMEN
    • [17]MISSMEN (def=0x0) // MISSMEN
    • [18]HITMRST (def=0x0) // HITMRST
    • [19]MISSMRST (def=0x0) // MISSMRST
  • 0x40030404ICACHE_SR// ICACHE status register

    • [0]BUSYF (def=0x1) // BUSYF
    • [1]BSYENDF (def=0x0) // BSYENDF
    • [2]ERRF (def=0x0) // ERRF
  • 0x40030408ICACHE_IER// ICACHE interrupt enable register

    • [1]BSYENDIE (def=0x0) // BSYENDIE
    • [2]ERRIE (def=0x0) // ERRIE
  • 0x4003040CICACHE_FCR// ICACHE flag clear register

    • [1]CBSYENDF (def=0x0) // CBSYENDF
    • [2]CERRF (def=0x0) // CERRF
  • 0x40030410ICACHE_HMONR// ICACHE hit monitor register

    • [0:31]HITMON (def=0x0) // HITMON
  • 0x40030414ICACHE_MMONR// ICACHE miss monitor register

    • [0:15]MISSMON (def=0x0) // MISSMON
  • 0x40030420ICACHE_CRR0// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x40030424ICACHE_CRR1// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x40030428ICACHE_CRR2// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x4003042CICACHE_CRR3// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  interrupts:
  • [107] ICACHE // Instruction cache global interrupt
• 0x50030400SEC_ICache//

  • 0x50030400ICACHE_CR// ICACHE control register

    • [0]EN (def=0x0) // EN
    • [1]CACHEINV (def=0x0) // CACHEINV
    • [2]WAYSEL (def=0x1) // WAYSEL
    • [16]HITMEN (def=0x0) // HITMEN
    • [17]MISSMEN (def=0x0) // MISSMEN
    • [18]HITMRST (def=0x0) // HITMRST
    • [19]MISSMRST (def=0x0) // MISSMRST
  • 0x50030404ICACHE_SR// ICACHE status register

    • [0]BUSYF (def=0x1) // BUSYF
    • [1]BSYENDF (def=0x0) // BSYENDF
    • [2]ERRF (def=0x0) // ERRF
  • 0x50030408ICACHE_IER// ICACHE interrupt enable register

    • [1]BSYENDIE (def=0x0) // BSYENDIE
    • [2]ERRIE (def=0x0) // ERRIE
  • 0x5003040CICACHE_FCR// ICACHE flag clear register

    • [1]CBSYENDF (def=0x0) // CBSYENDF
    • [2]CERRF (def=0x0) // CERRF
  • 0x50030410ICACHE_HMONR// ICACHE hit monitor register

    • [0:31]HITMON (def=0x0) // HITMON
  • 0x50030414ICACHE_MMONR// ICACHE miss monitor register

    • [0:15]MISSMON (def=0x0) // MISSMON
  • 0x50030420ICACHE_CRR0// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x50030424ICACHE_CRR1// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x50030428ICACHE_CRR2// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
  • 0x5003042CICACHE_CRR3// ICACHE region configuration register

    • [0:7]BASEADDR (def=0x0) // BASEADDR
    • [9:11]RSIZE (def=0x1) // RSIZE
    • [15]REN (def=0x0) // REN
    • [16:26]REMAPADDR (def=0x0) // REMAPADDR
    • [28]MSTSEL (def=0x0) // MSTSEL
    • [31]HBURST (def=0x0) // HBURST
• 0x40031400DCACHE// DCACHE

  • 0x40031400DCACHE_CR// DCACHE control register

    • [0]EN (def=0x0) // EN
    • [1]CACHEINV (def=0x0) // CACHEINV
    • [8:10]CACHECMD (def=0x0) // CACHECMD
    • [11]STARTCMD (def=0x0) // STARTCMD
    • [16]RHITMEN (def=0x0) // RHITMEN
    • [17]RMISSMEN (def=0x0) // RMISSMEN
    • [18]RHITMRST (def=0x0) // RHITMRST
    • [19]RMISSMRST (def=0x0) // RMISSMRST
    • [20]WHITMEN (def=0x0) // WHITMEN
    • [21]WMISSMEN (def=0x0) // WMISSMEN
    • [22]WHITMRST (def=0x0) // WHITMRST
    • [23]WMISSMRST (def=0x0) // WMISSMRST
    • [31]HBURST (def=0x0) // HBURST
  • 0x40031404DCACHE_SR// DCACHE status register

    • [0]BUSYF (def=0x1) // BUSYF
    • [1]BSYENDF (def=0x0) // BSYENDF
    • [2]ERRF (def=0x0) // ERRF
    • [3]BUSYCMDF (def=0x0) // BUSYCMDF
    • [4]CMDENDF (def=0x0) // CMDENDF
  • 0x40031408DCACHE_IER// DCACHE interrupt enable register

    • [1]BSYENDIE (def=0x0) // BSYENDIE
    • [2]ERRIE (def=0x0) // ERRIE
    • [4]CMDENDIE (def=0x0) // CMDENDIE
  • 0x4003140CDCACHE_FCR// DCACHE flag clear register

    • [1]CBSYENDF (def=0x0) // CBSYENDF
    • [2]CERRF (def=0x0) // CERRF
    • [4]CCMDENDF (def=0x0) // CCMDENDF
  • 0x40031410DCACHE_RHMONR// DCACHE read-hit monitor register

    • [0:31]RHITMON (def=0x0) // RHITMON
  • 0x40031414DCACHE_RMMONR// DCACHE read-miss monitor register

    • [0:15]MRISSMON (def=0x0) // RMISSMON
  • 0x40031420DCACHE_WHMONR// write-hit monitor register

    • [0:31]WHITMON (def=0x0) // WHITMON
  • 0x40031424DCACHE_WMMONR// write-miss monitor register

    • [0:15]WMISSMON (def=0x0) // WMISSMON
  • 0x40031428DCACHE_CMDRSADDRR// command range start address register

    • [0:31]CMDSTARTADDR (def=0x0) // CMDSTARTADDR
  • 0x4003142CDCACHE_CMDREADDRR// command range start address register

    • [0:31]CMDENDADDR (def=0x0) // CMDENDADDR
  interrupts:
  • [111] DCACHE // Data cache global interrupt
• 0x50031400SEC_DCACHE//

  • 0x50031400DCACHE_CR// DCACHE control register

    • [0]EN (def=0x0) // EN
    • [1]CACHEINV (def=0x0) // CACHEINV
    • [8:10]CACHECMD (def=0x0) // CACHECMD
    • [11]STARTCMD (def=0x0) // STARTCMD
    • [16]RHITMEN (def=0x0) // RHITMEN
    • [17]RMISSMEN (def=0x0) // RMISSMEN
    • [18]RHITMRST (def=0x0) // RHITMRST
    • [19]RMISSMRST (def=0x0) // RMISSMRST
    • [20]WHITMEN (def=0x0) // WHITMEN
    • [21]WMISSMEN (def=0x0) // WMISSMEN
    • [22]WHITMRST (def=0x0) // WHITMRST
    • [23]WMISSMRST (def=0x0) // WMISSMRST
    • [31]HBURST (def=0x0) // HBURST
  • 0x50031404DCACHE_SR// DCACHE status register

    • [0]BUSYF (def=0x1) // BUSYF
    • [1]BSYENDF (def=0x0) // BSYENDF
    • [2]ERRF (def=0x0) // ERRF
    • [3]BUSYCMDF (def=0x0) // BUSYCMDF
    • [4]CMDENDF (def=0x0) // CMDENDF
  • 0x50031408DCACHE_IER// DCACHE interrupt enable register

    • [1]BSYENDIE (def=0x0) // BSYENDIE
    • [2]ERRIE (def=0x0) // ERRIE
    • [4]CMDENDIE (def=0x0) // CMDENDIE
  • 0x5003140CDCACHE_FCR// DCACHE flag clear register

    • [1]CBSYENDF (def=0x0) // CBSYENDF
    • [2]CERRF (def=0x0) // CERRF
    • [4]CCMDENDF (def=0x0) // CCMDENDF
  • 0x50031410DCACHE_RHMONR// DCACHE read-hit monitor register

    • [0:31]RHITMON (def=0x0) // RHITMON
  • 0x50031414DCACHE_RMMONR// DCACHE read-miss monitor register

    • [0:15]MRISSMON (def=0x0) // RMISSMON
  • 0x50031420DCACHE_WHMONR// write-hit monitor register

    • [0:31]WHITMON (def=0x0) // WHITMON
  • 0x50031424DCACHE_WMMONR// write-miss monitor register

    • [0:15]WMISSMON (def=0x0) // WMISSMON
  • 0x50031428DCACHE_CMDRSADDRR// command range start address register

    • [0:31]CMDSTARTADDR (def=0x0) // CMDSTARTADDR
  • 0x5003142CDCACHE_CMDREADDRR// command range start address register

    • [0:31]CMDENDADDR (def=0x0) // CMDENDADDR
• 0x40003000IWDG// Independent watchdog

  • 0x40003000KR// Key register

    • [0:15]KEY (def=0x0) // Key value (write only, read 0x0000)
  • 0x40003004PR// Prescaler register

    • [0:3]PR (def=0x0) // Prescaler divider
  • 0x40003008RLR// Reload register

    • [0:11]RL (def=0xFFF) // Watchdog counter reload value
  • 0x4000300CSR// Status register

    • [14]EWIF (def=0x0) // Watchdog Early interrupt flag
    • [3]EWU (def=0x0) // Watchdog interrupt comparator value update
    • [2]WVU (def=0x0) // Watchdog counter window value update
    • [1]RVU (def=0x0) // Watchdog counter reload value update
    • [0]PVU (def=0x0) // Watchdog prescaler value update
  • 0x40003010WINR// Window register

    • [0:11]WIN (def=0xFFF) // Watchdog counter window value
  • 0x40003014EWCR// IWDG early wakeup interrupt register

    • [0:11]EWIT (def=0x0) // Watchdog counter window value
    • [14]EWIC (def=0x0) // Watchdog early interrupt acknowledge
    • [15]EWIE (def=0x0) // Watchdog early interrupt enable
• 0x50003000SEC_IWDG//

  • 0x50003000KR// Key register

    • [0:15]KEY (def=0x0) // Key value (write only, read 0x0000)
  • 0x50003004PR// Prescaler register

    • [0:3]PR (def=0x0) // Prescaler divider
  • 0x50003008RLR// Reload register

    • [0:11]RL (def=0xFFF) // Watchdog counter reload value
  • 0x5000300CSR// Status register

    • [14]EWIF (def=0x0) // Watchdog Early interrupt flag
    • [3]EWU (def=0x0) // Watchdog interrupt comparator value update
    • [2]WVU (def=0x0) // Watchdog counter window value update
    • [1]RVU (def=0x0) // Watchdog counter reload value update
    • [0]PVU (def=0x0) // Watchdog prescaler value update
  • 0x50003010WINR// Window register

    • [0:11]WIN (def=0xFFF) // Watchdog counter window value
  • 0x50003014EWCR// IWDG early wakeup interrupt register

    • [0:11]EWIT (def=0x0) // Watchdog counter window value
    • [14]EWIC (def=0x0) // Watchdog early interrupt acknowledge
    • [15]EWIE (def=0x0) // Watchdog early interrupt enable
• 0x46004400LPTIM1// Low power timer

  • 0x46004400ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x46004400ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x46004404ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004404ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004408DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004408DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x4600440CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x46004410CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x46004414CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x46004418ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x4600441CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x46004424CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x46004428RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x4600442CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x46004434CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x460047ECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x460047F0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
  interrupts:
  • [55] LPTIM1 // LPTIM1 global interrupt
• 0x56004400SEC_LPTIM1//

  • 0x56004400ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x56004400ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x56004404ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004404ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004408DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004408DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x5600440CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x56004410CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x56004414CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x56004418ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x5600441CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x56004424CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x56004428RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x5600442CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x56004434CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x560047ECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x560047F0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
• 0x40009400LPTIM2//

  • 0x40009400ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x40009400ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x40009404ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x40009404ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x40009408DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x40009408DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x4000940CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x40009410CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x40009414CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x40009418ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x4000941CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x40009424CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x40009428RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x4000942CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x40009434CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x400097ECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x400097F0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
  interrupts:
  • [6] LPTIM2 // LPTIM2 global interrupt
• 0x50009400SEC_LPTIM2//

  • 0x50009400ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x50009400ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x50009404ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x50009404ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x50009408DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x50009408DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x5000940CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x50009410CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x50009414CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x50009418ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x5000941CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x50009424CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x50009428RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x5000942CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x50009434CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x500097ECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x500097F0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
• 0x46004800LPTIM3//

  • 0x46004800ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x46004800ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x46004804ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004804ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004808DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004808DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x4600480CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x46004810CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x46004814CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x46004818ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x4600481CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x46004824CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x46004828RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x4600482CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x46004834CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x46004BECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x46004BF0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
  interrupts:
  • [0] LPTIM3 // LPTIM3 global interrupt
• 0x56004800SEC_LPTIM3//

  • 0x56004800ISR_output// Interrupt and Status Register (output mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [19]CMP2OK (def=0x0) // Compare register 2 update OK
    • [9]CC2IF (def=0x0) // Compare 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x56004800ISR_input// Interrupt and Status Register (intput mode)

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [13]CC2OF (def=0x0) // Capture 2 over-capture flag
    • [12]CC1OF (def=0x0) // Capture 1 over-capture flag
    • [9]CC2IF (def=0x0) // Capture 2 interrupt flag
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x56004804ICR_output// Interrupt Clear Register (output mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [19]CMP2OKCF (def=0x0) // Compare register 2 update OK clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004804ICR_input// Interrupt Clear Register (intput mode)

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [13]CC2OCF (def=0x0) // Capture/compare 2 over-capture clear flag
    • [12]CC1OCF (def=0x0) // Capture/compare 1 over-capture clear flag
    • [9]CC2CF (def=0x0) // Capture/compare 2 clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004808DIER_output// LPTIM interrupt Enable Register (output mode)

    • [23]UEDE (def=0x0) // Update event DMA request enable
    • [19]CMP2OKIE (def=0x0) // Compare register 2 update OK interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004808DIER_input// LPTIM interrupt Enable Register (intput mode)

    • [25]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [16]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [13]CC2OIE (def=0x0) // Capture/compare 2 over-capture interrupt enable
    • [12]CC1OIE (def=0x0) // Capture/compare 1 over-capture interrupt enable
    • [9]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x5600480CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x56004810CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x56004814CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x56004818ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x5600481CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x56004824CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x56004828RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x5600482CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x56004834CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x56004BECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x56004BF0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
• 0x46004C00LPTIM4// Low power timer

  • 0x46004C00ISR// Interrupt and Status Register

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x46004C04ICR// Interrupt Clear Register

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004C08DIER// LPTIM interrupt Enable Register

    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x46004C0CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x46004C10CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x46004C14CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x46004C18ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x46004C1CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x46004C24CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x46004C28RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x46004C2CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x46004C34CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x46004FECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x46004FF0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
  interrupts:
  • [110] LPTIM4 // LPTIM4 global interrupt
• 0x56004C00SEC_LPTIM4//

  • 0x56004C00ISR// Interrupt and Status Register

    • [24]DIEROK (def=0x0) // Interrupt enable register update OK
    • [8]REPOK (def=0x0) // Repetition register update Ok
    • [7]UE (def=0x0) // LPTIM update event occurred
    • [6]DOWN (def=0x0) // Counter direction change up to down
    • [5]UP (def=0x0) // Counter direction change down to up
    • [4]ARROK (def=0x0) // Autoreload register update OK
    • [3]CMP1OK (def=0x0) // Compare register 1 update OK
    • [2]EXTTRIG (def=0x0) // External trigger edge event
    • [1]ARRM (def=0x0) // Autoreload match
    • [0]CC1IF (def=0x0) // Compare 1 interrupt flag
  • 0x56004C04ICR// Interrupt Clear Register

    • [24]DIEROKCF (def=0x0) // Interrupt enable register update OK clear flag
    • [8]REPOKCF (def=0x0) // Repetition register update OK clear flag
    • [7]UECF (def=0x0) // Update event clear flag
    • [6]DOWNCF (def=0x0) // Direction change to down Clear Flag
    • [5]UPCF (def=0x0) // Direction change to UP Clear Flag
    • [4]ARROKCF (def=0x0) // Autoreload register update OK Clear Flag
    • [3]CMP1OKCF (def=0x0) // Compare register 1 update OK Clear Flag
    • [2]EXTTRIGCF (def=0x0) // External trigger valid edge Clear Flag
    • [1]ARRMCF (def=0x0) // Autoreload match Clear Flag
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004C08DIER// LPTIM interrupt Enable Register

    • [8]REPOKIE (def=0x0) // REPOKIE
    • [7]UEIE (def=0x0) // Update event interrupt enable
    • [6]DOWNIE (def=0x0) // Direction change to down Interrupt Enable
    • [5]UPIE (def=0x0) // Direction change to UP Interrupt Enable
    • [4]ARROKIE (def=0x0) // Autoreload register update OK Interrupt Enable
    • [3]CMP1OKIE (def=0x0) // Compare register 1 update OK Interrupt Enable
    • [2]EXTTRIGIE (def=0x0) // External trigger valid edge Interrupt Enable
    • [1]ARRMIE (def=0x0) // Autoreload match Interrupt Enable
    • [0]CC1IF (def=0x0) // Capture/compare 1 clear flag
  • 0x56004C0CCFGR// Configuration Register

    • [24]ENC (def=0x0) // Encoder mode enable
    • [23]COUNTMODE (def=0x0) // counter mode enabled
    • [22]PRELOAD (def=0x0) // Registers update mode
    • [21]WAVPOL (def=0x0) // Waveform shape polarity
    • [20]WAVE (def=0x0) // Waveform shape
    • [19]TIMOUT (def=0x0) // Timeout enable
    • [17:18]TRIGEN (def=0x0) // Trigger enable and polarity
    • [13:15]TRIGSEL (def=0x0) // Trigger selector
    • [9:11]PRESC (def=0x0) // Clock prescaler
    • [6:7]TRGFLT (def=0x0) // Configurable digital filter for trigger
    • [3:4]CKFLT (def=0x0) // Configurable digital filter for external clock
    • [1:2]CKPOL (def=0x0) // Clock Polarity
    • [0]CKSEL (def=0x0) // Clock selector
  • 0x56004C10CR// Control Register

    • [4]RSTARE (def=0x0) // Reset after read enable
    • [3]COUNTRST (def=0x0) // Counter reset
    • [2]CNTSTRT (def=0x0) // Timer start in continuous mode
    • [1]SNGSTRT (def=0x0) // LPTIM start in single mode
    • [0]ENABLE (def=0x0) // LPTIM Enable
  • 0x56004C14CCR1// Compare Register

    • [0:15]CCR1 (def=0x0) // Capture/compare 1 value
  • 0x56004C18ARR// Autoreload Register

    • [0:15]ARR (def=0x1) // Auto reload value
  • 0x56004C1CCNT// Counter Register

    • [0:15]CNT (def=0x0) // Counter value
  • 0x56004C24CFGR2// LPTIM configuration register 2

    • [20:21]IC2SEL (def=0x0) // LPTIM input capture 2 selection
    • [16:17]IC1SEL (def=0x0) // LPTIM input capture 1 selection
    • [4:5]IN2SEL (def=0x0) // LPTIM input 2 selection
    • [0:1]IN1SEL (def=0x0) // LPTIM input 1 selection
  • 0x56004C28RCR// LPTIM repetition register

    • [0:7]REP (def=0x0) // Repetition register value
  • 0x56004C2CCCMR1// LPTIM capture/compare mode register 1

    • [0]CC1SEL (def=0x0) // Capture/compare 1 selection
    • [1]CC1E (def=0x0) // Capture/compare 1 output enable
    • [2:3]CC1P (def=0x0) // Capture/compare 1 output polarity
    • [8:9]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [12:13]IC1F (def=0x0) // Input capture 1 filter
    • [16]CC2SEL (def=0x0) // Capture/compare 2 selection
    • [17]CC2E (def=0x0) // Capture/compare 2 output enable
    • [18:19]CC2P (def=0x0) // Capture/compare 2 output polarity
    • [24:25]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [28:29]IC2F (def=0x0) // Input capture 2 filter
  • 0x56004C34CCR2// LPTIM Compare Register 2

    • [0:15]CCR2 (def=0x0) // Capture/compare 2 value
  • 0x56004FECHWCFGR2// LPTIM peripheral hardware configuration register 2

    • [0:3]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16]CFG3 (def=0x0) // peripheral hardware configuration 3
  • 0x56004FF0HWCFGR1// LPTIM peripheral hardware configuration register 1

    • [0:7]CFG1 (def=0x0) // peripheral hardware configuration 1
    • [8:15]CFG2 (def=0x0) // peripheral hardware configuration 2
    • [16:19]CFG3 (def=0x0) // peripheral hardware configuration 3
    • [24:31]CFG4 (def=0x0) // peripheral hardware configuration 4
• 0x40032C00GTZC1_MPCBB1// GTZC1_MPCBB1

  • 0x40032C00MPCBB1_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x40032C10MPCBB1_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x40032D00MPCBB1_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D04MPCBB1_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D08MPCBB1_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D0CMPCBB1_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D10MPCBB1_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D14MPCBB1_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D18MPCBB1_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D1CMPCBB1_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D20MPCBB1_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D24MPCBB1_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D28MPCBB1_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D2CMPCBB1_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D30MPCBB1_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D34MPCBB1_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D38MPCBB1_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D3CMPCBB1_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D40MPCBB1_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D44MPCBB1_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D48MPCBB1_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D4CMPCBB1_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D50MPCBB1_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D54MPCBB1_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D58MPCBB1_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D5CMPCBB1_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D60MPCBB1_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D64MPCBB1_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D68MPCBB1_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D6CMPCBB1_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D70MPCBB1_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D74MPCBB1_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D78MPCBB1_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032D7CMPCBB1_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40032E00MPCBB1_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E04MPCBB1_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E08MPCBB1_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E0CMPCBB1_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E10MPCBB1_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E14MPCBB1_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E18MPCBB1_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E1CMPCBB1_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E20MPCBB1_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E24MPCBB1_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E28MPCBB1_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E2CMPCBB1_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E30MPCBB1_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E34MPCBB1_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E38MPCBB1_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E3CMPCBB1_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E40MPCBB1_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E44MPCBB1_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E48MPCBB1_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E4CMPCBB1_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E50MPCBB1_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E54MPCBB1_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E58MPCBB1_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E5CMPCBB1_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E60MPCBB1_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E64MPCBB1_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E68MPCBB1_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E6CMPCBB1_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E70MPCBB1_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E74MPCBB1_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E78MPCBB1_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40032E7CMPCBB1_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x50032C00SEC_GTZC1_MPCBB1//

  • 0x50032C00MPCBB1_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x50032C10MPCBB1_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x50032D00MPCBB1_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D04MPCBB1_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D08MPCBB1_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D0CMPCBB1_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D10MPCBB1_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D14MPCBB1_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D18MPCBB1_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D1CMPCBB1_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D20MPCBB1_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D24MPCBB1_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D28MPCBB1_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D2CMPCBB1_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D30MPCBB1_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D34MPCBB1_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D38MPCBB1_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D3CMPCBB1_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D40MPCBB1_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D44MPCBB1_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D48MPCBB1_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D4CMPCBB1_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D50MPCBB1_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D54MPCBB1_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D58MPCBB1_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D5CMPCBB1_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D60MPCBB1_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D64MPCBB1_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D68MPCBB1_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D6CMPCBB1_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D70MPCBB1_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D74MPCBB1_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D78MPCBB1_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032D7CMPCBB1_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50032E00MPCBB1_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E04MPCBB1_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E08MPCBB1_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E0CMPCBB1_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E10MPCBB1_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E14MPCBB1_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E18MPCBB1_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E1CMPCBB1_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E20MPCBB1_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E24MPCBB1_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E28MPCBB1_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E2CMPCBB1_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E30MPCBB1_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E34MPCBB1_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E38MPCBB1_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E3CMPCBB1_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E40MPCBB1_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E44MPCBB1_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E48MPCBB1_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E4CMPCBB1_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E50MPCBB1_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E54MPCBB1_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E58MPCBB1_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E5CMPCBB1_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E60MPCBB1_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E64MPCBB1_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E68MPCBB1_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E6CMPCBB1_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E70MPCBB1_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E74MPCBB1_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E78MPCBB1_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50032E7CMPCBB1_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x40033000GTZC1_MPCBB2// GTZC1_MPCBB2

  • 0x40033000MPCBB2_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x40033010MPCBB2_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x40033100MPCBB2_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033104MPCBB2_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033108MPCBB2_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003310CMPCBB2_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033110MPCBB2_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033114MPCBB2_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033118MPCBB2_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003311CMPCBB2_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033120MPCBB2_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033124MPCBB2_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033128MPCBB2_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003312CMPCBB2_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033130MPCBB2_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033134MPCBB2_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033138MPCBB2_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003313CMPCBB2_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033140MPCBB2_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033144MPCBB2_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033148MPCBB2_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003314CMPCBB2_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033150MPCBB2_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033154MPCBB2_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033158MPCBB2_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003315CMPCBB2_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033160MPCBB2_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033164MPCBB2_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033168MPCBB2_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003316CMPCBB2_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033170MPCBB2_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033174MPCBB2_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033178MPCBB2_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003317CMPCBB2_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033200MPCBB2_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033204MPCBB2_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033208MPCBB2_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003320CMPCBB2_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033210MPCBB2_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033214MPCBB2_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033218MPCBB2_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003321CMPCBB2_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033220MPCBB2_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033224MPCBB2_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033228MPCBB2_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003322CMPCBB2_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033230MPCBB2_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033234MPCBB2_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033238MPCBB2_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003323CMPCBB2_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033240MPCBB2_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033244MPCBB2_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033248MPCBB2_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003324CMPCBB2_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033250MPCBB2_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033254MPCBB2_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033258MPCBB2_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003325CMPCBB2_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033260MPCBB2_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033264MPCBB2_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033268MPCBB2_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003326CMPCBB2_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033270MPCBB2_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033274MPCBB2_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033278MPCBB2_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003327CMPCBB2_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x50033000SEC_GTZC1_MPCBB2//

  • 0x50033000MPCBB2_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x50033010MPCBB2_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x50033100MPCBB2_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033104MPCBB2_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033108MPCBB2_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003310CMPCBB2_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033110MPCBB2_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033114MPCBB2_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033118MPCBB2_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003311CMPCBB2_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033120MPCBB2_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033124MPCBB2_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033128MPCBB2_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003312CMPCBB2_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033130MPCBB2_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033134MPCBB2_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033138MPCBB2_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003313CMPCBB2_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033140MPCBB2_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033144MPCBB2_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033148MPCBB2_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003314CMPCBB2_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033150MPCBB2_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033154MPCBB2_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033158MPCBB2_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003315CMPCBB2_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033160MPCBB2_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033164MPCBB2_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033168MPCBB2_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003316CMPCBB2_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033170MPCBB2_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033174MPCBB2_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033178MPCBB2_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003317CMPCBB2_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033200MPCBB2_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033204MPCBB2_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033208MPCBB2_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003320CMPCBB2_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033210MPCBB2_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033214MPCBB2_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033218MPCBB2_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003321CMPCBB2_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033220MPCBB2_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033224MPCBB2_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033228MPCBB2_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003322CMPCBB2_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033230MPCBB2_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033234MPCBB2_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033238MPCBB2_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003323CMPCBB2_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033240MPCBB2_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033244MPCBB2_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033248MPCBB2_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003324CMPCBB2_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033250MPCBB2_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033254MPCBB2_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033258MPCBB2_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003325CMPCBB2_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033260MPCBB2_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033264MPCBB2_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033268MPCBB2_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003326CMPCBB2_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033270MPCBB2_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033274MPCBB2_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033278MPCBB2_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003327CMPCBB2_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x40033400GTZC1_MPCBB3// GTZC1_MPCBB3

  • 0x40033400MPCBB3_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x40033410MPCBB3_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x40033500MPCBB3_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033504MPCBB3_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033508MPCBB3_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003350CMPCBB3_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033510MPCBB3_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033514MPCBB3_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033518MPCBB3_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003351CMPCBB3_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033520MPCBB3_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033524MPCBB3_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033528MPCBB3_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003352CMPCBB3_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033530MPCBB3_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033534MPCBB3_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033538MPCBB3_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003353CMPCBB3_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033540MPCBB3_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033544MPCBB3_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033548MPCBB3_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003354CMPCBB3_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033550MPCBB3_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033554MPCBB3_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033558MPCBB3_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003355CMPCBB3_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033560MPCBB3_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033564MPCBB3_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033568MPCBB3_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003356CMPCBB3_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033570MPCBB3_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033574MPCBB3_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033578MPCBB3_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x4003357CMPCBB3_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x40033600MPCBB3_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033604MPCBB3_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033608MPCBB3_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003360CMPCBB3_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033610MPCBB3_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033614MPCBB3_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033618MPCBB3_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003361CMPCBB3_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033620MPCBB3_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033624MPCBB3_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033628MPCBB3_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003362CMPCBB3_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033630MPCBB3_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033634MPCBB3_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033638MPCBB3_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003363CMPCBB3_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033640MPCBB3_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033644MPCBB3_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033648MPCBB3_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003364CMPCBB3_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033650MPCBB3_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033654MPCBB3_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033658MPCBB3_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003365CMPCBB3_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033660MPCBB3_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033664MPCBB3_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033668MPCBB3_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003366CMPCBB3_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033670MPCBB3_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033674MPCBB3_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x40033678MPCBB3_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x4003367CMPCBB3_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x50033400SEC_GTZC1_MPCBB3//

  • 0x50033400MPCBB3_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x50033410MPCBB3_CFGLOCKR1// GTZC1 SRAMz MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // SPLCK0
    • [1]SPLCK1 (def=0x0) // SPLCK1
    • [2]SPLCK2 (def=0x0) // SPLCK2
    • [3]SPLCK3 (def=0x0) // SPLCK3
    • [4]SPLCK4 (def=0x0) // SPLCK4
    • [5]SPLCK5 (def=0x0) // SPLCK5
    • [6]SPLCK6 (def=0x0) // SPLCK6
    • [7]SPLCK7 (def=0x0) // SPLCK7
    • [8]SPLCK8 (def=0x0) // SPLCK8
    • [9]SPLCK9 (def=0x0) // SPLCK9
    • [10]SPLCK10 (def=0x0) // SPLCK10
    • [11]SPLCK11 (def=0x0) // SPLCK11
    • [12]SPLCK12 (def=0x0) // SPLCK12
    • [13]SPLCK13 (def=0x0) // SPLCK13
    • [14]SPLCK14 (def=0x0) // SPLCK14
    • [15]SPLCK15 (def=0x0) // SPLCK15
    • [16]SPLCK16 (def=0x0) // SPLCK16
    • [17]SPLCK17 (def=0x0) // SPLCK17
    • [18]SPLCK18 (def=0x0) // SPLCK18
    • [19]SPLCK19 (def=0x0) // SPLCK19
    • [20]SPLCK20 (def=0x0) // SPLCK20
    • [21]SPLCK21 (def=0x0) // SPLCK21
    • [22]SPLCK22 (def=0x0) // SPLCK22
    • [23]SPLCK23 (def=0x0) // SPLCK23
    • [24]SPLCK24 (def=0x0) // SPLCK24
    • [25]SPLCK25 (def=0x0) // SPLCK25
    • [26]SPLCK26 (def=0x0) // SPLCK26
    • [27]SPLCK27 (def=0x0) // SPLCK27
    • [28]SPLCK28 (def=0x0) // SPLCK28
    • [29]SPLCK29 (def=0x0) // SPLCK29
    • [30]SPLCK30 (def=0x0) // SPLCK30
    • [31]SPLCK31 (def=0x0) // SPLCK31
  • 0x50033500MPCBB3_SECCFGR0// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033504MPCBB3_SECCFGR1// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033508MPCBB3_SECCFGR2// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003350CMPCBB3_SECCFGR3// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033510MPCBB3_SECCFGR4// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033514MPCBB3_SECCFGR5// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033518MPCBB3_SECCFGR6// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003351CMPCBB3_SECCFGR7// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033520MPCBB3_SECCFGR8// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033524MPCBB3_SECCFGR9// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033528MPCBB3_SECCFGR10// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003352CMPCBB3_SECCFGR11// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033530MPCBB3_SECCFGR12// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033534MPCBB3_SECCFGR13// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033538MPCBB3_SECCFGR14// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003353CMPCBB3_SECCFGR15// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033540MPCBB3_SECCFGR16// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033544MPCBB3_SECCFGR17// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033548MPCBB3_SECCFGR18// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003354CMPCBB3_SECCFGR19// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033550MPCBB3_SECCFGR20// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033554MPCBB3_SECCFGR21// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033558MPCBB3_SECCFGR22// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003355CMPCBB3_SECCFGR23// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033560MPCBB3_SECCFGR24// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033564MPCBB3_SECCFGR25// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033568MPCBB3_SECCFGR26// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003356CMPCBB3_SECCFGR27// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033570MPCBB3_SECCFGR28// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033574MPCBB3_SECCFGR29// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033578MPCBB3_SECCFGR30// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x5003357CMPCBB3_SECCFGR31// MPCBBx security configuration for super-block x register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x50033600MPCBB3_PRIVCFGR0// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033604MPCBB3_PRIVCFGR1// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033608MPCBB3_PRIVCFGR2// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003360CMPCBB3_PRIVCFGR3// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033610MPCBB3_PRIVCFGR4// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033614MPCBB3_PRIVCFGR5// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033618MPCBB3_PRIVCFGR6// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003361CMPCBB3_PRIVCFGR7// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033620MPCBB3_PRIVCFGR8// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033624MPCBB3_PRIVCFGR9// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033628MPCBB3_PRIVCFGR10// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003362CMPCBB3_PRIVCFGR11// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033630MPCBB3_PRIVCFGR12// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033634MPCBB3_PRIVCFGR13// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033638MPCBB3_PRIVCFGR14// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003363CMPCBB3_PRIVCFGR15// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033640MPCBB3_PRIVCFGR16// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033644MPCBB3_PRIVCFGR17// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033648MPCBB3_PRIVCFGR18// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003364CMPCBB3_PRIVCFGR19// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033650MPCBB3_PRIVCFGR20// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033654MPCBB3_PRIVCFGR21// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033658MPCBB3_PRIVCFGR22// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003365CMPCBB3_PRIVCFGR23// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033660MPCBB3_PRIVCFGR24// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033664MPCBB3_PRIVCFGR25// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033668MPCBB3_PRIVCFGR26// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003366CMPCBB3_PRIVCFGR27// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033670MPCBB3_PRIVCFGR28// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033674MPCBB3_PRIVCFGR29// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x50033678MPCBB3_PRIVCFGR30// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
  • 0x5003367CMPCBB3_PRIVCFGR31// MPCBB privileged configuration for super-block x register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x40032800GTZC1_TZIC// GTZC1_TZIC

  • 0x40032800IER1// TZIC interrupt enable register 1

    • [0]TIM2IE (def=0x0) // TIM2IE
    • [1]TIM3IE (def=0x0) // TIM3IE
    • [2]TIM4IE (def=0x0) // TIM4IE
    • [3]TIM5IE (def=0x0) // TIM5IE
    • [4]TIM6IE (def=0x0) // TIM6IE
    • [5]TIM7IE (def=0x0) // TIM7IE
    • [6]WWDGIE (def=0x0) // WWDGIE
    • [7]IWDGIE (def=0x0) // IWDGIE
    • [8]SPI2IE (def=0x0) // SPI2IE
    • [9]USART2IE (def=0x0) // illegal access interrupt enable for USART2
    • [10]USART3IE (def=0x0) // illegal access interrupt enable for USART3
    • [11]USART4IE (def=0x0) // illegal access interrupt enable for UART4
    • [12]UART5IE (def=0x0) // illegal access interrupt enable for UART5
    • [13]I2C1IE (def=0x0) // illegal access interrupt enable for I2C1
    • [14]I2C2IE (def=0x0) // illegal access interrupt enable for I2C2
    • [15]CRSIE (def=0x0) // illegal access interrupt enable for CRS
    • [16]I2C4IE (def=0x0) // illegal access interrupt enable for I2C4
    • [17]LPTIM2IE (def=0x0) // illegal access interrupt enable for LPTIM2
    • [18]FDCAN1IE (def=0x0) // illegal access interrupt enable for FDCAN1
    • [19]UCPD1IE (def=0x0) // illegal access interrupt enable for UCPD1
  • 0x40032804IER2// TZIC interrupt enable register 2

    • [0]TIM1IE (def=0x0) // illegal access interrupt enable for TIM1
    • [1]SPI1IE (def=0x0) // illegal access interrupt enable for SPI1
    • [2]TIM8IE (def=0x0) // illegal access interrupt enable for TIM8
    • [3]USART1IE (def=0x0) // illegal access interrupt enable for USART1
    • [4]TIM15IE (def=0x0) // illegal access interrupt enable for TIM5
    • [5]TIM16IE (def=0x0) // illegal access interrupt enable for TIM6
    • [6]TIM17IE (def=0x0) // illegal access interrupt enable for TIM7
    • [7]SAI1IE (def=0x0) // illegal access interrupt enable for SAI1
    • [8]SAI2IE (def=0x0) // illegal access interrupt enable for SAI2
  • 0x40032808IER3// TZIC interrupt enable register 3

    • [0]MDF1IE (def=0x0) // illegal access interrupt enable for MDF1
    • [1]CORDICIE (def=0x0) // illegal access interrupt enable for CORDIC
    • [2]FMACIE (def=0x0) // illegal access interrupt enable for FMAC
    • [3]CRCIE (def=0x0) // illegal access interrupt enable for CRC
    • [4]TSCIE (def=0x0) // illegal access interrupt enable for TSC
    • [5]DMA2DIE (def=0x0) // illegal access interrupt enable for register of DMA2D
    • [6]ICACHEIE (def=0x0) // illegal access interrupt enable for ICACHE registers
    • [7]DCACHEIE (def=0x0) // illegal access interrupt enable for DCACHE registers
    • [8]ADC1IE (def=0x0) // illegal access interrupt enable for ADC1
    • [9]DCMIIE (def=0x0) // illegal access interrupt enable for DCMI
    • [10]OTGFSIE (def=0x0) // illegal access interrupt enable for OTG_FS
    • [11]AESIE (def=0x0) // illegal access interrupt enable for AES
    • [12]HASHIE (def=0x0) // illegal access interrupt enable for HASH
    • [13]RNGIE (def=0x0) // illegal access interrupt enable for RNG
    • [14]PKAIE (def=0x0) // illegal access interrupt enable for PKA
    • [15]SAESIE (def=0x0) // illegal access interrupt enable for SAES
    • [16]OCTOSPIMIE (def=0x0) // illegal access interrupt enable for OCTOSPIM
    • [17]SDMMC1IE (def=0x0) // illegal access interrupt enable for SDMMC2
    • [18]SDMMC2IE (def=0x0) // illegal access interrupt enable for SDMMC1
    • [19]FSMCIE (def=0x0) // illegal access interrupt enable for FSMC registers
    • [20]OCTOSPI1IE (def=0x0) // illegal access interrupt enable for OCTOSPI1 registers
    • [21]OCTOSPI2IE (def=0x0) // illegal access interrupt enable for OCTOSPI2 registers
    • [22]RAMCFGIE (def=0x0) // illegal access interrupt enable for RAMCFG
  • 0x4003280CIER4// TZIC interrupt enable register 4

    • [0]GPDMA1IE (def=0x0) // illegal access interrupt enable for GPDMA1
    • [1]FLASH_REGIE (def=0x0) // illegal access interrupt enable for FLASH registers
    • [2]FLASHIE (def=0x0) // illegal access interrupt enable for FLASH memory
    • [3]OTFDEC1IE (def=0x0) // illegal access interrupt enable for OTFDEC1
    • [4]OTFDEC2IE (def=0x0) // illegal access interrupt enable for OTFDEC2
    • [14]TZSC1IE (def=0x0) // illegal access interrupt enable for GTZC1 TZSC registers
    • [15]TZIC1IE (def=0x0) // illegal access interrupt enable for GTZC1 TZIC registers
    • [16]OCTOSPI1_MEMIE (def=0x0) // illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank
    • [17]FSMC_MEMIE (def=0x0) // illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3
    • [18]BKPSRAMIE (def=0x0) // illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank
    • [19]OCTOSPI2_MEMIE (def=0x0) // illegal access interrupt enable for OCTOSPI2 memory bank
    • [24]SRAM1IE (def=0x0) // illegal access interrupt enable for SRAM1
    • [25]MPCBB1_REGIE (def=0x0) // illegal access interrupt enable for MPCBB1 registers
    • [26]SRAM2IE (def=0x0) // illegal access interrupt enable for SRAM2
    • [27]MPCBB2_REGIE (def=0x0) // illegal access interrupt enable for MPCBB2 registers
    • [28]SRAM3IE (def=0x0) // illegal access interrupt enable for SRAM3
    • [29]MPCBB3_REGIE (def=0x0) // illegal access interrupt enable for MPCBB3 registers
  • 0x40032810SR1// TZIC status register 1

    • [0]TIM2F (def=0x0) // illegal access flag for TIM2
    • [1]TIM3F (def=0x0) // illegal access flag for TIM3
    • [2]TIM4F (def=0x0) // illegal access flag for TIM4
    • [3]TIM5F (def=0x0) // illegal access flag for TIM5
    • [4]TIM6F (def=0x0) // illegal access flag for TIM6
    • [5]TIM7F (def=0x0) // illegal access flag for TIM7
    • [6]WWDGF (def=0x0) // illegal access flag for WWDG
    • [7]IWDGF (def=0x0) // illegal access flag for IWDG
    • [8]SPI2F (def=0x0) // illegal access flag for SPI2
    • [9]USART2F (def=0x0) // illegal access flag for USART2
    • [10]USART3F (def=0x0) // illegal access flag for USART3
    • [11]UART4F (def=0x0) // illegal access flag for UART4
    • [12]UART5F (def=0x0) // illegal access flag for UART5
    • [13]I2C1F (def=0x0) // illegal access flag for I2C1
    • [14]I2C2F (def=0x0) // illegal access flag for I2C2
    • [15]CRSF (def=0x0) // illegal access flag for CRS
    • [16]I2C4F (def=0x0) // illegal access flag for I2C4
    • [17]LPTIM2F (def=0x0) // illegal access flag for LPTIM2
    • [18]FDCAN1F (def=0x0) // illegal access flag for FDCAN1
    • [19]UCPD1F (def=0x0) // illegal access flag for UCPD1
  • 0x40032814SR2// TZIC status register 2

    • [0]TIM1F (def=0x0) // illegal access flag for TIM1
    • [1]SPI1F (def=0x0) // illegal access flag for SPI1
    • [2]TIM8F (def=0x0) // illegal access flag for TIM8
    • [3]USART1F (def=0x0) // illegal access flag for USART1
    • [4]TIM15F (def=0x0) // illegal access flag for TIM5
    • [5]TIM16F (def=0x0) // illegal access flag for TIM6
    • [6]TIM17F (def=0x0) // illegal access flag for TIM7
    • [7]SAI1F (def=0x0) // illegal access flag for SAI1
    • [8]SAI2F (def=0x0) // illegal access flag for SAI2
  • 0x40032818SR3// TZIC status register 3

    • [0]MDF1F (def=0x0) // illegal access flag for MDF1
    • [1]CORDICF (def=0x0) // illegal access flag for CORDIC
    • [2]FMACF (def=0x0) // illegal access flag for FMAC
    • [3]CRCF (def=0x0) // illegal access flag for CRC
    • [4]TSCF (def=0x0) // illegal access flag for TSC
    • [5]DMA2DF (def=0x0) // illegal access flag for register of DMA2D
    • [6]ICACHEF (def=0x0) // illegal access flag for ICACHE registers
    • [7]DCACHEF (def=0x0) // illegal access flag for DCACHE registers
    • [8]ADC1F (def=0x0) // illegal access flag for ADC1
    • [9]DCMIF (def=0x0) // illegal access flag for DCMI
    • [10]OTGFSF (def=0x0) // illegal access flag for OTG_FS
    • [11]AESF (def=0x0) // illegal access flag for AES
    • [12]HASHF (def=0x0) // illegal access flag for HASH
    • [13]RNGF (def=0x0) // illegal access flag for RNG
    • [14]PKAF (def=0x0) // illegal access flag for PKA
    • [15]SAESF (def=0x0) // illegal access flag for SAES
    • [16]OCTOSPIMF (def=0x0) // illegal access flag for OCTOSPIM
    • [17]SDMMC1F (def=0x0) // illegal access flag for SDMMC2
    • [18]SDMMC2F (def=0x0) // illegal access flag for SDMMC1
    • [19]FSMCF (def=0x0) // illegal access flag for FSMC registers
    • [20]OCTOSPI1F (def=0x0) // illegal access flag for OCTOSPI1 registers
    • [21]OCTOSPI2F (def=0x0) // illegal access flag for OCTOSPI2 registers
    • [22]RAMCFGF (def=0x0) // illegal access flag for RAMCFG
  • 0x4003281CSR4// TZIC status register 4

    • [0]GPDMA1F (def=0x0) // illegal access flag for GPDMA1
    • [1]FLASH_REGF (def=0x0) // illegal access flag for FLASH registers
    • [2]FLASHF (def=0x0) // illegal access flag for FLASH memory
    • [3]OTFDEC1F (def=0x0) // illegal access flag for OTFDEC1
    • [4]OTFDEC2F (def=0x0) // illegal access flag for OTFDEC2
    • [14]TZSC1F (def=0x0) // illegal access flag for GTZC1 TZSC registers
    • [15]TZIC1F (def=0x0) // illegal access flag for GTZC1 TZIC registers
    • [16]OCTOSPI1_MEMF (def=0x0) // illegal access flag for MPCWM1 (OCTOSPI1) memory bank
    • [17]FSMC_MEMF (def=0x0) // illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)
    • [18]BKPSRAMF (def=0x0) // illegal access flag for MPCWM3 (BKPSRAM) memory bank
    • [19]OCTOSPI2_MEMF (def=0x0) // illegal access flag for OCTOSPI2 memory bank
    • [24]SRAM1F (def=0x0) // illegal access flag for SRAM1
    • [25]MPCBB1_REGF (def=0x0) // illegal access flag for MPCBB1 registers
    • [26]SRAM2F (def=0x0) // illegal access flag for SRAM2
    • [27]MPCBB2_REGF (def=0x0) // illegal access flag for MPCBB2 registers
    • [28]SRAM3F (def=0x0) // illegal access flag for SRAM3
    • [29]MPCBB3_REGF (def=0x0) // illegal access flag for MPCBB3 registers
  • 0x40032820FCR1// TZIC flag clear register 1

    • [0]CTIM2F (def=0x0) // clear the illegal access flag for TIM2
    • [1]CTIM3F (def=0x0) // clear the illegal access flag for TIM3
    • [2]CTIM4F (def=0x0) // clear the illegal access flag for TIM4
    • [3]CTIM5F (def=0x0) // clear the illegal access flag for TIM5
    • [4]CTIM6F (def=0x0) // clear the illegal access flag for TIM6
    • [5]CTIM7F (def=0x0) // clear the illegal access flag for TIM7
    • [6]CWWDGF (def=0x0) // clear the illegal access flag for WWDG
    • [7]CIWDGF (def=0x0) // clear the illegal access flag for IWDG
    • [8]CSPI2F (def=0x0) // clear the illegal access flag for SPI2
    • [9]CUSART2F (def=0x0) // clear the illegal access flag for USART2
    • [10]CUSART3F (def=0x0) // clear the illegal access flag for USART3
    • [11]CUART4F (def=0x0) // clear the illegal access flag for UART4
    • [12]CUART5F (def=0x0) // clear the illegal access flag for UART5
    • [13]CI2C1F (def=0x0) // clear the illegal access flag for I2C1
    • [14]CI2C2F (def=0x0) // clear the illegal access flag for I2C2
    • [15]CCRSF (def=0x0) // clear the illegal access flag for CRS
    • [16]CI2C4F (def=0x0) // clear the illegal access flag for I2C4
    • [17]CLPTIM2F (def=0x0) // clear the illegal access flag for LPTIM2
    • [18]CFDCAN1F (def=0x0) // clear the illegal access flag for FDCAN1
    • [19]CUCPD1F (def=0x0) // clear the illegal access flag for UCPD1
  • 0x40032824FCR2// TZIC flag clear register 2

    • [0]CTIM1F (def=0x0) // clear the illegal access flag for TIM1
    • [1]CSPI1F (def=0x0) // clear the illegal access flag for SPI1
    • [2]CTIM8F (def=0x0) // clear the illegal access flag for TIM8
    • [3]CUSART1F (def=0x0) // clear the illegal access flag for USART1
    • [4]CTIM15F (def=0x0) // clear the illegal access flag for TIM5
    • [5]CTIM16F (def=0x0) // clear the illegal access flag for TIM6
    • [6]CTIM17F (def=0x0) // clear the illegal access flag for TIM7
    • [7]CSAI1F (def=0x0) // clear the illegal access flag for SAI1
    • [8]CSAI2F (def=0x0) // clear the illegal access flag for SAI2
  • 0x40032828FCR3// TZIC flag clear register 3

    • [0]CMDF1F (def=0x0) // clear the illegal access flag for MDF1
    • [1]CCORDICF (def=0x0) // clear the illegal access flag for CORDIC
    • [2]CFMACF (def=0x0) // clear the illegal access flag for FMAC
    • [3]CCRCF (def=0x0) // clear the illegal access flag for CRC
    • [4]CTSCF (def=0x0) // clear the illegal access flag for TSC
    • [5]CDMA2DF (def=0x0) // clear the illegal access flag for register of DMA2D
    • [6]CICACHEF (def=0x0) // clear the illegal access flag for ICACHE registers
    • [7]CDCACHEF (def=0x0) // clear the illegal access flag for DCACHE registers
    • [8]CADC1F (def=0x0) // clear the illegal access flag for ADC1
    • [9]CDCMIF (def=0x0) // clear the illegal access flag for DCMI
    • [10]COTGFSF (def=0x0) // clear the illegal access flag for OTG_FS
    • [11]CAESF (def=0x0) // clear the illegal access flag for AES
    • [12]CHASHF (def=0x0) // clear the illegal access flag for HASH
    • [13]CRNGF (def=0x0) // clear the illegal access flag for RNG
    • [14]CPKAF (def=0x0) // clear the illegal access flag for PKA
    • [15]CSAESF (def=0x0) // clear the illegal access flag for SAES
    • [16]COCTOSPIMF (def=0x0) // clear the illegal access flag for OCTOSPIM
    • [17]CSDMMC1F (def=0x0) // clear the illegal access flag for SDMMC2
    • [18]CSDMMC2F (def=0x0) // clear the illegal access flag for SDMMC1
    • [19]CFSMCF (def=0x0) // clear the illegal access flag for FSMC registers
    • [20]COCTOSPI1F (def=0x0) // clear the illegal access flag for OCTOSPI1 registers
    • [21]COCTOSPI2F (def=0x0) // clear the illegal access flag for OCTOSPI2 registers
    • [22]CRAMCFGF (def=0x0) // clear the illegal access flag for RAMCFG
  • 0x4003282CFCR4// TZIC flag clear register 3

    • [0]CGPDMA1F (def=0x0) // clear the illegal access flag for GPDMA1
    • [1]CFLASH_REGF (def=0x0) // clear the illegal access flag for FLASH registers
    • [2]CFLASHF (def=0x0) // clear the illegal access flag for FLASH memory
    • [3]COTFDEC1F (def=0x0) // clear the illegal access flag for OTFDEC1
    • [4]COTFDEC2F (def=0x0) // clear the illegal access flag for OTFDEC2
    • [14]CTZSC1F (def=0x0) // clear the illegal access flag for GTZC1 TZSC registers
    • [15]CTZIC1F (def=0x0) // clear the illegal access flag for GTZC1 TZIC registers
    • [16]COCTOSPI1_MEMF (def=0x0) // clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank
    • [17]CFSMC_MEMF (def=0x0) // clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3
    • [18]CBKPSRAMF (def=0x0) // clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank
    • [19]COCTOSPI2_MEMF (def=0x0) // clear the illegal access flag for OCTOSPI2 memory bank
    • [24]CSRAM1F (def=0x0) // clear the illegal access flag for SRAM1
    • [25]CMPCBB1_REGF (def=0x0) // clear the illegal access flag for MPCBB1 registers
    • [26]CSRAM2F (def=0x0) // clear the illegal access flag for SRAM2
    • [27]CMPCBB2_REGF (def=0x0) // clear the illegal access flag for MPCBB2 registers
    • [28]CSRAM3F (def=0x0) // clear the illegal access flag for SRAM3
    • [29]CMPCBB3_REGF (def=0x0) // clear the illegal access flag for MPCBB3 registers
• 0x50032800SEC_GTZC1_TZIC//

  • 0x50032800IER1// TZIC interrupt enable register 1

    • [0]TIM2IE (def=0x0) // TIM2IE
    • [1]TIM3IE (def=0x0) // TIM3IE
    • [2]TIM4IE (def=0x0) // TIM4IE
    • [3]TIM5IE (def=0x0) // TIM5IE
    • [4]TIM6IE (def=0x0) // TIM6IE
    • [5]TIM7IE (def=0x0) // TIM7IE
    • [6]WWDGIE (def=0x0) // WWDGIE
    • [7]IWDGIE (def=0x0) // IWDGIE
    • [8]SPI2IE (def=0x0) // SPI2IE
    • [9]USART2IE (def=0x0) // illegal access interrupt enable for USART2
    • [10]USART3IE (def=0x0) // illegal access interrupt enable for USART3
    • [11]USART4IE (def=0x0) // illegal access interrupt enable for UART4
    • [12]UART5IE (def=0x0) // illegal access interrupt enable for UART5
    • [13]I2C1IE (def=0x0) // illegal access interrupt enable for I2C1
    • [14]I2C2IE (def=0x0) // illegal access interrupt enable for I2C2
    • [15]CRSIE (def=0x0) // illegal access interrupt enable for CRS
    • [16]I2C4IE (def=0x0) // illegal access interrupt enable for I2C4
    • [17]LPTIM2IE (def=0x0) // illegal access interrupt enable for LPTIM2
    • [18]FDCAN1IE (def=0x0) // illegal access interrupt enable for FDCAN1
    • [19]UCPD1IE (def=0x0) // illegal access interrupt enable for UCPD1
  • 0x50032804IER2// TZIC interrupt enable register 2

    • [0]TIM1IE (def=0x0) // illegal access interrupt enable for TIM1
    • [1]SPI1IE (def=0x0) // illegal access interrupt enable for SPI1
    • [2]TIM8IE (def=0x0) // illegal access interrupt enable for TIM8
    • [3]USART1IE (def=0x0) // illegal access interrupt enable for USART1
    • [4]TIM15IE (def=0x0) // illegal access interrupt enable for TIM5
    • [5]TIM16IE (def=0x0) // illegal access interrupt enable for TIM6
    • [6]TIM17IE (def=0x0) // illegal access interrupt enable for TIM7
    • [7]SAI1IE (def=0x0) // illegal access interrupt enable for SAI1
    • [8]SAI2IE (def=0x0) // illegal access interrupt enable for SAI2
  • 0x50032808IER3// TZIC interrupt enable register 3

    • [0]MDF1IE (def=0x0) // illegal access interrupt enable for MDF1
    • [1]CORDICIE (def=0x0) // illegal access interrupt enable for CORDIC
    • [2]FMACIE (def=0x0) // illegal access interrupt enable for FMAC
    • [3]CRCIE (def=0x0) // illegal access interrupt enable for CRC
    • [4]TSCIE (def=0x0) // illegal access interrupt enable for TSC
    • [5]DMA2DIE (def=0x0) // illegal access interrupt enable for register of DMA2D
    • [6]ICACHEIE (def=0x0) // illegal access interrupt enable for ICACHE registers
    • [7]DCACHEIE (def=0x0) // illegal access interrupt enable for DCACHE registers
    • [8]ADC1IE (def=0x0) // illegal access interrupt enable for ADC1
    • [9]DCMIIE (def=0x0) // illegal access interrupt enable for DCMI
    • [10]OTGFSIE (def=0x0) // illegal access interrupt enable for OTG_FS
    • [11]AESIE (def=0x0) // illegal access interrupt enable for AES
    • [12]HASHIE (def=0x0) // illegal access interrupt enable for HASH
    • [13]RNGIE (def=0x0) // illegal access interrupt enable for RNG
    • [14]PKAIE (def=0x0) // illegal access interrupt enable for PKA
    • [15]SAESIE (def=0x0) // illegal access interrupt enable for SAES
    • [16]OCTOSPIMIE (def=0x0) // illegal access interrupt enable for OCTOSPIM
    • [17]SDMMC1IE (def=0x0) // illegal access interrupt enable for SDMMC2
    • [18]SDMMC2IE (def=0x0) // illegal access interrupt enable for SDMMC1
    • [19]FSMCIE (def=0x0) // illegal access interrupt enable for FSMC registers
    • [20]OCTOSPI1IE (def=0x0) // illegal access interrupt enable for OCTOSPI1 registers
    • [21]OCTOSPI2IE (def=0x0) // illegal access interrupt enable for OCTOSPI2 registers
    • [22]RAMCFGIE (def=0x0) // illegal access interrupt enable for RAMCFG
  • 0x5003280CIER4// TZIC interrupt enable register 4

    • [0]GPDMA1IE (def=0x0) // illegal access interrupt enable for GPDMA1
    • [1]FLASH_REGIE (def=0x0) // illegal access interrupt enable for FLASH registers
    • [2]FLASHIE (def=0x0) // illegal access interrupt enable for FLASH memory
    • [3]OTFDEC1IE (def=0x0) // illegal access interrupt enable for OTFDEC1
    • [4]OTFDEC2IE (def=0x0) // illegal access interrupt enable for OTFDEC2
    • [14]TZSC1IE (def=0x0) // illegal access interrupt enable for GTZC1 TZSC registers
    • [15]TZIC1IE (def=0x0) // illegal access interrupt enable for GTZC1 TZIC registers
    • [16]OCTOSPI1_MEMIE (def=0x0) // illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank
    • [17]FSMC_MEMIE (def=0x0) // illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3
    • [18]BKPSRAMIE (def=0x0) // illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank
    • [19]OCTOSPI2_MEMIE (def=0x0) // illegal access interrupt enable for OCTOSPI2 memory bank
    • [24]SRAM1IE (def=0x0) // illegal access interrupt enable for SRAM1
    • [25]MPCBB1_REGIE (def=0x0) // illegal access interrupt enable for MPCBB1 registers
    • [26]SRAM2IE (def=0x0) // illegal access interrupt enable for SRAM2
    • [27]MPCBB2_REGIE (def=0x0) // illegal access interrupt enable for MPCBB2 registers
    • [28]SRAM3IE (def=0x0) // illegal access interrupt enable for SRAM3
    • [29]MPCBB3_REGIE (def=0x0) // illegal access interrupt enable for MPCBB3 registers
  • 0x50032810SR1// TZIC status register 1

    • [0]TIM2F (def=0x0) // illegal access flag for TIM2
    • [1]TIM3F (def=0x0) // illegal access flag for TIM3
    • [2]TIM4F (def=0x0) // illegal access flag for TIM4
    • [3]TIM5F (def=0x0) // illegal access flag for TIM5
    • [4]TIM6F (def=0x0) // illegal access flag for TIM6
    • [5]TIM7F (def=0x0) // illegal access flag for TIM7
    • [6]WWDGF (def=0x0) // illegal access flag for WWDG
    • [7]IWDGF (def=0x0) // illegal access flag for IWDG
    • [8]SPI2F (def=0x0) // illegal access flag for SPI2
    • [9]USART2F (def=0x0) // illegal access flag for USART2
    • [10]USART3F (def=0x0) // illegal access flag for USART3
    • [11]UART4F (def=0x0) // illegal access flag for UART4
    • [12]UART5F (def=0x0) // illegal access flag for UART5
    • [13]I2C1F (def=0x0) // illegal access flag for I2C1
    • [14]I2C2F (def=0x0) // illegal access flag for I2C2
    • [15]CRSF (def=0x0) // illegal access flag for CRS
    • [16]I2C4F (def=0x0) // illegal access flag for I2C4
    • [17]LPTIM2F (def=0x0) // illegal access flag for LPTIM2
    • [18]FDCAN1F (def=0x0) // illegal access flag for FDCAN1
    • [19]UCPD1F (def=0x0) // illegal access flag for UCPD1
  • 0x50032814SR2// TZIC status register 2

    • [0]TIM1F (def=0x0) // illegal access flag for TIM1
    • [1]SPI1F (def=0x0) // illegal access flag for SPI1
    • [2]TIM8F (def=0x0) // illegal access flag for TIM8
    • [3]USART1F (def=0x0) // illegal access flag for USART1
    • [4]TIM15F (def=0x0) // illegal access flag for TIM5
    • [5]TIM16F (def=0x0) // illegal access flag for TIM6
    • [6]TIM17F (def=0x0) // illegal access flag for TIM7
    • [7]SAI1F (def=0x0) // illegal access flag for SAI1
    • [8]SAI2F (def=0x0) // illegal access flag for SAI2
  • 0x50032818SR3// TZIC status register 3

    • [0]MDF1F (def=0x0) // illegal access flag for MDF1
    • [1]CORDICF (def=0x0) // illegal access flag for CORDIC
    • [2]FMACF (def=0x0) // illegal access flag for FMAC
    • [3]CRCF (def=0x0) // illegal access flag for CRC
    • [4]TSCF (def=0x0) // illegal access flag for TSC
    • [5]DMA2DF (def=0x0) // illegal access flag for register of DMA2D
    • [6]ICACHEF (def=0x0) // illegal access flag for ICACHE registers
    • [7]DCACHEF (def=0x0) // illegal access flag for DCACHE registers
    • [8]ADC1F (def=0x0) // illegal access flag for ADC1
    • [9]DCMIF (def=0x0) // illegal access flag for DCMI
    • [10]OTGFSF (def=0x0) // illegal access flag for OTG_FS
    • [11]AESF (def=0x0) // illegal access flag for AES
    • [12]HASHF (def=0x0) // illegal access flag for HASH
    • [13]RNGF (def=0x0) // illegal access flag for RNG
    • [14]PKAF (def=0x0) // illegal access flag for PKA
    • [15]SAESF (def=0x0) // illegal access flag for SAES
    • [16]OCTOSPIMF (def=0x0) // illegal access flag for OCTOSPIM
    • [17]SDMMC1F (def=0x0) // illegal access flag for SDMMC2
    • [18]SDMMC2F (def=0x0) // illegal access flag for SDMMC1
    • [19]FSMCF (def=0x0) // illegal access flag for FSMC registers
    • [20]OCTOSPI1F (def=0x0) // illegal access flag for OCTOSPI1 registers
    • [21]OCTOSPI2F (def=0x0) // illegal access flag for OCTOSPI2 registers
    • [22]RAMCFGF (def=0x0) // illegal access flag for RAMCFG
  • 0x5003281CSR4// TZIC status register 4

    • [0]GPDMA1F (def=0x0) // illegal access flag for GPDMA1
    • [1]FLASH_REGF (def=0x0) // illegal access flag for FLASH registers
    • [2]FLASHF (def=0x0) // illegal access flag for FLASH memory
    • [3]OTFDEC1F (def=0x0) // illegal access flag for OTFDEC1
    • [4]OTFDEC2F (def=0x0) // illegal access flag for OTFDEC2
    • [14]TZSC1F (def=0x0) // illegal access flag for GTZC1 TZSC registers
    • [15]TZIC1F (def=0x0) // illegal access flag for GTZC1 TZIC registers
    • [16]OCTOSPI1_MEMF (def=0x0) // illegal access flag for MPCWM1 (OCTOSPI1) memory bank
    • [17]FSMC_MEMF (def=0x0) // illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR)
    • [18]BKPSRAMF (def=0x0) // illegal access flag for MPCWM3 (BKPSRAM) memory bank
    • [19]OCTOSPI2_MEMF (def=0x0) // illegal access flag for OCTOSPI2 memory bank
    • [24]SRAM1F (def=0x0) // illegal access flag for SRAM1
    • [25]MPCBB1_REGF (def=0x0) // illegal access flag for MPCBB1 registers
    • [26]SRAM2F (def=0x0) // illegal access flag for SRAM2
    • [27]MPCBB2_REGF (def=0x0) // illegal access flag for MPCBB2 registers
    • [28]SRAM3F (def=0x0) // illegal access flag for SRAM3
    • [29]MPCBB3_REGF (def=0x0) // illegal access flag for MPCBB3 registers
  • 0x50032820FCR1// TZIC flag clear register 1

    • [0]CTIM2F (def=0x0) // clear the illegal access flag for TIM2
    • [1]CTIM3F (def=0x0) // clear the illegal access flag for TIM3
    • [2]CTIM4F (def=0x0) // clear the illegal access flag for TIM4
    • [3]CTIM5F (def=0x0) // clear the illegal access flag for TIM5
    • [4]CTIM6F (def=0x0) // clear the illegal access flag for TIM6
    • [5]CTIM7F (def=0x0) // clear the illegal access flag for TIM7
    • [6]CWWDGF (def=0x0) // clear the illegal access flag for WWDG
    • [7]CIWDGF (def=0x0) // clear the illegal access flag for IWDG
    • [8]CSPI2F (def=0x0) // clear the illegal access flag for SPI2
    • [9]CUSART2F (def=0x0) // clear the illegal access flag for USART2
    • [10]CUSART3F (def=0x0) // clear the illegal access flag for USART3
    • [11]CUART4F (def=0x0) // clear the illegal access flag for UART4
    • [12]CUART5F (def=0x0) // clear the illegal access flag for UART5
    • [13]CI2C1F (def=0x0) // clear the illegal access flag for I2C1
    • [14]CI2C2F (def=0x0) // clear the illegal access flag for I2C2
    • [15]CCRSF (def=0x0) // clear the illegal access flag for CRS
    • [16]CI2C4F (def=0x0) // clear the illegal access flag for I2C4
    • [17]CLPTIM2F (def=0x0) // clear the illegal access flag for LPTIM2
    • [18]CFDCAN1F (def=0x0) // clear the illegal access flag for FDCAN1
    • [19]CUCPD1F (def=0x0) // clear the illegal access flag for UCPD1
  • 0x50032824FCR2// TZIC flag clear register 2

    • [0]CTIM1F (def=0x0) // clear the illegal access flag for TIM1
    • [1]CSPI1F (def=0x0) // clear the illegal access flag for SPI1
    • [2]CTIM8F (def=0x0) // clear the illegal access flag for TIM8
    • [3]CUSART1F (def=0x0) // clear the illegal access flag for USART1
    • [4]CTIM15F (def=0x0) // clear the illegal access flag for TIM5
    • [5]CTIM16F (def=0x0) // clear the illegal access flag for TIM6
    • [6]CTIM17F (def=0x0) // clear the illegal access flag for TIM7
    • [7]CSAI1F (def=0x0) // clear the illegal access flag for SAI1
    • [8]CSAI2F (def=0x0) // clear the illegal access flag for SAI2
  • 0x50032828FCR3// TZIC flag clear register 3

    • [0]CMDF1F (def=0x0) // clear the illegal access flag for MDF1
    • [1]CCORDICF (def=0x0) // clear the illegal access flag for CORDIC
    • [2]CFMACF (def=0x0) // clear the illegal access flag for FMAC
    • [3]CCRCF (def=0x0) // clear the illegal access flag for CRC
    • [4]CTSCF (def=0x0) // clear the illegal access flag for TSC
    • [5]CDMA2DF (def=0x0) // clear the illegal access flag for register of DMA2D
    • [6]CICACHEF (def=0x0) // clear the illegal access flag for ICACHE registers
    • [7]CDCACHEF (def=0x0) // clear the illegal access flag for DCACHE registers
    • [8]CADC1F (def=0x0) // clear the illegal access flag for ADC1
    • [9]CDCMIF (def=0x0) // clear the illegal access flag for DCMI
    • [10]COTGFSF (def=0x0) // clear the illegal access flag for OTG_FS
    • [11]CAESF (def=0x0) // clear the illegal access flag for AES
    • [12]CHASHF (def=0x0) // clear the illegal access flag for HASH
    • [13]CRNGF (def=0x0) // clear the illegal access flag for RNG
    • [14]CPKAF (def=0x0) // clear the illegal access flag for PKA
    • [15]CSAESF (def=0x0) // clear the illegal access flag for SAES
    • [16]COCTOSPIMF (def=0x0) // clear the illegal access flag for OCTOSPIM
    • [17]CSDMMC1F (def=0x0) // clear the illegal access flag for SDMMC2
    • [18]CSDMMC2F (def=0x0) // clear the illegal access flag for SDMMC1
    • [19]CFSMCF (def=0x0) // clear the illegal access flag for FSMC registers
    • [20]COCTOSPI1F (def=0x0) // clear the illegal access flag for OCTOSPI1 registers
    • [21]COCTOSPI2F (def=0x0) // clear the illegal access flag for OCTOSPI2 registers
    • [22]CRAMCFGF (def=0x0) // clear the illegal access flag for RAMCFG
  • 0x5003282CFCR4// TZIC flag clear register 3

    • [0]CGPDMA1F (def=0x0) // clear the illegal access flag for GPDMA1
    • [1]CFLASH_REGF (def=0x0) // clear the illegal access flag for FLASH registers
    • [2]CFLASHF (def=0x0) // clear the illegal access flag for FLASH memory
    • [3]COTFDEC1F (def=0x0) // clear the illegal access flag for OTFDEC1
    • [4]COTFDEC2F (def=0x0) // clear the illegal access flag for OTFDEC2
    • [14]CTZSC1F (def=0x0) // clear the illegal access flag for GTZC1 TZSC registers
    • [15]CTZIC1F (def=0x0) // clear the illegal access flag for GTZC1 TZIC registers
    • [16]COCTOSPI1_MEMF (def=0x0) // clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank
    • [17]CFSMC_MEMF (def=0x0) // clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3
    • [18]CBKPSRAMF (def=0x0) // clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank
    • [19]COCTOSPI2_MEMF (def=0x0) // clear the illegal access flag for OCTOSPI2 memory bank
    • [24]CSRAM1F (def=0x0) // clear the illegal access flag for SRAM1
    • [25]CMPCBB1_REGF (def=0x0) // clear the illegal access flag for MPCBB1 registers
    • [26]CSRAM2F (def=0x0) // clear the illegal access flag for SRAM2
    • [27]CMPCBB2_REGF (def=0x0) // clear the illegal access flag for MPCBB2 registers
    • [28]CSRAM3F (def=0x0) // clear the illegal access flag for SRAM3
    • [29]CMPCBB3_REGF (def=0x0) // clear the illegal access flag for MPCBB3 registers
• 0x40032400GTZC1_TZSC// GTZC1_TZSC

  • 0x40032400TZSC_CR// TZSC control register

    • [0]LCK (def=0x0) // lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
  • 0x40032410TZSC_SECCFGR1// TZSC secure configuration register 1

    • [0]TIM2SEC (def=0x0) // secure access mode for TIM2
    • [1]TIM3SEC (def=0x0) // secure access mode for TIM3
    • [2]TIM4SEC (def=0x0) // secure access mode for TIM4
    • [3]TIM5SEC (def=0x0) // secure access mode for TIM5
    • [4]TIM6SEC (def=0x0) // secure access mode for TIM6
    • [5]TIM7SEC (def=0x0) // secure access mode for TIM7
    • [6]WWDGSEC (def=0x0) // secure access mode for WWDG
    • [7]IWDGSEC (def=0x0) // secure access mode for IWDG
    • [8]SPI2SEC (def=0x0) // secure access mode for SPI2
    • [9]USART2SEC (def=0x0) // secure access mode for USART2
    • [10]USART3SEC (def=0x0) // secure access mode for USART3
    • [11]UART4SEC (def=0x0) // secure access mode for UART4
    • [12]UART5SEC (def=0x0) // secure access mode for UART5
    • [13]I2C1SEC (def=0x0) // secure access mode for I2C1
    • [14]I2C2SEC (def=0x0) // secure access mode for I2C2
    • [15]CRSSEC (def=0x0) // secure access mode for CRS
    • [16]I2C4SEC (def=0x0) // secure access mode for I2C4
    • [17]LPTIM2SEC (def=0x0) // secure access mode for LPTIM2
    • [18]FDCAN1SEC (def=0x0) // secure access mode for FDCAN1
    • [19]UCPD1SEC (def=0x0) // secure access mode for UCPD1
  • 0x40032414TZSC_SECCFGR2// TZSC secure configuration register 2

    • [0]TIM1SEC (def=0x0) // secure access mode for TIM1
    • [1]SPI1SEC (def=0x0) // secure access mode for SPI1
    • [2]TIM8SEC (def=0x0) // secure access mode for TIM8
    • [3]USART1SEC (def=0x0) // secure access mode for USART1
    • [4]TIM15SEC (def=0x0) // secure access mode for TIM5
    • [5]TIM16SEC (def=0x0) // secure access mode for TIM6
    • [6]TIM17SEC (def=0x0) // secure access mode for TIM7
    • [7]SAI1SEC (def=0x0) // secure access mode for SAI1
    • [8]SAI2SEC (def=0x0) // secure access mode for SAI2
  • 0x40032418TZSC_SECCFGR3// TZSC secure configuration register 3

    • [0]MDF1SEC (def=0x0) // secure access mode for MDF1
    • [1]CORDICSEC (def=0x0) // secure access mode for CORDIC
    • [2]FMACSEC (def=0x0) // secure access mode for FMAC
    • [3]CRCSEC (def=0x0) // secure access mode for CRC
    • [4]TSCSEC (def=0x0) // secure access mode for TSC
    • [5]DMA2DSEC (def=0x0) // secure access mode for register of DMA2D
    • [6]ICACHE_REGSEC (def=0x0) // secure access mode for ICACHE registers
    • [7]DCACHE_REGSEC (def=0x0) // secure access mode for DCACHE registers
    • [8]ADC1SEC (def=0x0) // secure access mode for ADC1
    • [9]DCMISEC (def=0x0) // secure access mode for DCMI
    • [10]OTGFSSEC (def=0x0) // secure access mode for OTG_FS
    • [11]AESSEC (def=0x0) // secure access mode for AES
    • [12]HASHSEC (def=0x0) // secure access mode for HASH
    • [13]RNGSEC (def=0x0) // secure access mode for RNG
    • [14]PKASEC (def=0x0) // secure access mode for PKA
    • [15]SAESSEC (def=0x0) // secure access mode for SAES
    • [16]OCTOSPIMSEC (def=0x0) // secure access mode for OCTOSPIM
    • [17]SDMMC1SEC (def=0x0) // secure access mode for SDMMC2
    • [18]SDMMC2SEC (def=0x0) // secure access mode for SDMMC1
    • [19]FSMC_REGSEC (def=0x0) // secure access mode for FSMC registers
    • [20]OCTOSPI1_REGSEC (def=0x0) // secure access mode for OCTOSPI1 registers
    • [21]OCTOSPI2_REGSEC (def=0x0) // secure access mode for OCTOSPI2 registers
    • [22]RAMCFGSEC (def=0x0) // secure access mode for RAMCFG
  • 0x40032420TZSC_PRIVCFGR1// TZSC privilege configuration register 1

    • [0]TIM2PRIV (def=0x0) // privileged access mode for TIM2
    • [1]TIM3PRIV (def=0x0) // privileged access mode for TIM3
    • [2]TIM4PRIV (def=0x0) // privileged access mode for TIM4
    • [3]TIM5PRIV (def=0x0) // privileged access mode for TIM5
    • [4]TIM6PRIV (def=0x0) // privileged access mode for TIM6
    • [5]TIM7PRIV (def=0x0) // privileged access mode for TIM7
    • [6]WWDGPRIV (def=0x0) // privileged access mode for WWDG
    • [7]IWDGPRIV (def=0x0) // privileged access mode for IWDG
    • [8]SPI2PRIV (def=0x0) // privileged access mode for SPI2
    • [9]USART2PRIV (def=0x0) // privileged access mode for USART2
    • [10]USART3PRIV (def=0x0) // privileged access mode for USART3
    • [11]UART4PRIV (def=0x0) // privileged access mode for UART4
    • [12]UART5PRIV (def=0x0) // privileged access mode for UART5
    • [13]I2C1PRIV (def=0x0) // privileged access mode for I2C1
    • [14]I2C2PRIV (def=0x0) // privileged access mode for I2C2
    • [15]CRSPRIV (def=0x0) // privileged access mode for CRS
    • [16]I2C4PRIV (def=0x0) // privileged access mode for I2C4
    • [17]LPTIM2PRIV (def=0x0) // privileged access mode for LPTIM2
    • [18]FDCAN1PRIV (def=0x0) // privileged access mode for FDCAN1
    • [19]UCPD1PRIV (def=0x0) // privileged access mode for UCPD1
  • 0x40032424TZSC_PRIVCFGR2// TZSC privilege configuration register 2

    • [0]TIM1PRIV (def=0x0) // privileged access mode for TIM1
    • [1]SPI1PRIV (def=0x0) // privileged access mode for SPI1PRIV
    • [2]TIM8PRIV (def=0x0) // privileged access mode for TIM8
    • [3]USART1PRIV (def=0x0) // privileged access mode for USART1
    • [4]TIM15PRIV (def=0x0) // privileged access mode for TIM15
    • [5]TIM16PRIV (def=0x0) // privileged access mode for TIM16
    • [6]TIM17PRIV (def=0x0) // privileged access mode for TIM17
    • [7]SAI1PRIV (def=0x0) // privileged access mode for SAI1
    • [8]SAI2PRIV (def=0x0) // privileged access mode for SAI2
  • 0x40032428TZSC_PRIVCFGR3// TZSC privilege configuration register 3

    • [0]MDF1PRIV (def=0x0) // privileged access mode for MDF1
    • [1]CORDICPRIV (def=0x0) // privileged access mode for CORDIC
    • [2]FMACPRIV (def=0x0) // privileged access mode for FMAC
    • [3]CRCPRIV (def=0x0) // privileged access mode for CRC
    • [4]TSCPRIV (def=0x0) // privileged access mode for TSC
    • [5]DMA2DPRIV (def=0x0) // privileged access mode for register of DMA2D
    • [6]ICACHE_REGPRIV (def=0x0) // privileged access mode for ICACHE registers
    • [7]DCACHE_REGPRIV (def=0x0) // privileged access mode for DCACHE registers
    • [8]ADC1PRIV (def=0x0) // privileged access mode for ADC1
    • [9]DCMIPRIV (def=0x0) // privileged access mode for DCMI
    • [10]OTGFSPRIV (def=0x0) // privileged access mode for OTG_FS
    • [11]AESPRIV (def=0x0) // privileged access mode for AES
    • [12]HASHPRIV (def=0x0) // privileged access mode for HASH
    • [13]RNGPRIV (def=0x0) // privileged access mode for RNG
    • [14]PKAPRIV (def=0x0) // privileged access mode for PKA
    • [15]SAESPRIV (def=0x0) // privileged access mode for SAES
    • [16]OCTOSPIMPRIV (def=0x0) // privileged access mode for OCTOSPIM
    • [17]SDMMC1PRIV (def=0x0) // privileged access mode for SDMMC2
    • [18]SDMMC2PRIV (def=0x0) // privileged access mode for SDMMC1
    • [19]FSMC_REGPRIV (def=0x0) // privileged access mode for FSMC registers
    • [20]OCTOSPI1_REGPRIV (def=0x0) // privileged access mode for OCTOSPI1
    • [21]OCTOSPI2_REGPRIV (def=0x0) // privileged access mode for OCTOSPI2
    • [22]RAMCFGPRIV (def=0x0) // privileged access mode for RAMCFG
  • 0x40032440TZSC_MPCWM1ACFGR// TZSC memory 1 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x40032444TZSC_MPCWM1AR// TZSC memory 1 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032448TZSC_MPCWM1BCFGR// TZSC memory 1 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x4003244CTZSC_MPCWM1BR// TZSC memory 1 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032450TZSC_MPCWM2ACFGR// TZSC memory 2 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x40032454TZSC_MPCWM2AR// TZSC memory 2 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032458TZSC_MPCWM2BCFGR// TZSC memory 2 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x4003245CTZSC_MPCWM2BR// TZSC memory 2 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032460TZSC_MPCWM3ACFGR// TZSC memory 3 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x40032464TZSC_MPCWM3AR// TZSC memory 3 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032470TZSC_MPCWM4ACFGR// TZSC memory 4 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x40032474TZSC_MPCWM4AR// TZSC memory 4 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032480TZSC_MPCWM5ACFGR// TZSC memory 5 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x40032484TZSC_MPCWM5AR// TZSC memory 5 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x40032488TZSC_MPCWM5BCFGR// TZSC memory 5 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x4003248CTZSC_MPCWM5BR// TZSC memory 5 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
• 0x50032400SEC_GTZC1_TZSC//

  • 0x50032400TZSC_CR// TZSC control register

    • [0]LCK (def=0x0) // lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
  • 0x50032410TZSC_SECCFGR1// TZSC secure configuration register 1

    • [0]TIM2SEC (def=0x0) // secure access mode for TIM2
    • [1]TIM3SEC (def=0x0) // secure access mode for TIM3
    • [2]TIM4SEC (def=0x0) // secure access mode for TIM4
    • [3]TIM5SEC (def=0x0) // secure access mode for TIM5
    • [4]TIM6SEC (def=0x0) // secure access mode for TIM6
    • [5]TIM7SEC (def=0x0) // secure access mode for TIM7
    • [6]WWDGSEC (def=0x0) // secure access mode for WWDG
    • [7]IWDGSEC (def=0x0) // secure access mode for IWDG
    • [8]SPI2SEC (def=0x0) // secure access mode for SPI2
    • [9]USART2SEC (def=0x0) // secure access mode for USART2
    • [10]USART3SEC (def=0x0) // secure access mode for USART3
    • [11]UART4SEC (def=0x0) // secure access mode for UART4
    • [12]UART5SEC (def=0x0) // secure access mode for UART5
    • [13]I2C1SEC (def=0x0) // secure access mode for I2C1
    • [14]I2C2SEC (def=0x0) // secure access mode for I2C2
    • [15]CRSSEC (def=0x0) // secure access mode for CRS
    • [16]I2C4SEC (def=0x0) // secure access mode for I2C4
    • [17]LPTIM2SEC (def=0x0) // secure access mode for LPTIM2
    • [18]FDCAN1SEC (def=0x0) // secure access mode for FDCAN1
    • [19]UCPD1SEC (def=0x0) // secure access mode for UCPD1
  • 0x50032414TZSC_SECCFGR2// TZSC secure configuration register 2

    • [0]TIM1SEC (def=0x0) // secure access mode for TIM1
    • [1]SPI1SEC (def=0x0) // secure access mode for SPI1
    • [2]TIM8SEC (def=0x0) // secure access mode for TIM8
    • [3]USART1SEC (def=0x0) // secure access mode for USART1
    • [4]TIM15SEC (def=0x0) // secure access mode for TIM5
    • [5]TIM16SEC (def=0x0) // secure access mode for TIM6
    • [6]TIM17SEC (def=0x0) // secure access mode for TIM7
    • [7]SAI1SEC (def=0x0) // secure access mode for SAI1
    • [8]SAI2SEC (def=0x0) // secure access mode for SAI2
  • 0x50032418TZSC_SECCFGR3// TZSC secure configuration register 3

    • [0]MDF1SEC (def=0x0) // secure access mode for MDF1
    • [1]CORDICSEC (def=0x0) // secure access mode for CORDIC
    • [2]FMACSEC (def=0x0) // secure access mode for FMAC
    • [3]CRCSEC (def=0x0) // secure access mode for CRC
    • [4]TSCSEC (def=0x0) // secure access mode for TSC
    • [5]DMA2DSEC (def=0x0) // secure access mode for register of DMA2D
    • [6]ICACHE_REGSEC (def=0x0) // secure access mode for ICACHE registers
    • [7]DCACHE_REGSEC (def=0x0) // secure access mode for DCACHE registers
    • [8]ADC1SEC (def=0x0) // secure access mode for ADC1
    • [9]DCMISEC (def=0x0) // secure access mode for DCMI
    • [10]OTGFSSEC (def=0x0) // secure access mode for OTG_FS
    • [11]AESSEC (def=0x0) // secure access mode for AES
    • [12]HASHSEC (def=0x0) // secure access mode for HASH
    • [13]RNGSEC (def=0x0) // secure access mode for RNG
    • [14]PKASEC (def=0x0) // secure access mode for PKA
    • [15]SAESSEC (def=0x0) // secure access mode for SAES
    • [16]OCTOSPIMSEC (def=0x0) // secure access mode for OCTOSPIM
    • [17]SDMMC1SEC (def=0x0) // secure access mode for SDMMC2
    • [18]SDMMC2SEC (def=0x0) // secure access mode for SDMMC1
    • [19]FSMC_REGSEC (def=0x0) // secure access mode for FSMC registers
    • [20]OCTOSPI1_REGSEC (def=0x0) // secure access mode for OCTOSPI1 registers
    • [21]OCTOSPI2_REGSEC (def=0x0) // secure access mode for OCTOSPI2 registers
    • [22]RAMCFGSEC (def=0x0) // secure access mode for RAMCFG
  • 0x50032420TZSC_PRIVCFGR1// TZSC privilege configuration register 1

    • [0]TIM2PRIV (def=0x0) // privileged access mode for TIM2
    • [1]TIM3PRIV (def=0x0) // privileged access mode for TIM3
    • [2]TIM4PRIV (def=0x0) // privileged access mode for TIM4
    • [3]TIM5PRIV (def=0x0) // privileged access mode for TIM5
    • [4]TIM6PRIV (def=0x0) // privileged access mode for TIM6
    • [5]TIM7PRIV (def=0x0) // privileged access mode for TIM7
    • [6]WWDGPRIV (def=0x0) // privileged access mode for WWDG
    • [7]IWDGPRIV (def=0x0) // privileged access mode for IWDG
    • [8]SPI2PRIV (def=0x0) // privileged access mode for SPI2
    • [9]USART2PRIV (def=0x0) // privileged access mode for USART2
    • [10]USART3PRIV (def=0x0) // privileged access mode for USART3
    • [11]UART4PRIV (def=0x0) // privileged access mode for UART4
    • [12]UART5PRIV (def=0x0) // privileged access mode for UART5
    • [13]I2C1PRIV (def=0x0) // privileged access mode for I2C1
    • [14]I2C2PRIV (def=0x0) // privileged access mode for I2C2
    • [15]CRSPRIV (def=0x0) // privileged access mode for CRS
    • [16]I2C4PRIV (def=0x0) // privileged access mode for I2C4
    • [17]LPTIM2PRIV (def=0x0) // privileged access mode for LPTIM2
    • [18]FDCAN1PRIV (def=0x0) // privileged access mode for FDCAN1
    • [19]UCPD1PRIV (def=0x0) // privileged access mode for UCPD1
  • 0x50032424TZSC_PRIVCFGR2// TZSC privilege configuration register 2

    • [0]TIM1PRIV (def=0x0) // privileged access mode for TIM1
    • [1]SPI1PRIV (def=0x0) // privileged access mode for SPI1PRIV
    • [2]TIM8PRIV (def=0x0) // privileged access mode for TIM8
    • [3]USART1PRIV (def=0x0) // privileged access mode for USART1
    • [4]TIM15PRIV (def=0x0) // privileged access mode for TIM15
    • [5]TIM16PRIV (def=0x0) // privileged access mode for TIM16
    • [6]TIM17PRIV (def=0x0) // privileged access mode for TIM17
    • [7]SAI1PRIV (def=0x0) // privileged access mode for SAI1
    • [8]SAI2PRIV (def=0x0) // privileged access mode for SAI2
  • 0x50032428TZSC_PRIVCFGR3// TZSC privilege configuration register 3

    • [0]MDF1PRIV (def=0x0) // privileged access mode for MDF1
    • [1]CORDICPRIV (def=0x0) // privileged access mode for CORDIC
    • [2]FMACPRIV (def=0x0) // privileged access mode for FMAC
    • [3]CRCPRIV (def=0x0) // privileged access mode for CRC
    • [4]TSCPRIV (def=0x0) // privileged access mode for TSC
    • [5]DMA2DPRIV (def=0x0) // privileged access mode for register of DMA2D
    • [6]ICACHE_REGPRIV (def=0x0) // privileged access mode for ICACHE registers
    • [7]DCACHE_REGPRIV (def=0x0) // privileged access mode for DCACHE registers
    • [8]ADC1PRIV (def=0x0) // privileged access mode for ADC1
    • [9]DCMIPRIV (def=0x0) // privileged access mode for DCMI
    • [10]OTGFSPRIV (def=0x0) // privileged access mode for OTG_FS
    • [11]AESPRIV (def=0x0) // privileged access mode for AES
    • [12]HASHPRIV (def=0x0) // privileged access mode for HASH
    • [13]RNGPRIV (def=0x0) // privileged access mode for RNG
    • [14]PKAPRIV (def=0x0) // privileged access mode for PKA
    • [15]SAESPRIV (def=0x0) // privileged access mode for SAES
    • [16]OCTOSPIMPRIV (def=0x0) // privileged access mode for OCTOSPIM
    • [17]SDMMC1PRIV (def=0x0) // privileged access mode for SDMMC2
    • [18]SDMMC2PRIV (def=0x0) // privileged access mode for SDMMC1
    • [19]FSMC_REGPRIV (def=0x0) // privileged access mode for FSMC registers
    • [20]OCTOSPI1_REGPRIV (def=0x0) // privileged access mode for OCTOSPI1
    • [21]OCTOSPI2_REGPRIV (def=0x0) // privileged access mode for OCTOSPI2
    • [22]RAMCFGPRIV (def=0x0) // privileged access mode for RAMCFG
  • 0x50032440TZSC_MPCWM1ACFGR// TZSC memory 1 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x50032444TZSC_MPCWM1AR// TZSC memory 1 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032448TZSC_MPCWM1BCFGR// TZSC memory 1 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x5003244CTZSC_MPCWM1BR// TZSC memory 1 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032450TZSC_MPCWM2ACFGR// TZSC memory 2 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x50032454TZSC_MPCWM2AR// TZSC memory 2 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032458TZSC_MPCWM2BCFGR// TZSC memory 2 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x5003245CTZSC_MPCWM2BR// TZSC memory 2 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032460TZSC_MPCWM3ACFGR// TZSC memory 3 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x50032464TZSC_MPCWM3AR// TZSC memory 3 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032470TZSC_MPCWM4ACFGR// TZSC memory 4 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x50032474TZSC_MPCWM4AR// TZSC memory 4 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032480TZSC_MPCWM5ACFGR// TZSC memory 5 sub-region A watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x50032484TZSC_MPCWM5AR// TZSC memory 5 sub-region A watermark register

    • [0:10]SUBA_START (def=0x0) // Start of sub-region A
    • [16:27]SUBA_LENGTH (def=0x0) // Length of sub-region A
  • 0x50032488TZSC_MPCWM5BCFGR// TZSC memory 5 sub-region B watermark configuration register

    • [0]SREN (def=0x0) // Sub-region enable
    • [1]SRLOCK (def=0x0) // Sub-region lock
    • [8]SEC (def=0x0) // Secure sub-region
    • [9]PRIV (def=0x0) // Privileged sub-region
  • 0x5003248CTZSC_MPCWM5BR// TZSC memory 5 sub-region B watermark register

    • [0:10]SUBB_START (def=0x0) // Start of sub-region A
    • [16:27]SUBB_LENGTH (def=0x0) // Length of sub-region A
• 0x46023800GTZC2_MPCBB4// GTZC2_MPCBB4

  • 0x46023800MPCBB4_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x46023810MPCBB4_CFGLOCK// GTZC2 SRAM4 MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // Security/privilege configuration lock for super-block 0
  • 0x46023900MPCBB4_SECCFGR0// MPCBB security configuration for super-block 0 register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x46023A00MPCBB4_PRIVCFGR0// MPCBB privileged configuration for super-block 0 register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x56023800SEC_GTZC2_MPCBB4//

  • 0x56023800MPCBB4_CR// MPCBB control register

    • [0]GLOCK (def=0x0) // lock the control register of the MPCBB until next reset
    • [30]INVSECSTATE (def=0x0) // SRAMx clocks security state
    • [31]SRWILADIS (def=0x0) // secure read/write illegal access disable
  • 0x56023810MPCBB4_CFGLOCK// GTZC2 SRAM4 MPCBB configuration lock register

    • [0]SPLCK0 (def=0x0) // Security/privilege configuration lock for super-block 0
  • 0x56023900MPCBB4_SECCFGR0// MPCBB security configuration for super-block 0 register

    • [0]SEC0 (def=0x1) // SEC0
    • [1]SEC1 (def=0x1) // SEC1
    • [2]SEC2 (def=0x1) // SEC2
    • [3]SEC3 (def=0x1) // SEC3
    • [4]SEC4 (def=0x1) // SEC4
    • [5]SEC5 (def=0x1) // SEC5
    • [6]SEC6 (def=0x1) // SEC6
    • [7]SEC7 (def=0x1) // SEC7
    • [8]SEC8 (def=0x1) // SEC8
    • [9]SEC9 (def=0x1) // SEC9
    • [10]SEC10 (def=0x1) // SEC10
    • [11]SEC11 (def=0x1) // SEC11
    • [12]SEC12 (def=0x1) // SEC12
    • [13]SEC13 (def=0x1) // SEC13
    • [14]SEC14 (def=0x1) // SEC14
    • [15]SEC15 (def=0x1) // SEC15
    • [16]SEC16 (def=0x1) // SEC16
    • [17]SEC17 (def=0x1) // SEC17
    • [18]SEC18 (def=0x1) // SEC18
    • [19]SEC19 (def=0x1) // SEC19
    • [20]SEC20 (def=0x1) // SEC20
    • [21]SEC21 (def=0x1) // SEC21
    • [22]SEC22 (def=0x1) // SEC22
    • [23]SEC23 (def=0x1) // SEC23
    • [24]SEC24 (def=0x1) // SEC24
    • [25]SEC25 (def=0x1) // SEC25
    • [26]SEC26 (def=0x1) // SEC26
    • [27]SEC27 (def=0x1) // SEC27
    • [28]SEC28 (def=0x1) // SEC28
    • [29]SEC29 (def=0x1) // SEC29
    • [30]SEC30 (def=0x1) // SEC30
    • [31]SEC31 (def=0x1) // SEC31
  • 0x56023A00MPCBB4_PRIVCFGR0// MPCBB privileged configuration for super-block 0 register

    • [0]PRIV0 (def=0x1) // PRIV0
    • [1]PRIV1 (def=0x1) // PRIV1
    • [2]PRIV2 (def=0x1) // PRIV2
    • [3]PRIV3 (def=0x1) // PRIV3
    • [4]PRIV4 (def=0x1) // PRIV4
    • [5]PRIV5 (def=0x1) // PRIV5
    • [6]PRIV6 (def=0x1) // PRIV6
    • [7]PRIV7 (def=0x1) // PRIV7
    • [8]PRIV8 (def=0x1) // PRIV8
    • [9]PRIV9 (def=0x1) // PRIV9
    • [10]PRIV10 (def=0x1) // PRIV10
    • [11]PRIV11 (def=0x1) // PRIV11
    • [12]PRIV12 (def=0x1) // PRIV12
    • [13]PRIV13 (def=0x1) // PRIV13
    • [14]PRIV14 (def=0x1) // PRIV14
    • [15]PRIV15 (def=0x1) // PRIV15
    • [16]PRIV16 (def=0x1) // PRIV16
    • [17]PRIV17 (def=0x1) // PRIV17
    • [18]PRIV18 (def=0x1) // PRIV18
    • [19]PRIV19 (def=0x1) // PRIV19
    • [20]PRIV20 (def=0x1) // PRIV20
    • [21]PRIV21 (def=0x1) // PRIV21
    • [22]PRIV22 (def=0x1) // PRIV22
    • [23]PRIV23 (def=0x1) // PRIV23
    • [24]PRIV24 (def=0x1) // PRIV24
    • [25]PRIV25 (def=0x1) // PRIV25
    • [26]PRIV26 (def=0x1) // PRIV26
    • [27]PRIV27 (def=0x1) // PRIV27
    • [28]PRIV28 (def=0x1) // PRIV28
    • [29]PRIV29 (def=0x1) // PRIV29
    • [30]PRIV30 (def=0x1) // PRIV30
    • [31]PRIV31 (def=0x1) // PRIV31
• 0x46023400GTZC2_TZIC// GTZC2_TZIC

  • 0x46023400IER1// TZIC interrupt enable register 1

    • [0]SPI3IE (def=0x0) // illegal access interrupt enable for SPI3
    • [1]LPUART1IE (def=0x0) // illegal access interrupt enable for LPUART1
    • [2]I2C3IE (def=0x0) // illegal access interrupt enable for I2C3
    • [3]LPTIM1IE (def=0x0) // illegal access interrupt enable for LPTIM1
    • [4]LPTIM3IE (def=0x0) // illegal access interrupt enable for LPTIM3
    • [5]LPTIM4IE (def=0x0) // illegal access interrupt enable for LPTIM4
    • [6]OPAMPIE (def=0x0) // illegal access interrupt enable for OPAMP
    • [7]COMPIE (def=0x0) // illegal access interrupt enable for COMP
    • [8]ADC4IE (def=0x0) // illegal access interrupt enable for ADC4
    • [9]VREFBUFIE (def=0x0) // illegal access interrupt enable for VREFBUF
    • [11]DAC1IE (def=0x0) // illegal access interrupt enable for DAC1
    • [12]ADF1IE (def=0x0) // illegal access interrupt enable for ADF1
  • 0x46023404IER2// TZIC interrupt enable register 2

    • [0]SYSCFGIE (def=0x0) // illegal access interrupt enable for SYSCFG
    • [1]RTCIE (def=0x0) // illegal access interrupt enable for RTC
    • [2]TAMPIE (def=0x0) // illegal access interrupt enable for TAMP
    • [3]PWRIE (def=0x0) // illegal access interrupt enable for PWR
    • [4]RCCIE (def=0x0) // illegal access interrupt enable for RCC
    • [5]LPDMA1IE (def=0x0) // illegal access interrupt enable for LPDMA
    • [6]EXTIIE (def=0x0) // illegal access interrupt enable for EXTI
    • [14]TZSC2IE (def=0x0) // illegal access interrupt enable for GTZC2 TZSC registers
    • [15]TZIC2IE (def=0x0) // illegal access interrupt enable for GTZC2 TZIC registers
    • [24]SRAM4IE (def=0x0) // illegal access interrupt enable for SRAM4
    • [25]MPCBB4_REGIE (def=0x0) // illegal access interrupt enable for MPCBB4 registers
  • 0x46023410SR1// TZIC status register 1

    • [0]SPI3F (def=0x0) // illegal access flag for SPI3
    • [1]LPUART1F (def=0x0) // illegal access flag for LPUART1
    • [2]I2C3F (def=0x0) // illegal access flag for I2C3
    • [3]LPTIM1F (def=0x0) // illegal access flag for LPTIM1
    • [4]LPTIM3F (def=0x0) // illegal access flag for LPTIM3
    • [5]LPTIM4F (def=0x0) // illegal access flag for LPTIM4
    • [6]OPAMPF (def=0x0) // illegal access flag for OPAMP
    • [7]COMPF (def=0x0) // illegal access flag for COMP
    • [8]ADC4F (def=0x0) // illegal access flag for ADC4
    • [9]VREFBUFF (def=0x0) // illegal access flag for VREFBUF
    • [11]DAC1F (def=0x0) // illegal access flag for DAC1
    • [12]ADF1F (def=0x0) // illegal access flag for ADF1
  • 0x46023414SR2// TZIC status register 2

    • [0]SYSCFGF (def=0x0) // illegal access flag for SYSCFG
    • [1]RTCF (def=0x0) // illegal access flag for RTC
    • [2]TAMPF (def=0x0) // illegal access flag for TAMP
    • [3]PWRF (def=0x0) // illegal access flag for PWRUSART1F
    • [4]RCCF (def=0x0) // illegal access flag for RCC
    • [5]LPDMA1F (def=0x0) // illegal access flag for LPDMA
    • [6]EXTIF (def=0x0) // illegal access flag for EXTI
    • [14]TZSC2F (def=0x0) // illegal access flag for GTZC2 TZSC registers
    • [15]TZIC2F (def=0x0) // illegal access flag for GTZC2 TZIC registers
    • [24]SRAM4F (def=0x0) // illegal access flag for SRAM4
    • [25]MPCBB4_REGF (def=0x0) // illegal access flag for MPCBB4 registers
  • 0x46023420FCR1// TZIC flag clear register 1

    • [0]CSPI3F (def=0x0) // clear the illegal access flag for SPI3
    • [1]CLPUART1F (def=0x0) // clear the illegal access flag for LPUART1
    • [2]CI2C3F (def=0x0) // clear the illegal access flag for I2C3
    • [3]CLPTIM1F (def=0x0) // clear the illegal access flag for LPTIM1
    • [4]CLPTIM3F (def=0x0) // clear the illegal access flag for LPTIM3
    • [5]CLPTIM4F (def=0x0) // clear the illegal access flag for LPTIM4
    • [6]COPAMPF (def=0x0) // clear the illegal access flag for OPAMP
    • [7]CCOMPF (def=0x0) // clear the illegal access flag for COMP
    • [8]CADC4F (def=0x0) // clear the illegal access flag for ADC4
    • [9]CVREFBUFF (def=0x0) // clear the illegal access flag for VREFBUF
    • [11]CDAC1F (def=0x0) // clear the illegal access flag for DAC1
    • [12]CADF1F (def=0x0) // clear the illegal access flag for ADF1
  • 0x46023424FCR2// TZIC flag clear register 2

    • [0]CSYSCFGF (def=0x0) // clear the illegal access flag for SYSCFG
    • [1]CRTCF (def=0x0) // clear the illegal access flag for RTC
    • [2]CTAMPF (def=0x0) // clear the illegal access flag for TAMP
    • [3]CPWRF (def=0x0) // clear the illegal access flag for PWR
    • [4]CRCCF (def=0x0) // clear the illegal access flag for RCC
    • [5]CLPDMA1F (def=0x0) // clear the illegal access flag for LPDMA
    • [6]CEXTIF (def=0x0) // clear the illegal access flag for EXTI
    • [14]CTZSC2F (def=0x0) // clear the illegal access flag for GTZC2 TZSC registers
    • [15]CTZIC2F (def=0x0) // clear the illegal access flag for GTZC2 TZIC registers
    • [24]CSRAM4F (def=0x0) // clear the illegal access flag for SRAM4
    • [25]CMPCBB4_REGF (def=0x0) // clear the illegal access flag for MPCBB4 registers
• 0x56023400SEC_GTZC2_TZIC//

  • 0x56023400IER1// TZIC interrupt enable register 1

    • [0]SPI3IE (def=0x0) // illegal access interrupt enable for SPI3
    • [1]LPUART1IE (def=0x0) // illegal access interrupt enable for LPUART1
    • [2]I2C3IE (def=0x0) // illegal access interrupt enable for I2C3
    • [3]LPTIM1IE (def=0x0) // illegal access interrupt enable for LPTIM1
    • [4]LPTIM3IE (def=0x0) // illegal access interrupt enable for LPTIM3
    • [5]LPTIM4IE (def=0x0) // illegal access interrupt enable for LPTIM4
    • [6]OPAMPIE (def=0x0) // illegal access interrupt enable for OPAMP
    • [7]COMPIE (def=0x0) // illegal access interrupt enable for COMP
    • [8]ADC4IE (def=0x0) // illegal access interrupt enable for ADC4
    • [9]VREFBUFIE (def=0x0) // illegal access interrupt enable for VREFBUF
    • [11]DAC1IE (def=0x0) // illegal access interrupt enable for DAC1
    • [12]ADF1IE (def=0x0) // illegal access interrupt enable for ADF1
  • 0x56023404IER2// TZIC interrupt enable register 2

    • [0]SYSCFGIE (def=0x0) // illegal access interrupt enable for SYSCFG
    • [1]RTCIE (def=0x0) // illegal access interrupt enable for RTC
    • [2]TAMPIE (def=0x0) // illegal access interrupt enable for TAMP
    • [3]PWRIE (def=0x0) // illegal access interrupt enable for PWR
    • [4]RCCIE (def=0x0) // illegal access interrupt enable for RCC
    • [5]LPDMA1IE (def=0x0) // illegal access interrupt enable for LPDMA
    • [6]EXTIIE (def=0x0) // illegal access interrupt enable for EXTI
    • [14]TZSC2IE (def=0x0) // illegal access interrupt enable for GTZC2 TZSC registers
    • [15]TZIC2IE (def=0x0) // illegal access interrupt enable for GTZC2 TZIC registers
    • [24]SRAM4IE (def=0x0) // illegal access interrupt enable for SRAM4
    • [25]MPCBB4_REGIE (def=0x0) // illegal access interrupt enable for MPCBB4 registers
  • 0x56023410SR1// TZIC status register 1

    • [0]SPI3F (def=0x0) // illegal access flag for SPI3
    • [1]LPUART1F (def=0x0) // illegal access flag for LPUART1
    • [2]I2C3F (def=0x0) // illegal access flag for I2C3
    • [3]LPTIM1F (def=0x0) // illegal access flag for LPTIM1
    • [4]LPTIM3F (def=0x0) // illegal access flag for LPTIM3
    • [5]LPTIM4F (def=0x0) // illegal access flag for LPTIM4
    • [6]OPAMPF (def=0x0) // illegal access flag for OPAMP
    • [7]COMPF (def=0x0) // illegal access flag for COMP
    • [8]ADC4F (def=0x0) // illegal access flag for ADC4
    • [9]VREFBUFF (def=0x0) // illegal access flag for VREFBUF
    • [11]DAC1F (def=0x0) // illegal access flag for DAC1
    • [12]ADF1F (def=0x0) // illegal access flag for ADF1
  • 0x56023414SR2// TZIC status register 2

    • [0]SYSCFGF (def=0x0) // illegal access flag for SYSCFG
    • [1]RTCF (def=0x0) // illegal access flag for RTC
    • [2]TAMPF (def=0x0) // illegal access flag for TAMP
    • [3]PWRF (def=0x0) // illegal access flag for PWRUSART1F
    • [4]RCCF (def=0x0) // illegal access flag for RCC
    • [5]LPDMA1F (def=0x0) // illegal access flag for LPDMA
    • [6]EXTIF (def=0x0) // illegal access flag for EXTI
    • [14]TZSC2F (def=0x0) // illegal access flag for GTZC2 TZSC registers
    • [15]TZIC2F (def=0x0) // illegal access flag for GTZC2 TZIC registers
    • [24]SRAM4F (def=0x0) // illegal access flag for SRAM4
    • [25]MPCBB4_REGF (def=0x0) // illegal access flag for MPCBB4 registers
  • 0x56023420FCR1// TZIC flag clear register 1

    • [0]CSPI3F (def=0x0) // clear the illegal access flag for SPI3
    • [1]CLPUART1F (def=0x0) // clear the illegal access flag for LPUART1
    • [2]CI2C3F (def=0x0) // clear the illegal access flag for I2C3
    • [3]CLPTIM1F (def=0x0) // clear the illegal access flag for LPTIM1
    • [4]CLPTIM3F (def=0x0) // clear the illegal access flag for LPTIM3
    • [5]CLPTIM4F (def=0x0) // clear the illegal access flag for LPTIM4
    • [6]COPAMPF (def=0x0) // clear the illegal access flag for OPAMP
    • [7]CCOMPF (def=0x0) // clear the illegal access flag for COMP
    • [8]CADC4F (def=0x0) // clear the illegal access flag for ADC4
    • [9]CVREFBUFF (def=0x0) // clear the illegal access flag for VREFBUF
    • [11]CDAC1F (def=0x0) // clear the illegal access flag for DAC1
    • [12]CADF1F (def=0x0) // clear the illegal access flag for ADF1
  • 0x56023424FCR2// TZIC flag clear register 2

    • [0]CSYSCFGF (def=0x0) // clear the illegal access flag for SYSCFG
    • [1]CRTCF (def=0x0) // clear the illegal access flag for RTC
    • [2]CTAMPF (def=0x0) // clear the illegal access flag for TAMP
    • [3]CPWRF (def=0x0) // clear the illegal access flag for PWR
    • [4]CRCCF (def=0x0) // clear the illegal access flag for RCC
    • [5]CLPDMA1F (def=0x0) // clear the illegal access flag for LPDMA
    • [6]CEXTIF (def=0x0) // clear the illegal access flag for EXTI
    • [14]CTZSC2F (def=0x0) // clear the illegal access flag for GTZC2 TZSC registers
    • [15]CTZIC2F (def=0x0) // clear the illegal access flag for GTZC2 TZIC registers
    • [24]CSRAM4F (def=0x0) // clear the illegal access flag for SRAM4
    • [25]CMPCBB4_REGF (def=0x0) // clear the illegal access flag for MPCBB4 registers
• 0x46023000GTZC2_TZSC// GTZC2_TZSC

  • 0x46023000TZSC_CR// TZSC control register

    • [0]LCK (def=0x0) // lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
  • 0x46023010TZSC_SECCFGR1// TZSC secure configuration register 1

    • [0]SPI3SEC (def=0x0) // secure access mode for SPI3
    • [1]LPUART1SEC (def=0x0) // secure access mode for LPUART1
    • [2]I2C3SEC (def=0x0) // secure access mode for I2C3
    • [3]LPTIM1SEC (def=0x0) // secure access mode for LPTIM1
    • [4]LPTIM3SEC (def=0x0) // secure access mode for LPTIM3
    • [5]LPTIM4SEC (def=0x0) // secure access mode for LPTIM4
    • [6]OPAMPSEC (def=0x0) // secure access mode for OPAMP
    • [7]COMPSEC (def=0x0) // secure access mode for COMP
    • [8]ADC4SEC (def=0x0) // secure access mode for ADC4
    • [9]VREFBUFSEC (def=0x0) // secure access mode for VREFBUF
    • [11]DAC1SEC (def=0x0) // secure access mode for DAC1
    • [12]ADF1SEC (def=0x0) // secure access mode for ADF1
  • 0x46023020TZSC_PRIVCFGR1// TZSC privilege configuration register 1

    • [0]SPI3PRIV (def=0x0) // privileged access mode for SPI3
    • [1]LPUART1PRIV (def=0x0) // privileged access mode for LPUART1
    • [2]I2C3PRIV (def=0x0) // privileged access mode for I2C3
    • [3]LPTIM1PRIV (def=0x0) // privileged access mode for LPTIM1
    • [4]LPTIM3PRIV (def=0x0) // privileged access mode for LPTIM3
    • [5]LPTIM4PRIV (def=0x0) // privileged access mode for LPTIM4
    • [6]OPAMPPRIV (def=0x0) // privileged access mode for OPAMP
    • [7]COMPPRIV (def=0x0) // privileged access mode for COMP
    • [8]ADC4PRIV (def=0x0) // privileged access mode for ADC4
    • [9]VREFBUFPRIV (def=0x0) // privileged access mode for VREFBUF
    • [11]DAC1PRIV (def=0x0) // privileged access mode for DAC1
    • [12]ADF1PRIV (def=0x0) // privileged access mode for ADF1
• 0x56023000SEC_GTZC2_TZSC//

  • 0x56023000TZSC_CR// TZSC control register

    • [0]LCK (def=0x0) // lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
  • 0x56023010TZSC_SECCFGR1// TZSC secure configuration register 1

    • [0]SPI3SEC (def=0x0) // secure access mode for SPI3
    • [1]LPUART1SEC (def=0x0) // secure access mode for LPUART1
    • [2]I2C3SEC (def=0x0) // secure access mode for I2C3
    • [3]LPTIM1SEC (def=0x0) // secure access mode for LPTIM1
    • [4]LPTIM3SEC (def=0x0) // secure access mode for LPTIM3
    • [5]LPTIM4SEC (def=0x0) // secure access mode for LPTIM4
    • [6]OPAMPSEC (def=0x0) // secure access mode for OPAMP
    • [7]COMPSEC (def=0x0) // secure access mode for COMP
    • [8]ADC4SEC (def=0x0) // secure access mode for ADC4
    • [9]VREFBUFSEC (def=0x0) // secure access mode for VREFBUF
    • [11]DAC1SEC (def=0x0) // secure access mode for DAC1
    • [12]ADF1SEC (def=0x0) // secure access mode for ADF1
  • 0x56023020TZSC_PRIVCFGR1// TZSC privilege configuration register 1

    • [0]SPI3PRIV (def=0x0) // privileged access mode for SPI3
    • [1]LPUART1PRIV (def=0x0) // privileged access mode for LPUART1
    • [2]I2C3PRIV (def=0x0) // privileged access mode for I2C3
    • [3]LPTIM1PRIV (def=0x0) // privileged access mode for LPTIM1
    • [4]LPTIM3PRIV (def=0x0) // privileged access mode for LPTIM3
    • [5]LPTIM4PRIV (def=0x0) // privileged access mode for LPTIM4
    • [6]OPAMPPRIV (def=0x0) // privileged access mode for OPAMP
    • [7]COMPPRIV (def=0x0) // privileged access mode for COMP
    • [8]ADC4PRIV (def=0x0) // privileged access mode for ADC4
    • [9]VREFBUFPRIV (def=0x0) // privileged access mode for VREFBUF
    • [11]DAC1PRIV (def=0x0) // privileged access mode for DAC1
    • [12]ADF1PRIV (def=0x0) // privileged access mode for ADF1
• 0x46020800PWR// Power control

  • 0x46020800PWR_CR1// PWR control register 1

    • [0:2]LPMS (def=0x0) // Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deeps
    • [5]RRSB1 (def=0x0) // SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 conten
    • [6]RRSB2 (def=0x0) // SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 conten
    • [7]ULPMEN (def=0x0) // BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in disco
    • [8]SRAM1PD (def=0x0) // SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1.
    • [9]SRAM2PD (def=0x0) // SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2.
    • [10]SRAM3PD (def=0x0) // SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3.
    • [11]SRAM4PD (def=0x0) // SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4.
  • 0x46020804PWR_CR2// PWR control register 2

    • [0]SRAM1PDS1 (def=0x0) // SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [1]SRAM1PDS2 (def=0x0) // SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [2]SRAM1PDS3 (def=0x0) // SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [4]SRAM2PDS1 (def=0x0) // SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in
    • [5]SRAM2PDS2 (def=0x0) // SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention i
    • [6]SRAM4PDS (def=0x0) // SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)
    • [8]ICRAMPDS (def=0x0) // ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [9]DC1RAMPDS (def=0x0) // DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [10]DMA2DRAMPDS (def=0x0) // DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [11]PRAMPDS (def=0x0) // FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [12]PKARAMPDS (def=0x0) // PKA SRAM power-down
    • [13]SRAM4FWU (def=0x0) // SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-of
    • [14]FLASHFWU (def=0x0) // Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off
    • [16]SRAM3PDS1 (def=0x0) // SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [17]SRAM3PDS2 (def=0x0) // SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [18]SRAM3PDS3 (def=0x0) // SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [19]SRAM3PDS4 (def=0x0) // SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [20]SRAM3PDS5 (def=0x0) // SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [21]SRAM3PDS6 (def=0x0) // SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [22]SRAM3PDS7 (def=0x0) // SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [23]SRAM3PDS8 (def=0x0) // SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [31]SRDRUN (def=0x0) // SmartRun domain in Run mode
  • 0x46020808PWR_CR3// PWR control register 3

    • [1]REGSEL (def=0x0) // Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SM
    • [2]FSTEN (def=0x0) // Fast soft start
  • 0x4602080CPWR_VOSR// PWR voltage scaling register

    • [14]BOOSTRDY (def=0x0) // EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached.
    • [15]VOSRDY (def=0x1) // Ready bit for VCORE voltage scaling output selection
    • [16:17]VOS (def=0x0) // Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC =
    • [18]BOOSTEN (def=0x0) // EPOD booster enable
  • 0x46020810PWR_SVMCR// PWR supply voltage monitoring control register

    • [4]PVDE (def=0x0) // Power voltage detector enable
    • [5:7]PVDLS (def=0x0) // Power voltage detector level selection These bits select the voltage threshold detected by the powe
    • [24]UVMEN (def=0x0) // VDDUSB independent USB voltage monitor enable
    • [25]IO2VMEN (def=0x0) // VDDIO2 independent I/Os voltage monitor enable
    • [26]AVM1EN (def=0x0) // VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold)
    • [27]AVM2EN (def=0x0) // VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold)
    • [28]USV (def=0x0) // VDDUSB independent USB supply valid
    • [29]IO2SV (def=0x0) // VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical
    • [30]ASV (def=0x0) // VDDA independent analog supply valid
  • 0x46020814PWR_WUCR1// PWR wakeup control register 1

    • [0]WUPEN1 (def=0x0) // Wakeup pin WKUP1 enable
    • [1]WUPEN2 (def=0x0) // Wakeup pin WKUP2 enable
    • [2]WUPEN3 (def=0x0) // Wakeup pin WKUP3 enable
    • [3]WUPEN4 (def=0x0) // Wakeup pin WKUP4 enable
    • [4]WUPEN5 (def=0x0) // Wakeup pin WKUP5 enable
    • [5]WUPEN6 (def=0x0) // Wakeup pin WKUP6 enable
    • [6]WUPEN7 (def=0x0) // Wakeup pin WKUP7 enable
    • [7]WUPEN8 (def=0x0) // Wakeup pin WKUP8 enable
  • 0x46020818PWR_WUCR2// PWR wakeup control register 2

    • [0]WUPP1 (def=0x0) // Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0.
    • [1]WUPP2 (def=0x0) // Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0.
    • [2]WUPP3 (def=0x0) // Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0.
    • [3]WUPP4 (def=0x0) // Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0.
    • [4]WUPP5 (def=0x0) // Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0.
    • [5]WUPP6 (def=0x0) // Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0.
    • [6]WUPP7 (def=0x0) // Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0.
    • [7]WUPP8 (def=0x0) // Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0.
  • 0x4602081CPWR_WUCR3// PWR wakeup control register 3

    • [0:1]WUSEL1 (def=0x0) // Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0.
    • [2:3]WUSEL2 (def=0x0) // Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0.
    • [4:5]WUSEL3 (def=0x0) // Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0.
    • [6:7]WUSEL4 (def=0x0) // Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0.
    • [8:9]WUSEL5 (def=0x0) // Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0.
    • [10:11]WUSEL6 (def=0x0) // Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0.
    • [12:13]WUSEL7 (def=0x0) // Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0.
    • [14:15]WUSEL8 (def=0x0) // Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0.
  • 0x46020820PWR_BDCR1// PWR Backup domain control register 1

    • [0]BREN (def=0x0) // Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept
    • [4]MONEN (def=0x0) // Backup domain voltage and temperature monitoring enable
  • 0x46020824PWR_BDCR2// PWR Backup domain control register 2

    • [0]VBE (def=0x0) // VBAT charging enable
    • [1]VBRS (def=0x0) // VBAT charging resistor selection
  • 0x46020828PWR_DBPR// PWR disable Backup domain register

    • [0]DBP (def=0x0) // Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are
  • 0x4602082CPWR_UCPDR// PWR USB Type-C™ and Power Delivery register

    • [0]UCPD_DBDIS (def=0x0) // UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enable
    • [1]UCPD_STBY (def=0x0) // UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. Th
  • 0x46020830PWR_SECCFGR// PWR security configuration register

    • [0]WUP1SEC (def=0x0) // WUP1 secure protection
    • [1]WUP2SEC (def=0x0) // WUP2 secure protection
    • [2]WUP3SEC (def=0x0) // WUP3 secure protection
    • [3]WUP4SEC (def=0x0) // WUP4 secure protection
    • [4]WUP5SEC (def=0x0) // WUP5 secure protection
    • [5]WUP6SEC (def=0x0) // WUP6 secure protection
    • [6]WUP7SEC (def=0x0) // WUP7 secure protection
    • [7]WUP8SEC (def=0x0) // WUP8 secure protection
    • [12]LPMSEC (def=0x0) // Low-power modes secure protection
    • [13]VDMSEC (def=0x0) // Voltage detection and monitoring secure protection
    • [14]VBSEC (def=0x0) // Backup domain secure protection
    • [15]APCSEC (def=0x0) // Pull-up/pull-down secure protection
  • 0x46020834PWR_PRIVCFGR// PWR privilege control register

    • [0]SPRIV (def=0x0) // PWR secure functions privilege configuration This bit is set and reset by software. It can be writt
    • [1]NSPRIV (def=0x0) // PWR non-secure functions privilege configuration This bit is set and reset by software. It can be w
  • 0x46020838PWR_SR// PWR status register

    • [0]CSSF (def=0x0) // Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in P
    • [1]STOPF (def=0x0) // Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by softwar
    • [2]SBF (def=0x0) // Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by
  • 0x4602083CPWR_SVMSR//

    • [1]REGS (def=0x0) // Regulator selection
    • [4]PVDO (def=0x0) // VDD voltage detector output
    • [15]ACTVOSRDY (def=0x1) // Voltage level ready for currently used VOS
    • [16:17]ACTVOS (def=0x0) // VOS currently applied to VCORE This field provides the last VOS value.
    • [24]VDDUSBRDY (def=0x0) // VDDUSB ready
    • [25]VDDIO2RDY (def=0x0) // VDDIO2 ready
    • [26]VDDA1RDY (def=0x0) // VDDA ready versus 1.6V voltage monitor
    • [27]VDDA2RDY (def=0x0) // VDDA ready versus 1.8 V voltage monitor
  • 0x46020840PWR_BDSR// PWR Backup domain status register

    • [1]VBATH (def=0x0) // Backup domain voltage level monitoring versus high threshold
    • [2]TEMPL (def=0x0) // Temperature level monitoring versus low threshold
    • [3]TEMPH (def=0x0) // Temperature level monitoring versus high threshold
  • 0x46020844PWR_WUSR// PWR wakeup status register

    • [0]WUF1 (def=0x0) // Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by
    • [1]WUF2 (def=0x0) // Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by
    • [2]WUF3 (def=0x0) // Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by
    • [3]WUF4 (def=0x0) // Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by
    • [4]WUF5 (def=0x0) // Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by
    • [5]WUF6 (def=0x0) // Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by
    • [6]WUF7 (def=0x0) // Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by
    • [7]WUF8 (def=0x0) // Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by
  • 0x46020848PWR_WUSCR// PWR wakeup status clear register

    • [0]CWUF1 (def=0x0) // Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR.
    • [1]CWUF2 (def=0x0) // Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR.
    • [2]CWUF3 (def=0x0) // Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR.
    • [3]CWUF4 (def=0x0) // Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR.
    • [4]CWUF5 (def=0x0) // Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR.
    • [5]CWUF6 (def=0x0) // Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR.
    • [6]CWUF7 (def=0x0) // Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR.
    • [7]CWUF8 (def=0x0) // Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR.
  • 0x4602084CPWR_APCR// PWR apply pull configuration register

    • [0]APC (def=0x0) // Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down confi
  • 0x46020850PWR_PUCRA// PWR port A pull-up control register

    • [0]PU0 (def=0x0) // Port A pull-up bit
    • [1]PU1 (def=0x0) // Port A pull-up bit
    • [2]PU2 (def=0x0) // Port A pull-up bit
    • [3]PU3 (def=0x0) // Port A pull-up bit
    • [4]PU4 (def=0x0) // Port A pull-up bit
    • [5]PU5 (def=0x0) // Port A pull-up bit
    • [6]PU6 (def=0x0) // Port A pull-up bit
    • [7]PU7 (def=0x0) // Port A pull-up bit
    • [8]PU8 (def=0x0) // Port A pull-up bit
    • [9]PU9 (def=0x0) // Port A pull-up bit
    • [10]PU10 (def=0x0) // Port A pull-up bit
    • [11]PU11 (def=0x0) // Port A pull-up bit
    • [12]PU12 (def=0x0) // Port A pull-up bit
    • [13]PU13 (def=0x0) // Port A pull-up bit
    • [15]PU15 (def=0x0) // Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in P
  • 0x46020854PWR_PDCRA// PWR port A pull-down control register

    • [0]PD0 (def=0x0) // Port A pull-down bit
    • [1]PD1 (def=0x0) // Port A pull-down bit
    • [2]PD2 (def=0x0) // Port A pull-down bit
    • [3]PD3 (def=0x0) // Port A pull-down bit
    • [4]PD4 (def=0x0) // Port A pull-down bit
    • [5]PD5 (def=0x0) // Port A pull-down bit
    • [6]PD6 (def=0x0) // Port A pull-down bit
    • [7]PD7 (def=0x0) // Port A pull-down bit
    • [8]PD8 (def=0x0) // Port A pull-down bit
    • [9]PD9 (def=0x0) // Port A pull-down bit
    • [10]PD10 (def=0x0) // Port A pull-down bit
    • [11]PD11 (def=0x0) // Port A pull-down bit
    • [12]PD12 (def=0x0) // Port A pull-down bit
    • [14]PD14 (def=0x0) // Port A pull-down bit
  • 0x46020858PWR_PUCRB// PWR port B pull-up control register

    • [0]PU0 (def=0x0) // Port B pull-up bit
    • [1]PU1 (def=0x0) // Port B pull-up bit
    • [2]PU2 (def=0x0) // Port B pull-up bit
    • [3]PU3 (def=0x0) // Port B pull-up bit
    • [4]PU4 (def=0x0) // Port B pull-up bit
    • [5]PU5 (def=0x0) // Port B pull-up bit
    • [6]PU6 (def=0x0) // Port B pull-up bit
    • [7]PU7 (def=0x0) // Port B pull-up bit
    • [8]PU8 (def=0x0) // Port B pull-up bit
    • [9]PU9 (def=0x0) // Port B pull-up bit
    • [10]PU10 (def=0x0) // Port B pull-up bit
    • [11]PU11 (def=0x0) // Port B pull-up bit
    • [12]PU12 (def=0x0) // Port B pull-up bit
    • [13]PU13 (def=0x0) // Port B pull-up bit
    • [14]PU14 (def=0x0) // Port B pull-up bit
    • [15]PU15 (def=0x0) // Port B pull-up bit
  • 0x4602085CPWR_PDCRB// PWR port B pull-down control register

    • [0]PD0 (def=0x0) // Port B pull-down bit
    • [1]PD1 (def=0x0) // Port B pull-down bit
    • [2]PD2 (def=0x0) // Port B pull-down bit
    • [3]PD3 (def=0x0) // Port B pull-down bit
    • [5]PD5 (def=0x0) // Port B pull-down bit
    • [6]PD6 (def=0x0) // Port B pull-down bit
    • [7]PD7 (def=0x0) // Port B pull-down bit
    • [8]PD8 (def=0x0) // Port B pull-down bit
    • [9]PD9 (def=0x0) // Port B pull-down bit
    • [10]PD10 (def=0x0) // Port B pull-down bit
    • [11]PD11 (def=0x0) // Port B pull-down bit
    • [12]PD12 (def=0x0) // Port B pull-down bit
    • [13]PD13 (def=0x0) // Port B pull-down bit
    • [14]PD14 (def=0x0) // Port B pull-down bit
    • [15]PD15 (def=0x0) // Port B pull-down bit
  • 0x46020860PWR_PUCRC// PWR port C pull-up control register

    • [0]PU0 (def=0x0) // Port C pull-up bit
    • [1]PU1 (def=0x0) // Port C pull-up bit
    • [2]PU2 (def=0x0) // Port C pull-up bit
    • [3]PU3 (def=0x0) // Port C pull-up bit
    • [4]PU4 (def=0x0) // Port C pull-up bit
    • [5]PU5 (def=0x0) // Port C pull-up bit
    • [6]PU6 (def=0x0) // Port C pull-up bit
    • [7]PU7 (def=0x0) // Port C pull-up bit
    • [8]PU8 (def=0x0) // Port C pull-up bit
    • [9]PU9 (def=0x0) // Port C pull-up bit
    • [10]PU10 (def=0x0) // Port C pull-up bit
    • [11]PU11 (def=0x0) // Port C pull-up bit
    • [12]PU12 (def=0x0) // Port C pull-up bit
    • [13]PU13 (def=0x0) // Port C pull-up bit
    • [14]PU14 (def=0x0) // Port C pull-up bit
    • [15]PU15 (def=0x0) // Port C pull-up bit
  • 0x46020864PWR_PDCRC// PWR port C pull-down control register

    • [0]PD0 (def=0x0) // Port C pull-down bit
    • [1]PD1 (def=0x0) // Port C pull-down bit
    • [2]PD2 (def=0x0) // Port C pull-down bit
    • [3]PD3 (def=0x0) // Port C pull-down bit
    • [4]PD4 (def=0x0) // Port C pull-down bit
    • [5]PD5 (def=0x0) // Port C pull-down bit
    • [6]PD6 (def=0x0) // Port C pull-down bit
    • [7]PD7 (def=0x0) // Port C pull-down bit
    • [8]PD8 (def=0x0) // Port C pull-down bit
    • [9]PD9 (def=0x0) // Port C pull-down bit
    • [10]PD10 (def=0x0) // Port C pull-down bit
    • [11]PD11 (def=0x0) // Port C pull-down bit
    • [12]PD12 (def=0x0) // Port C pull-down bit
    • [13]PD13 (def=0x0) // Port C pull-down bit
    • [14]PD14 (def=0x0) // Port C pull-down bit
    • [15]PD15 (def=0x0) // Port C pull-down bit
  • 0x46020868PWR_PUCRD// PWR port D pull-up control register

    • [0]PU0 (def=0x0) // Port D pull-up bit
    • [1]PU1 (def=0x0) // Port D pull-up bit
    • [2]PU2 (def=0x0) // Port D pull-up bit
    • [3]PU3 (def=0x0) // Port D pull-up bit
    • [4]PU4 (def=0x0) // Port D pull-up bit
    • [5]PU5 (def=0x0) // Port D pull-up bit
    • [6]PU6 (def=0x0) // Port D pull-up bit
    • [7]PU7 (def=0x0) // Port D pull-up bit
    • [8]PU8 (def=0x0) // Port D pull-up bit
    • [9]PU9 (def=0x0) // Port D pull-up bit
    • [10]PU10 (def=0x0) // Port D pull-up bit
    • [11]PU11 (def=0x0) // Port D pull-up bit
    • [12]PU12 (def=0x0) // Port D pull-up bit
    • [13]PU13 (def=0x0) // Port D pull-up bit
    • [14]PU14 (def=0x0) // Port D pull-up bit
    • [15]PU15 (def=0x0) // Port D pull-up bit
  • 0x4602086CPWR_PDCRD// PWR port D pull-down control register

    • [0]PD0 (def=0x0) // Port D pull-down bit
    • [1]PD1 (def=0x0) // Port D pull-down bit
    • [2]PD2 (def=0x0) // Port D pull-down bit
    • [3]PD3 (def=0x0) // Port D pull-down bit
    • [4]PD4 (def=0x0) // Port D pull-down bit
    • [5]PD5 (def=0x0) // Port D pull-down bit
    • [6]PD6 (def=0x0) // Port D pull-down bit
    • [7]PD7 (def=0x0) // Port D pull-down bit
    • [8]PD8 (def=0x0) // Port D pull-down bit
    • [9]PD9 (def=0x0) // Port D pull-down bit
    • [10]PD10 (def=0x0) // Port D pull-down bit
    • [11]PD11 (def=0x0) // Port D pull-down bit
    • [12]PD12 (def=0x0) // Port D pull-down bit
    • [13]PD13 (def=0x0) // Port D pull-down bit
    • [14]PD14 (def=0x0) // Port D pull-down bit
    • [15]PD15 (def=0x0) // Port D pull-down bit
  • 0x46020870PWR_PUCRE// PWR port E pull-up control register

    • [0]PU0 (def=0x0) // Port E pull-up bit
    • [1]PU1 (def=0x0) // Port E pull-up bit
    • [2]PU2 (def=0x0) // Port E pull-up bit
    • [3]PU3 (def=0x0) // Port E pull-up bit
    • [4]PU4 (def=0x0) // Port E pull-up bit
    • [5]PU5 (def=0x0) // Port E pull-up bit
    • [6]PU6 (def=0x0) // Port E pull-up bit
    • [7]PU7 (def=0x0) // Port E pull-up bit
    • [8]PU8 (def=0x0) // Port E pull-up bit
    • [9]PU9 (def=0x0) // Port E pull-up bit
    • [10]PU10 (def=0x0) // Port E pull-up bit
    • [11]PU11 (def=0x0) // Port E pull-up bit
    • [12]PU12 (def=0x0) // Port E pull-up bit
    • [13]PU13 (def=0x0) // Port E pull-up bit
    • [14]PU14 (def=0x0) // Port E pull-up bit
    • [15]PU15 (def=0x0) // Port E pull-up bit
  • 0x46020874PWR_PDCRE// PWR port E pull-down control register

    • [0]PD0 (def=0x0) // Port E pull-down bit
    • [1]PD1 (def=0x0) // Port E pull-down bit
    • [2]PD2 (def=0x0) // Port E pull-down bit
    • [3]PD3 (def=0x0) // Port E pull-down bit
    • [4]PD4 (def=0x0) // Port E pull-down bit
    • [5]PD5 (def=0x0) // Port E pull-down bit
    • [6]PD6 (def=0x0) // Port E pull-down bit
    • [7]PD7 (def=0x0) // Port E pull-down bit
    • [8]PD8 (def=0x0) // Port E pull-down bit
    • [9]PD9 (def=0x0) // Port E pull-down bit
    • [10]PD10 (def=0x0) // Port E pull-down bit
    • [11]PD11 (def=0x0) // Port E pull-down bit
    • [12]PD12 (def=0x0) // Port E pull-down bit
    • [13]PD13 (def=0x0) // Port E pull-down bit
    • [14]PD14 (def=0x0) // Port E pull-down bit
    • [15]PD15 (def=0x0) // Port E pull-down bit
  • 0x46020878PWR_PUCRF// PWR port F pull-up control register

    • [0]PU0 (def=0x0) // Port F pull-up bit
    • [1]PU1 (def=0x0) // Port F pull-up bit
    • [2]PU2 (def=0x0) // Port F pull-up bit
    • [3]PU3 (def=0x0) // Port F pull-up bit
    • [4]PU4 (def=0x0) // Port F pull-up bit
    • [5]PU5 (def=0x0) // Port F pull-up bit
    • [6]PU6 (def=0x0) // Port F pull-up bit
    • [7]PU7 (def=0x0) // Port F pull-up bit
    • [8]PU8 (def=0x0) // Port F pull-up bit
    • [9]PU9 (def=0x0) // Port F pull-up bit
    • [10]PU10 (def=0x0) // Port F pull-up bit
    • [11]PU11 (def=0x0) // Port F pull-up bit
    • [12]PU12 (def=0x0) // Port F pull-up bit
    • [13]PU13 (def=0x0) // Port F pull-up bit
    • [14]PU14 (def=0x0) // Port F pull-up bit
    • [15]PU15 (def=0x0) // Port F pull-up bit
  • 0x4602087CPWR_PDCRF// PWR port F pull-down control register

    • [0]PD0 (def=0x0) // Port F pull-down bit
    • [1]PD1 (def=0x0) // Port F pull-down bit
    • [2]PD2 (def=0x0) // Port F pull-down bit
    • [3]PD3 (def=0x0) // Port F pull-down bit
    • [4]PD4 (def=0x0) // Port F pull-down bit
    • [5]PD5 (def=0x0) // Port F pull-down bit
    • [6]PD6 (def=0x0) // Port F pull-down bit
    • [7]PD7 (def=0x0) // Port F pull-down bit
    • [8]PD8 (def=0x0) // Port F pull-down bit
    • [9]PD9 (def=0x0) // Port F pull-down bit
    • [10]PD10 (def=0x0) // Port F pull-down bit
    • [11]PD11 (def=0x0) // Port F pull-down bit
    • [12]PD12 (def=0x0) // Port F pull-down bit
    • [13]PD13 (def=0x0) // Port F pull-down bit
    • [14]PD14 (def=0x0) // Port F pull-down bit
    • [15]PD15 (def=0x0) // Port F pull-down bit
  • 0x46020880PWR_PUCRG// PWR port G pull-up control register

    • [0]PU0 (def=0x0) // Port G pull-up bit
    • [1]PU1 (def=0x0) // Port G pull-up bit
    • [2]PU2 (def=0x0) // Port G pull-up bit
    • [3]PU3 (def=0x0) // Port G pull-up bit
    • [4]PU4 (def=0x0) // Port G pull-up bit
    • [5]PU5 (def=0x0) // Port G pull-up bit
    • [6]PU6 (def=0x0) // Port G pull-up bit
    • [7]PU7 (def=0x0) // Port G pull-up bit
    • [8]PU8 (def=0x0) // Port G pull-up bit
    • [9]PU9 (def=0x0) // Port G pull-up bit
    • [10]PU10 (def=0x0) // Port G pull-up bit
    • [11]PU11 (def=0x0) // Port G pull-up bit
    • [12]PU12 (def=0x0) // Port G pull-up bit
    • [13]PU13 (def=0x0) // Port G pull-up bit
    • [14]PU14 (def=0x0) // Port G pull-up bit
    • [15]PU15 (def=0x0) // Port G pull-up bit
  • 0x46020884PWR_PDCRG// PWR port G pull-down control register

    • [0]PD0 (def=0x0) // Port G pull-down bit
    • [1]PD1 (def=0x0) // Port G pull-down bit
    • [2]PD2 (def=0x0) // Port G pull-down bit
    • [3]PD3 (def=0x0) // Port G pull-down bit
    • [4]PD4 (def=0x0) // Port G pull-down bit
    • [5]PD5 (def=0x0) // Port G pull-down bit
    • [6]PD6 (def=0x0) // Port G pull-down bit
    • [7]PD7 (def=0x0) // Port G pull-down bit
    • [8]PD8 (def=0x0) // Port G pull-down bit
    • [9]PD9 (def=0x0) // Port G pull-down bit
    • [10]PD10 (def=0x0) // Port G pull-down bit
    • [11]PD11 (def=0x0) // Port G pull-down bit
    • [12]PD12 (def=0x0) // Port G pull-down bit
    • [13]PD13 (def=0x0) // Port G pull-down bit
    • [14]PD14 (def=0x0) // Port G pull-down bit
    • [15]PD15 (def=0x0) // Port G pull-down bit
  • 0x46020888PWR_PUCRH// PWR port H pull-up control register

    • [0]PU0 (def=0x0) // Port H pull-up bit
    • [1]PU1 (def=0x0) // Port H pull-up bit
    • [2]PU2 (def=0x0) // Port H pull-up bit
    • [3]PU3 (def=0x0) // Port H pull-up bit
    • [4]PU4 (def=0x0) // Port H pull-up bit
    • [5]PU5 (def=0x0) // Port H pull-up bit
    • [6]PU6 (def=0x0) // Port H pull-up bit
    • [7]PU7 (def=0x0) // Port H pull-up bit
    • [8]PU8 (def=0x0) // Port H pull-up bit
    • [9]PU9 (def=0x0) // Port H pull-up bit
    • [10]PU10 (def=0x0) // Port H pull-up bit
    • [11]PU11 (def=0x0) // Port H pull-up bit
    • [12]PU12 (def=0x0) // Port H pull-up bit
    • [13]PU13 (def=0x0) // Port H pull-up bit
    • [14]PU14 (def=0x0) // Port H pull-up bit
    • [15]PU15 (def=0x0) // Port H pull-up bit
  • 0x4602088CPWR_PDCRH// PWR port H pull-down control register

    • [0]PD0 (def=0x0) // Port H pull-down bit
    • [1]PD1 (def=0x0) // Port H pull-down bit
    • [2]PD2 (def=0x0) // Port H pull-down bit
    • [3]PD3 (def=0x0) // Port H pull-down bit
    • [4]PD4 (def=0x0) // Port H pull-down bit
    • [5]PD5 (def=0x0) // Port H pull-down bit
    • [6]PD6 (def=0x0) // Port H pull-down bit
    • [7]PD7 (def=0x0) // Port H pull-down bit
    • [8]PD8 (def=0x0) // Port H pull-down bit
    • [9]PD9 (def=0x0) // Port H pull-down bit
    • [10]PD10 (def=0x0) // Port H pull-down bit
    • [11]PD11 (def=0x0) // Port H pull-down bit
    • [12]PD12 (def=0x0) // Port H pull-down bit
    • [13]PD13 (def=0x0) // Port H pull-down bit
    • [14]PD14 (def=0x0) // Port H pull-down bit
    • [15]PD15 (def=0x0) // Port H pull-down bit
  • 0x46020890PWR_PUCRI// PWR port I pull-up control register

    • [0]PU0 (def=0x0) // Port I pull-up bit
    • [1]PU1 (def=0x0) // Port I pull-up bit
    • [2]PU2 (def=0x0) // Port I pull-up bit
    • [3]PU3 (def=0x0) // Port I pull-up bit
    • [4]PU4 (def=0x0) // Port I pull-up bit
    • [5]PU5 (def=0x0) // Port I pull-up bit
    • [6]PU6 (def=0x0) // Port I pull-up bit
    • [7]PU7 (def=0x0) // Port I pull-up bit
  • 0x46020894PWR_PDCRI// PWR port I pull-down control register

    • [0]PD0 (def=0x0) // Port I pull-down bit
    • [1]PD1 (def=0x0) // Port I pull-down bit
    • [2]PD2 (def=0x0) // Port I pull-down bit
    • [3]PD3 (def=0x0) // Port I pull-down bit
    • [4]PD4 (def=0x0) // Port I pull-down bit
    • [5]PD5 (def=0x0) // Port I pull-down bit
    • [6]PD6 (def=0x0) // Port I pull-down bit
    • [7]PD7 (def=0x0) // Port I pull-down bit
  interrupts:
  • [63] PWR_S3WU // PWR wakeup from Stop 3 interrupt
• 0x56020800SEC_PWR//

  • 0x56020800PWR_CR1// PWR control register 1

    • [0:2]LPMS (def=0x0) // Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deeps
    • [5]RRSB1 (def=0x0) // SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 conten
    • [6]RRSB2 (def=0x0) // SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 conten
    • [7]ULPMEN (def=0x0) // BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in disco
    • [8]SRAM1PD (def=0x0) // SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1.
    • [9]SRAM2PD (def=0x0) // SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2.
    • [10]SRAM3PD (def=0x0) // SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3.
    • [11]SRAM4PD (def=0x0) // SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4.
  • 0x56020804PWR_CR2// PWR control register 2

    • [0]SRAM1PDS1 (def=0x0) // SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [1]SRAM1PDS2 (def=0x0) // SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [2]SRAM1PDS3 (def=0x0) // SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [4]SRAM2PDS1 (def=0x0) // SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in
    • [5]SRAM2PDS2 (def=0x0) // SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention i
    • [6]SRAM4PDS (def=0x0) // SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)
    • [8]ICRAMPDS (def=0x0) // ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [9]DC1RAMPDS (def=0x0) // DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [10]DMA2DRAMPDS (def=0x0) // DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [11]PRAMPDS (def=0x0) // FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
    • [12]PKARAMPDS (def=0x0) // PKA SRAM power-down
    • [13]SRAM4FWU (def=0x0) // SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-of
    • [14]FLASHFWU (def=0x0) // Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off
    • [16]SRAM3PDS1 (def=0x0) // SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [17]SRAM3PDS2 (def=0x0) // SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [18]SRAM3PDS3 (def=0x0) // SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [19]SRAM3PDS4 (def=0x0) // SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [20]SRAM3PDS5 (def=0x0) // SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [21]SRAM3PDS6 (def=0x0) // SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [22]SRAM3PDS7 (def=0x0) // SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [23]SRAM3PDS8 (def=0x0) // SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
    • [31]SRDRUN (def=0x0) // SmartRun domain in Run mode
  • 0x56020808PWR_CR3// PWR control register 3

    • [1]REGSEL (def=0x0) // Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SM
    • [2]FSTEN (def=0x0) // Fast soft start
  • 0x5602080CPWR_VOSR// PWR voltage scaling register

    • [14]BOOSTRDY (def=0x0) // EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached.
    • [15]VOSRDY (def=0x1) // Ready bit for VCORE voltage scaling output selection
    • [16:17]VOS (def=0x0) // Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC =
    • [18]BOOSTEN (def=0x0) // EPOD booster enable
  • 0x56020810PWR_SVMCR// PWR supply voltage monitoring control register

    • [4]PVDE (def=0x0) // Power voltage detector enable
    • [5:7]PVDLS (def=0x0) // Power voltage detector level selection These bits select the voltage threshold detected by the powe
    • [24]UVMEN (def=0x0) // VDDUSB independent USB voltage monitor enable
    • [25]IO2VMEN (def=0x0) // VDDIO2 independent I/Os voltage monitor enable
    • [26]AVM1EN (def=0x0) // VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold)
    • [27]AVM2EN (def=0x0) // VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold)
    • [28]USV (def=0x0) // VDDUSB independent USB supply valid
    • [29]IO2SV (def=0x0) // VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical
    • [30]ASV (def=0x0) // VDDA independent analog supply valid
  • 0x56020814PWR_WUCR1// PWR wakeup control register 1

    • [0]WUPEN1 (def=0x0) // Wakeup pin WKUP1 enable
    • [1]WUPEN2 (def=0x0) // Wakeup pin WKUP2 enable
    • [2]WUPEN3 (def=0x0) // Wakeup pin WKUP3 enable
    • [3]WUPEN4 (def=0x0) // Wakeup pin WKUP4 enable
    • [4]WUPEN5 (def=0x0) // Wakeup pin WKUP5 enable
    • [5]WUPEN6 (def=0x0) // Wakeup pin WKUP6 enable
    • [6]WUPEN7 (def=0x0) // Wakeup pin WKUP7 enable
    • [7]WUPEN8 (def=0x0) // Wakeup pin WKUP8 enable
  • 0x56020818PWR_WUCR2// PWR wakeup control register 2

    • [0]WUPP1 (def=0x0) // Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0.
    • [1]WUPP2 (def=0x0) // Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0.
    • [2]WUPP3 (def=0x0) // Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0.
    • [3]WUPP4 (def=0x0) // Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0.
    • [4]WUPP5 (def=0x0) // Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0.
    • [5]WUPP6 (def=0x0) // Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0.
    • [6]WUPP7 (def=0x0) // Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0.
    • [7]WUPP8 (def=0x0) // Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0.
  • 0x5602081CPWR_WUCR3// PWR wakeup control register 3

    • [0:1]WUSEL1 (def=0x0) // Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0.
    • [2:3]WUSEL2 (def=0x0) // Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0.
    • [4:5]WUSEL3 (def=0x0) // Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0.
    • [6:7]WUSEL4 (def=0x0) // Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0.
    • [8:9]WUSEL5 (def=0x0) // Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0.
    • [10:11]WUSEL6 (def=0x0) // Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0.
    • [12:13]WUSEL7 (def=0x0) // Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0.
    • [14:15]WUSEL8 (def=0x0) // Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0.
  • 0x56020820PWR_BDCR1// PWR Backup domain control register 1

    • [0]BREN (def=0x0) // Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept
    • [4]MONEN (def=0x0) // Backup domain voltage and temperature monitoring enable
  • 0x56020824PWR_BDCR2// PWR Backup domain control register 2

    • [0]VBE (def=0x0) // VBAT charging enable
    • [1]VBRS (def=0x0) // VBAT charging resistor selection
  • 0x56020828PWR_DBPR// PWR disable Backup domain register

    • [0]DBP (def=0x0) // Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are
  • 0x5602082CPWR_UCPDR// PWR USB Type-C™ and Power Delivery register

    • [0]UCPD_DBDIS (def=0x0) // UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enable
    • [1]UCPD_STBY (def=0x0) // UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. Th
  • 0x56020830PWR_SECCFGR// PWR security configuration register

    • [0]WUP1SEC (def=0x0) // WUP1 secure protection
    • [1]WUP2SEC (def=0x0) // WUP2 secure protection
    • [2]WUP3SEC (def=0x0) // WUP3 secure protection
    • [3]WUP4SEC (def=0x0) // WUP4 secure protection
    • [4]WUP5SEC (def=0x0) // WUP5 secure protection
    • [5]WUP6SEC (def=0x0) // WUP6 secure protection
    • [6]WUP7SEC (def=0x0) // WUP7 secure protection
    • [7]WUP8SEC (def=0x0) // WUP8 secure protection
    • [12]LPMSEC (def=0x0) // Low-power modes secure protection
    • [13]VDMSEC (def=0x0) // Voltage detection and monitoring secure protection
    • [14]VBSEC (def=0x0) // Backup domain secure protection
    • [15]APCSEC (def=0x0) // Pull-up/pull-down secure protection
  • 0x56020834PWR_PRIVCFGR// PWR privilege control register

    • [0]SPRIV (def=0x0) // PWR secure functions privilege configuration This bit is set and reset by software. It can be writt
    • [1]NSPRIV (def=0x0) // PWR non-secure functions privilege configuration This bit is set and reset by software. It can be w
  • 0x56020838PWR_SR// PWR status register

    • [0]CSSF (def=0x0) // Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in P
    • [1]STOPF (def=0x0) // Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by softwar
    • [2]SBF (def=0x0) // Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by
  • 0x5602083CPWR_SVMSR//

    • [1]REGS (def=0x0) // Regulator selection
    • [4]PVDO (def=0x0) // VDD voltage detector output
    • [15]ACTVOSRDY (def=0x1) // Voltage level ready for currently used VOS
    • [16:17]ACTVOS (def=0x0) // VOS currently applied to VCORE This field provides the last VOS value.
    • [24]VDDUSBRDY (def=0x0) // VDDUSB ready
    • [25]VDDIO2RDY (def=0x0) // VDDIO2 ready
    • [26]VDDA1RDY (def=0x0) // VDDA ready versus 1.6V voltage monitor
    • [27]VDDA2RDY (def=0x0) // VDDA ready versus 1.8 V voltage monitor
  • 0x56020840PWR_BDSR// PWR Backup domain status register

    • [1]VBATH (def=0x0) // Backup domain voltage level monitoring versus high threshold
    • [2]TEMPL (def=0x0) // Temperature level monitoring versus low threshold
    • [3]TEMPH (def=0x0) // Temperature level monitoring versus high threshold
  • 0x56020844PWR_WUSR// PWR wakeup status register

    • [0]WUF1 (def=0x0) // Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by
    • [1]WUF2 (def=0x0) // Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by
    • [2]WUF3 (def=0x0) // Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by
    • [3]WUF4 (def=0x0) // Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by
    • [4]WUF5 (def=0x0) // Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by
    • [5]WUF6 (def=0x0) // Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by
    • [6]WUF7 (def=0x0) // Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by
    • [7]WUF8 (def=0x0) // Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by
  • 0x56020848PWR_WUSCR// PWR wakeup status clear register

    • [0]CWUF1 (def=0x0) // Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR.
    • [1]CWUF2 (def=0x0) // Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR.
    • [2]CWUF3 (def=0x0) // Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR.
    • [3]CWUF4 (def=0x0) // Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR.
    • [4]CWUF5 (def=0x0) // Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR.
    • [5]CWUF6 (def=0x0) // Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR.
    • [6]CWUF7 (def=0x0) // Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR.
    • [7]CWUF8 (def=0x0) // Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR.
  • 0x5602084CPWR_APCR// PWR apply pull configuration register

    • [0]APC (def=0x0) // Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down confi
  • 0x56020850PWR_PUCRA// PWR port A pull-up control register

    • [0]PU0 (def=0x0) // Port A pull-up bit
    • [1]PU1 (def=0x0) // Port A pull-up bit
    • [2]PU2 (def=0x0) // Port A pull-up bit
    • [3]PU3 (def=0x0) // Port A pull-up bit
    • [4]PU4 (def=0x0) // Port A pull-up bit
    • [5]PU5 (def=0x0) // Port A pull-up bit
    • [6]PU6 (def=0x0) // Port A pull-up bit
    • [7]PU7 (def=0x0) // Port A pull-up bit
    • [8]PU8 (def=0x0) // Port A pull-up bit
    • [9]PU9 (def=0x0) // Port A pull-up bit
    • [10]PU10 (def=0x0) // Port A pull-up bit
    • [11]PU11 (def=0x0) // Port A pull-up bit
    • [12]PU12 (def=0x0) // Port A pull-up bit
    • [13]PU13 (def=0x0) // Port A pull-up bit
    • [15]PU15 (def=0x0) // Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in P
  • 0x56020854PWR_PDCRA// PWR port A pull-down control register

    • [0]PD0 (def=0x0) // Port A pull-down bit
    • [1]PD1 (def=0x0) // Port A pull-down bit
    • [2]PD2 (def=0x0) // Port A pull-down bit
    • [3]PD3 (def=0x0) // Port A pull-down bit
    • [4]PD4 (def=0x0) // Port A pull-down bit
    • [5]PD5 (def=0x0) // Port A pull-down bit
    • [6]PD6 (def=0x0) // Port A pull-down bit
    • [7]PD7 (def=0x0) // Port A pull-down bit
    • [8]PD8 (def=0x0) // Port A pull-down bit
    • [9]PD9 (def=0x0) // Port A pull-down bit
    • [10]PD10 (def=0x0) // Port A pull-down bit
    • [11]PD11 (def=0x0) // Port A pull-down bit
    • [12]PD12 (def=0x0) // Port A pull-down bit
    • [14]PD14 (def=0x0) // Port A pull-down bit
  • 0x56020858PWR_PUCRB// PWR port B pull-up control register

    • [0]PU0 (def=0x0) // Port B pull-up bit
    • [1]PU1 (def=0x0) // Port B pull-up bit
    • [2]PU2 (def=0x0) // Port B pull-up bit
    • [3]PU3 (def=0x0) // Port B pull-up bit
    • [4]PU4 (def=0x0) // Port B pull-up bit
    • [5]PU5 (def=0x0) // Port B pull-up bit
    • [6]PU6 (def=0x0) // Port B pull-up bit
    • [7]PU7 (def=0x0) // Port B pull-up bit
    • [8]PU8 (def=0x0) // Port B pull-up bit
    • [9]PU9 (def=0x0) // Port B pull-up bit
    • [10]PU10 (def=0x0) // Port B pull-up bit
    • [11]PU11 (def=0x0) // Port B pull-up bit
    • [12]PU12 (def=0x0) // Port B pull-up bit
    • [13]PU13 (def=0x0) // Port B pull-up bit
    • [14]PU14 (def=0x0) // Port B pull-up bit
    • [15]PU15 (def=0x0) // Port B pull-up bit
  • 0x5602085CPWR_PDCRB// PWR port B pull-down control register

    • [0]PD0 (def=0x0) // Port B pull-down bit
    • [1]PD1 (def=0x0) // Port B pull-down bit
    • [2]PD2 (def=0x0) // Port B pull-down bit
    • [3]PD3 (def=0x0) // Port B pull-down bit
    • [5]PD5 (def=0x0) // Port B pull-down bit
    • [6]PD6 (def=0x0) // Port B pull-down bit
    • [7]PD7 (def=0x0) // Port B pull-down bit
    • [8]PD8 (def=0x0) // Port B pull-down bit
    • [9]PD9 (def=0x0) // Port B pull-down bit
    • [10]PD10 (def=0x0) // Port B pull-down bit
    • [11]PD11 (def=0x0) // Port B pull-down bit
    • [12]PD12 (def=0x0) // Port B pull-down bit
    • [13]PD13 (def=0x0) // Port B pull-down bit
    • [14]PD14 (def=0x0) // Port B pull-down bit
    • [15]PD15 (def=0x0) // Port B pull-down bit
  • 0x56020860PWR_PUCRC// PWR port C pull-up control register

    • [0]PU0 (def=0x0) // Port C pull-up bit
    • [1]PU1 (def=0x0) // Port C pull-up bit
    • [2]PU2 (def=0x0) // Port C pull-up bit
    • [3]PU3 (def=0x0) // Port C pull-up bit
    • [4]PU4 (def=0x0) // Port C pull-up bit
    • [5]PU5 (def=0x0) // Port C pull-up bit
    • [6]PU6 (def=0x0) // Port C pull-up bit
    • [7]PU7 (def=0x0) // Port C pull-up bit
    • [8]PU8 (def=0x0) // Port C pull-up bit
    • [9]PU9 (def=0x0) // Port C pull-up bit
    • [10]PU10 (def=0x0) // Port C pull-up bit
    • [11]PU11 (def=0x0) // Port C pull-up bit
    • [12]PU12 (def=0x0) // Port C pull-up bit
    • [13]PU13 (def=0x0) // Port C pull-up bit
    • [14]PU14 (def=0x0) // Port C pull-up bit
    • [15]PU15 (def=0x0) // Port C pull-up bit
  • 0x56020864PWR_PDCRC// PWR port C pull-down control register

    • [0]PD0 (def=0x0) // Port C pull-down bit
    • [1]PD1 (def=0x0) // Port C pull-down bit
    • [2]PD2 (def=0x0) // Port C pull-down bit
    • [3]PD3 (def=0x0) // Port C pull-down bit
    • [4]PD4 (def=0x0) // Port C pull-down bit
    • [5]PD5 (def=0x0) // Port C pull-down bit
    • [6]PD6 (def=0x0) // Port C pull-down bit
    • [7]PD7 (def=0x0) // Port C pull-down bit
    • [8]PD8 (def=0x0) // Port C pull-down bit
    • [9]PD9 (def=0x0) // Port C pull-down bit
    • [10]PD10 (def=0x0) // Port C pull-down bit
    • [11]PD11 (def=0x0) // Port C pull-down bit
    • [12]PD12 (def=0x0) // Port C pull-down bit
    • [13]PD13 (def=0x0) // Port C pull-down bit
    • [14]PD14 (def=0x0) // Port C pull-down bit
    • [15]PD15 (def=0x0) // Port C pull-down bit
  • 0x56020868PWR_PUCRD// PWR port D pull-up control register

    • [0]PU0 (def=0x0) // Port D pull-up bit
    • [1]PU1 (def=0x0) // Port D pull-up bit
    • [2]PU2 (def=0x0) // Port D pull-up bit
    • [3]PU3 (def=0x0) // Port D pull-up bit
    • [4]PU4 (def=0x0) // Port D pull-up bit
    • [5]PU5 (def=0x0) // Port D pull-up bit
    • [6]PU6 (def=0x0) // Port D pull-up bit
    • [7]PU7 (def=0x0) // Port D pull-up bit
    • [8]PU8 (def=0x0) // Port D pull-up bit
    • [9]PU9 (def=0x0) // Port D pull-up bit
    • [10]PU10 (def=0x0) // Port D pull-up bit
    • [11]PU11 (def=0x0) // Port D pull-up bit
    • [12]PU12 (def=0x0) // Port D pull-up bit
    • [13]PU13 (def=0x0) // Port D pull-up bit
    • [14]PU14 (def=0x0) // Port D pull-up bit
    • [15]PU15 (def=0x0) // Port D pull-up bit
  • 0x5602086CPWR_PDCRD// PWR port D pull-down control register

    • [0]PD0 (def=0x0) // Port D pull-down bit
    • [1]PD1 (def=0x0) // Port D pull-down bit
    • [2]PD2 (def=0x0) // Port D pull-down bit
    • [3]PD3 (def=0x0) // Port D pull-down bit
    • [4]PD4 (def=0x0) // Port D pull-down bit
    • [5]PD5 (def=0x0) // Port D pull-down bit
    • [6]PD6 (def=0x0) // Port D pull-down bit
    • [7]PD7 (def=0x0) // Port D pull-down bit
    • [8]PD8 (def=0x0) // Port D pull-down bit
    • [9]PD9 (def=0x0) // Port D pull-down bit
    • [10]PD10 (def=0x0) // Port D pull-down bit
    • [11]PD11 (def=0x0) // Port D pull-down bit
    • [12]PD12 (def=0x0) // Port D pull-down bit
    • [13]PD13 (def=0x0) // Port D pull-down bit
    • [14]PD14 (def=0x0) // Port D pull-down bit
    • [15]PD15 (def=0x0) // Port D pull-down bit
  • 0x56020870PWR_PUCRE// PWR port E pull-up control register

    • [0]PU0 (def=0x0) // Port E pull-up bit
    • [1]PU1 (def=0x0) // Port E pull-up bit
    • [2]PU2 (def=0x0) // Port E pull-up bit
    • [3]PU3 (def=0x0) // Port E pull-up bit
    • [4]PU4 (def=0x0) // Port E pull-up bit
    • [5]PU5 (def=0x0) // Port E pull-up bit
    • [6]PU6 (def=0x0) // Port E pull-up bit
    • [7]PU7 (def=0x0) // Port E pull-up bit
    • [8]PU8 (def=0x0) // Port E pull-up bit
    • [9]PU9 (def=0x0) // Port E pull-up bit
    • [10]PU10 (def=0x0) // Port E pull-up bit
    • [11]PU11 (def=0x0) // Port E pull-up bit
    • [12]PU12 (def=0x0) // Port E pull-up bit
    • [13]PU13 (def=0x0) // Port E pull-up bit
    • [14]PU14 (def=0x0) // Port E pull-up bit
    • [15]PU15 (def=0x0) // Port E pull-up bit
  • 0x56020874PWR_PDCRE// PWR port E pull-down control register

    • [0]PD0 (def=0x0) // Port E pull-down bit
    • [1]PD1 (def=0x0) // Port E pull-down bit
    • [2]PD2 (def=0x0) // Port E pull-down bit
    • [3]PD3 (def=0x0) // Port E pull-down bit
    • [4]PD4 (def=0x0) // Port E pull-down bit
    • [5]PD5 (def=0x0) // Port E pull-down bit
    • [6]PD6 (def=0x0) // Port E pull-down bit
    • [7]PD7 (def=0x0) // Port E pull-down bit
    • [8]PD8 (def=0x0) // Port E pull-down bit
    • [9]PD9 (def=0x0) // Port E pull-down bit
    • [10]PD10 (def=0x0) // Port E pull-down bit
    • [11]PD11 (def=0x0) // Port E pull-down bit
    • [12]PD12 (def=0x0) // Port E pull-down bit
    • [13]PD13 (def=0x0) // Port E pull-down bit
    • [14]PD14 (def=0x0) // Port E pull-down bit
    • [15]PD15 (def=0x0) // Port E pull-down bit
  • 0x56020878PWR_PUCRF// PWR port F pull-up control register

    • [0]PU0 (def=0x0) // Port F pull-up bit
    • [1]PU1 (def=0x0) // Port F pull-up bit
    • [2]PU2 (def=0x0) // Port F pull-up bit
    • [3]PU3 (def=0x0) // Port F pull-up bit
    • [4]PU4 (def=0x0) // Port F pull-up bit
    • [5]PU5 (def=0x0) // Port F pull-up bit
    • [6]PU6 (def=0x0) // Port F pull-up bit
    • [7]PU7 (def=0x0) // Port F pull-up bit
    • [8]PU8 (def=0x0) // Port F pull-up bit
    • [9]PU9 (def=0x0) // Port F pull-up bit
    • [10]PU10 (def=0x0) // Port F pull-up bit
    • [11]PU11 (def=0x0) // Port F pull-up bit
    • [12]PU12 (def=0x0) // Port F pull-up bit
    • [13]PU13 (def=0x0) // Port F pull-up bit
    • [14]PU14 (def=0x0) // Port F pull-up bit
    • [15]PU15 (def=0x0) // Port F pull-up bit
  • 0x5602087CPWR_PDCRF// PWR port F pull-down control register

    • [0]PD0 (def=0x0) // Port F pull-down bit
    • [1]PD1 (def=0x0) // Port F pull-down bit
    • [2]PD2 (def=0x0) // Port F pull-down bit
    • [3]PD3 (def=0x0) // Port F pull-down bit
    • [4]PD4 (def=0x0) // Port F pull-down bit
    • [5]PD5 (def=0x0) // Port F pull-down bit
    • [6]PD6 (def=0x0) // Port F pull-down bit
    • [7]PD7 (def=0x0) // Port F pull-down bit
    • [8]PD8 (def=0x0) // Port F pull-down bit
    • [9]PD9 (def=0x0) // Port F pull-down bit
    • [10]PD10 (def=0x0) // Port F pull-down bit
    • [11]PD11 (def=0x0) // Port F pull-down bit
    • [12]PD12 (def=0x0) // Port F pull-down bit
    • [13]PD13 (def=0x0) // Port F pull-down bit
    • [14]PD14 (def=0x0) // Port F pull-down bit
    • [15]PD15 (def=0x0) // Port F pull-down bit
  • 0x56020880PWR_PUCRG// PWR port G pull-up control register

    • [0]PU0 (def=0x0) // Port G pull-up bit
    • [1]PU1 (def=0x0) // Port G pull-up bit
    • [2]PU2 (def=0x0) // Port G pull-up bit
    • [3]PU3 (def=0x0) // Port G pull-up bit
    • [4]PU4 (def=0x0) // Port G pull-up bit
    • [5]PU5 (def=0x0) // Port G pull-up bit
    • [6]PU6 (def=0x0) // Port G pull-up bit
    • [7]PU7 (def=0x0) // Port G pull-up bit
    • [8]PU8 (def=0x0) // Port G pull-up bit
    • [9]PU9 (def=0x0) // Port G pull-up bit
    • [10]PU10 (def=0x0) // Port G pull-up bit
    • [11]PU11 (def=0x0) // Port G pull-up bit
    • [12]PU12 (def=0x0) // Port G pull-up bit
    • [13]PU13 (def=0x0) // Port G pull-up bit
    • [14]PU14 (def=0x0) // Port G pull-up bit
    • [15]PU15 (def=0x0) // Port G pull-up bit
  • 0x56020884PWR_PDCRG// PWR port G pull-down control register

    • [0]PD0 (def=0x0) // Port G pull-down bit
    • [1]PD1 (def=0x0) // Port G pull-down bit
    • [2]PD2 (def=0x0) // Port G pull-down bit
    • [3]PD3 (def=0x0) // Port G pull-down bit
    • [4]PD4 (def=0x0) // Port G pull-down bit
    • [5]PD5 (def=0x0) // Port G pull-down bit
    • [6]PD6 (def=0x0) // Port G pull-down bit
    • [7]PD7 (def=0x0) // Port G pull-down bit
    • [8]PD8 (def=0x0) // Port G pull-down bit
    • [9]PD9 (def=0x0) // Port G pull-down bit
    • [10]PD10 (def=0x0) // Port G pull-down bit
    • [11]PD11 (def=0x0) // Port G pull-down bit
    • [12]PD12 (def=0x0) // Port G pull-down bit
    • [13]PD13 (def=0x0) // Port G pull-down bit
    • [14]PD14 (def=0x0) // Port G pull-down bit
    • [15]PD15 (def=0x0) // Port G pull-down bit
  • 0x56020888PWR_PUCRH// PWR port H pull-up control register

    • [0]PU0 (def=0x0) // Port H pull-up bit
    • [1]PU1 (def=0x0) // Port H pull-up bit
    • [2]PU2 (def=0x0) // Port H pull-up bit
    • [3]PU3 (def=0x0) // Port H pull-up bit
    • [4]PU4 (def=0x0) // Port H pull-up bit
    • [5]PU5 (def=0x0) // Port H pull-up bit
    • [6]PU6 (def=0x0) // Port H pull-up bit
    • [7]PU7 (def=0x0) // Port H pull-up bit
    • [8]PU8 (def=0x0) // Port H pull-up bit
    • [9]PU9 (def=0x0) // Port H pull-up bit
    • [10]PU10 (def=0x0) // Port H pull-up bit
    • [11]PU11 (def=0x0) // Port H pull-up bit
    • [12]PU12 (def=0x0) // Port H pull-up bit
    • [13]PU13 (def=0x0) // Port H pull-up bit
    • [14]PU14 (def=0x0) // Port H pull-up bit
    • [15]PU15 (def=0x0) // Port H pull-up bit
  • 0x5602088CPWR_PDCRH// PWR port H pull-down control register

    • [0]PD0 (def=0x0) // Port H pull-down bit
    • [1]PD1 (def=0x0) // Port H pull-down bit
    • [2]PD2 (def=0x0) // Port H pull-down bit
    • [3]PD3 (def=0x0) // Port H pull-down bit
    • [4]PD4 (def=0x0) // Port H pull-down bit
    • [5]PD5 (def=0x0) // Port H pull-down bit
    • [6]PD6 (def=0x0) // Port H pull-down bit
    • [7]PD7 (def=0x0) // Port H pull-down bit
    • [8]PD8 (def=0x0) // Port H pull-down bit
    • [9]PD9 (def=0x0) // Port H pull-down bit
    • [10]PD10 (def=0x0) // Port H pull-down bit
    • [11]PD11 (def=0x0) // Port H pull-down bit
    • [12]PD12 (def=0x0) // Port H pull-down bit
    • [13]PD13 (def=0x0) // Port H pull-down bit
    • [14]PD14 (def=0x0) // Port H pull-down bit
    • [15]PD15 (def=0x0) // Port H pull-down bit
  • 0x56020890PWR_PUCRI// PWR port I pull-up control register

    • [0]PU0 (def=0x0) // Port I pull-up bit
    • [1]PU1 (def=0x0) // Port I pull-up bit
    • [2]PU2 (def=0x0) // Port I pull-up bit
    • [3]PU3 (def=0x0) // Port I pull-up bit
    • [4]PU4 (def=0x0) // Port I pull-up bit
    • [5]PU5 (def=0x0) // Port I pull-up bit
    • [6]PU6 (def=0x0) // Port I pull-up bit
    • [7]PU7 (def=0x0) // Port I pull-up bit
  • 0x56020894PWR_PDCRI// PWR port I pull-down control register

    • [0]PD0 (def=0x0) // Port I pull-down bit
    • [1]PD1 (def=0x0) // Port I pull-down bit
    • [2]PD2 (def=0x0) // Port I pull-down bit
    • [3]PD3 (def=0x0) // Port I pull-down bit
    • [4]PD4 (def=0x0) // Port I pull-down bit
    • [5]PD5 (def=0x0) // Port I pull-down bit
    • [6]PD6 (def=0x0) // Port I pull-down bit
    • [7]PD7 (def=0x0) // Port I pull-down bit
• 0x46020C00RCC// Reset and clock control

  • 0x46020C00RCC_CR// RCC clock control register

    • [0]MSISON (def=0x1) // MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MS
    • [1]MSIKERON (def=0x0) // MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even
    • [2]MSISRDY (def=0x1) // MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. I
    • [3]MSIPLLEN (def=0x0) // MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of
    • [4]MSIKON (def=0x1) // MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MS
    • [5]MSIKRDY (def=0x1) // MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set on
    • [6]MSIPLLSEL (def=0x0) // MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI outpu
    • [7]MSIPLLFAST (def=0x0) // MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode
    • [8]HSION (def=0x0) // HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the H
    • [9]HSIKERON (def=0x0) // HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON
    • [10]HSIRDY (def=0x0) // HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It
    • [12]HSI48ON (def=0x0) // HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the H
    • [13]HSI48RDY (def=0x0) // HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Iti
    • [14]SHSION (def=0x0) // SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SH
    • [15]SHSIRDY (def=0x0) // SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. I
    • [16]HSEON (def=0x0) // HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE
    • [17]HSERDY (def=0x0) // HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Not
    • [18]HSEBYP (def=0x0) // HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with
    • [19]CSSON (def=0x0) // Clock security system enable This bit is set by software to enable the clock security system. When
    • [20]HSEEXT (def=0x0) // HSE external clock bypass mode This bit is set and reset by software to select the external clock m
    • [24]PLL1ON (def=0x0) // PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardwa
    • [25]PLL1RDY (def=0x0) // PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked.
    • [26]PLL2ON (def=0x0) // PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when
    • [27]PLL2RDY (def=0x0) // PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked.
    • [28]PLL3ON (def=0x0) // PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when
    • [29]PLL3RDY (def=0x0) // PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked.
  • 0x46020C08RCC_ICSCR1// RCC internal clock sources calibration register 1

    • [0:4]MSICAL3 (def=0x0) // MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the fac
    • [5:9]MSICAL2 (def=0x0) // MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the fact
    • [10:14]MSICAL1 (def=0x0) // MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the facto
    • [15:19]MSICAL0 (def=0x0) // MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the facto
    • [22]MSIBIAS (def=0x0) // MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MS
    • [23]MSIRGSEL (def=0x0) // MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with
    • [24:27]MSIKRANGE (def=0x4) // MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscil
    • [28:31]MSISRANGE (def=0x4) // MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscil
  • 0x46020C0CRCC_ICSCR2// RCC internal clock sources calibration register 2

    • [0:4]MSITRIM3 (def=0x10) // MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming
    • [5:9]MSITRIM2 (def=0x10) // MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming v
    • [10:14]MSITRIM1 (def=0x10) // MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming va
    • [15:19]MSITRIM0 (def=0x10) // MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming va
  • 0x46020C10RCC_ICSCR3// RCC internal clock sources calibration register 3

    • [0:11]HSICAL (def=0x0) // HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibra
    • [16:20]HSITRIM (def=0x10) // HSI clock trimming These bits provide an additional user-programmable trimming value that is added
  • 0x46020C14RCC_CRRCR// RCC clock recovery RC register

    • [0:8]HSI48CAL (def=0x0) // HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 cal
  • 0x46020C1CRCC_CFGR1// RCC clock configuration register 1

    • [0:1]SW (def=0x0) // system clock switch This bitfield is set and cleared by software to select system clock source (SYS
    • [2:3]SWS (def=0x0) // system clock switch status This bitfield is set and cleared by hardware to indicate which clock sou
    • [4]STOPWUCK (def=0x0) // wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select
    • [5]STOPKERWUCK (def=0x0) // wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software t
    • [24:27]MCOSEL (def=0x0) // microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: T
    • [28:30]MCOPRE (def=0x0) // microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly r
  • 0x46020C20RCC_CFGR2// RCC clock configuration register 2

    • [0:3]HPRE (def=0x0) // AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AH
    • [4:6]PPRE1 (def=0x0) // APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1
    • [8:10]PPRE2 (def=0x0) // APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2
    • [12:14]DPRE (def=0x6) // DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DS
    • [16]AHB1DIS (def=0x0) // AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [17]AHB2DIS1 (def=0x0) // AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of
    • [18]AHB2DIS2 (def=0x0) // AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of
    • [19]APB1DIS (def=0x0) // APB1 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [20]APB2DIS (def=0x0) // APB2 clock disable This bit can be set in order to further reduce power consumption, when none of t
  • 0x46020C24RCC_CFGR3// RCC clock configuration register 3

    • [4:6]PPRE3 (def=0x0) // APB3 prescaler This bitfield is set and cleared by software to control the division factor of the A
    • [16]AHB3DIS (def=0x0) // AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [17]APB3DIS (def=0x0) // APB3 clock disable This bit can be set in order to further reduce power consumption, when none of t
  • 0x46020C28RCC_PLL1CFGR// RCC PLL1 configuration register

    • [0:1]PLL1SRC (def=0x0) // PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. I
    • [2:3]PLL1RGE (def=0x0) // PLL1 input frequency range This bit is set and reset by software to select the proper reference fre
    • [4]PLL1FRACEN (def=0x0) // PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRAC
    • [8:11]PLL1M (def=0x0) // Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the P
    • [12:15]PLL1MBOOST (def=0x0) // Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure th
    • [16]PLL1PEN (def=0x0) // PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck outpu
    • [17]PLL1QEN (def=0x0) // PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck outpu
    • [18]PLL1REN (def=0x0) // PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck outpu
  • 0x46020C2CRCC_PLL2CFGR// RCC PLL2 configuration register

    • [0:1]PLL2SRC (def=0x0) // PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. I
    • [2:3]PLL2RGE (def=0x0) // PLL2 input frequency range This bitfield is set and reset by software to select the proper referenc
    • [4]PLL2FRACEN (def=0x0) // PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRAC
    • [8:11]PLL2M (def=0x0) // Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the P
    • [16]PLL2PEN (def=0x0) // PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck outpu
    • [17]PLL2QEN (def=0x0) // PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck outpu
    • [18]PLL2REN (def=0x0) // PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck outpu
  • 0x46020C30RCC_PLL3CFGR// RCC PLL3 configuration register

    • [0:1]PLL3SRC (def=0x0) // PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. I
    • [2:3]PLL3RGE (def=0x0) // PLL3 input frequency range This bit is set and reset by software to select the proper reference fre
    • [4]PLL3FRACEN (def=0x0) // PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRAC
    • [8:11]PLL3M (def=0x0) // Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the P
    • [16]PLL3PEN (def=0x0) // PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck outpu
    • [17]PLL3QEN (def=0x0) // PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck outpu
    • [18]PLL3REN (def=0x0) // PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck outpu
  • 0x46020C34RCC_PLL1DIVR// RCC PLL1 dividers register

    • [0:8]PLL1N (def=0x80) // Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL1P (def=0x1) // PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL1Q (def=0x1) // PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL1R (def=0x1) // PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pl
  • 0x46020C38RCC_PLL1FRACR// RCC PLL1 fractional divider register

    • [3:15]PLL1FRACN (def=0x0) // Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by softwar
  • 0x46020C3CRCC_PLL2DIVR// RCC PLL2 dividers configuration register

    • [0:8]PLL2N (def=0x80) // Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL2P (def=0x1) // PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL2Q (def=0x1) // PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL2R (def=0x1) // PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of th
  • 0x46020C40RCC_PLL2FRACR// RCC PLL2 fractional divider register

    • [3:15]PLL2FRACN (def=0x0) // Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by softwar
  • 0x46020C44RCC_PLL3DIVR// RCC PLL3 dividers configuration register

    • [0:8]PLL3N (def=0x80) // Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL3P (def=0x1) // PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL3Q (def=0x1) // PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL3R (def=0x1) // PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of th
  • 0x46020C48RCC_PLL3FRACR// RCC PLL3 fractional divider register

    • [3:15]PLL3FRACN (def=0x0) // Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by softwar
  • 0x46020C50RCC_CIER// RCC clock interrupt enable register

    • [0]LSIRDYIE (def=0x0) // LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [1]LSERDYIE (def=0x0) // LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [2]MSISRDYIE (def=0x0) // MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [3]HSIRDYIE (def=0x0) // HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt ca
    • [4]HSERDYIE (def=0x0) // HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [5]HSI48RDYIE (def=0x0) // HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt ca
    • [6]PLL1RDYIE (def=0x0) // PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [7]PLL2RDYIE (def=0x0) // PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [8]PLL3RDYIE (def=0x0) // PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [11]MSIKRDYIE (def=0x0) // MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [12]SHSIRDYIE (def=0x0) // SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
  • 0x46020C54RCC_CIFR// RCC clock interrupt flag register

    • [0]LSIRDYF (def=0x0) // LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE
    • [1]LSERDYF (def=0x0) // LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE
    • [2]MSISRDYF (def=0x0) // MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRD
    • [3]HSIRDYF (def=0x0) // HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIR
    • [4]HSERDYF (def=0x0) // HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE
    • [5]HSI48RDYF (def=0x0) // HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI4
    • [6]PLL1RDYF (def=0x0) // PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It
    • [7]PLL2RDYF (def=0x0) // PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It
    • [8]PLL3RDYF (def=0x0) // PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It
    • [10]CSSF (def=0x0) // Clock security system interrupt flag This bit is set by hardware when a failure is detected in the
    • [11]MSIKRDYF (def=0x0) // MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRD
    • [12]SHSIRDYF (def=0x0) // SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRD
  • 0x46020C58RCC_CICR// RCC clock interrupt clear register

    • [0]LSIRDYC (def=0x0) // LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect.
    • [1]LSERDYC (def=0x0) // LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.
    • [2]MSISRDYC (def=0x0) // MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect.
    • [3]HSIRDYC (def=0x0) // HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.
    • [4]HSERDYC (def=0x0) // HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.
    • [5]HSI48RDYC (def=0x0) // HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effec
    • [6]PLL1RDYC (def=0x0) // PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.
    • [7]PLL2RDYC (def=0x0) // PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect.
    • [8]PLL3RDYC (def=0x0) // PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect.
    • [10]CSSC (def=0x0) // Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no
    • [11]MSIKRDYC (def=0x0) // MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has
    • [12]SHSIRDYC (def=0x0) // SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has
  • 0x46020C60RCC_AHB1RSTR// RCC AHB1 peripheral reset register

    • [0]GPDMA1RST (def=0x0) // GPDMA1 reset This bit is set and cleared by software.
    • [1]CORDICRST (def=0x0) // CORDIC reset This bit is set and cleared by software.
    • [2]FMACRST (def=0x0) // FMAC reset This bit is set and cleared by software.
    • [3]MDF1RST (def=0x0) // MDF1 reset This bit is set and cleared by software.
    • [12]CRCRST (def=0x0) // CRC reset This bit is set and cleared by software.
    • [15]JPEGRST (def=0x0) // JPEG reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [16]TSCRST (def=0x0) // TSC reset This bit is set and cleared by software.
    • [17]RAMCFGRST (def=0x0) // RAMCFG reset This bit is set and cleared by software.
    • [18]DMA2DRST (def=0x0) // DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devic
    • [19]GFXMMURST (def=0x0) // GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devi
    • [20]GPU2DRST (def=0x0) // GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x46020C64RCC_AHB2RSTR1// RCC AHB2 peripheral reset register 1

    • [0]GPIOARST (def=0x0) // I/O port A reset This bit is set and cleared by software.
    • [1]GPIOBRST (def=0x0) // I/O port B reset This bit is set and cleared by software.
    • [2]GPIOCRST (def=0x0) // I/O port C reset This bit is set and cleared by software.
    • [3]GPIODRST (def=0x0) // I/O port D reset This bit is set and cleared by software.
    • [4]GPIOERST (def=0x0) // I/O port E reset This bit is set and cleared by software.
    • [5]GPIOFRST (def=0x0) // I/O port F reset This bit is set and cleared by software. This bit is only available on some device
    • [6]GPIOGRST (def=0x0) // I/O port G reset This bit is set and cleared by software.
    • [7]GPIOHRST (def=0x0) // I/O port H reset This bit is set and cleared by software.
    • [8]GPIOIRST (def=0x0) // I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some
    • [9]GPIOJRST (def=0x0) // I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some
    • [10]ADC12RST (def=0x0) // ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U5
    • [12]DCMI_PSSIRST (def=0x0) // DCMI and PSSI reset This bit is set and cleared by software.
    • [14]OTGRST (def=0x0) // OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on
    • [16]AESRST (def=0x0) // AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only avai
    • [17]HASHRST (def=0x0) // HASH reset This bit is set and cleared by software.
    • [18]RNGRST (def=0x0) // RNG reset This bit is set and cleared by software.
    • [19]PKARST (def=0x0) // PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices
    • [20]SAESRST (def=0x0) // SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only ava
    • [21]OCTOSPIMRST (def=0x0) // OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some de
    • [23]OTFDEC1RST (def=0x0) // OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some dev
    • [24]OTFDEC2RST (def=0x0) // OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some dev
    • [27]SDMMC1RST (def=0x0) // SDMMC1 reset This bit is set and cleared by software.
    • [28]SDMMC2RST (def=0x0) // SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devi
  • 0x46020C68RCC_AHB2RSTR2// RCC AHB2 peripheral reset register 2

    • [0]FSMCRST (def=0x0) // Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only av
    • [4]OCTOSPI1RST (def=0x0) // OCTOSPI1 reset This bit is set and cleared by software.
    • [8]OCTOSPI2RST (def=0x0) // OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some de
    • [12]HSPI1RST (def=0x0) // HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x46020C6CRCC_AHB3RSTR// RCC AHB3 peripheral reset register

    • [0]LPGPIO1RST (def=0x0) // LPGPIO1 reset This bit is set and cleared by software.
    • [5]ADC4RST (def=0x0) // ADC4 reset This bit is set and cleared by software.
    • [6]DAC1RST (def=0x0) // DAC1 reset This bit is set and cleared by software.
    • [9]LPDMA1RST (def=0x0) // LPDMA1 reset This bit is set and cleared by software.
    • [10]ADF1RST (def=0x0) // ADF1 reset This bit is set and cleared by software.
  • 0x46020C74RCC_APB1RSTR1// RCC APB1 peripheral reset register 1

    • [0]TIM2RST (def=0x0) // TIM2 reset This bit is set and cleared by software.
    • [1]TIM3RST (def=0x0) // TIM3 reset This bit is set and cleared by software.
    • [2]TIM4RST (def=0x0) // TIM4 reset This bit is set and cleared by software.
    • [3]TIM5RST (def=0x0) // TIM5 reset This bit is set and cleared by software.
    • [4]TIM6RST (def=0x0) // TIM6 reset This bit is set and cleared by software.
    • [5]TIM7RST (def=0x0) // TIM7 reset This bit is set and cleared by software.
    • [14]SPI2RST (def=0x0) // SPI2 reset This bit is set and cleared by software.
    • [17]USART2RST (def=0x0) // USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devi
    • [18]USART3RST (def=0x0) // USART3 reset This bit is set and cleared by software.
    • [19]UART4RST (def=0x0) // UART4 reset This bit is set and cleared by software.
    • [20]UART5RST (def=0x0) // UART5 reset This bit is set and cleared by software.
    • [21]I2C1RST (def=0x0) // I2C1 reset This bit is set and cleared by software.
    • [22]I2C2RST (def=0x0) // I2C2 reset This bit is set and cleared by software.
    • [24]CRSRST (def=0x0) // CRS reset This bit is set and cleared by software.
    • [25]USART6RST (def=0x0) // USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devi
  • 0x46020C78RCC_APB1RSTR2// RCC APB1 peripheral reset register 2

    • [1]I2C4RST (def=0x0) // I2C4 reset This bit is set and cleared by software
    • [5]LPTIM2RST (def=0x0) // LPTIM2 reset This bit is set and cleared by software.
    • [6]I2C5RST (def=0x0) // I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices
    • [7]I2C6RST (def=0x0) // I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices
    • [9]FDCAN1RST (def=0x0) // FDCAN1 reset This bit is set and cleared by software.
    • [23]UCPD1RST (def=0x0) // UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x46020C7CRCC_APB2RSTR// RCC APB2 peripheral reset register

    • [11]TIM1RST (def=0x0) // TIM1 reset This bit is set and cleared by software.
    • [12]SPI1RST (def=0x0) // SPI1 reset This bit is set and cleared by software.
    • [13]TIM8RST (def=0x0) // TIM8 reset This bit is set and cleared by software.
    • [14]USART1RST (def=0x0) // USART1 reset This bit is set and cleared by software.
    • [16]TIM15RST (def=0x0) // TIM15 reset This bit is set and cleared by software.
    • [17]TIM16RST (def=0x0) // TIM16 reset This bit is set and cleared by software.
    • [18]TIM17RST (def=0x0) // TIM17 reset This bit is set and cleared by software.
    • [21]SAI1RST (def=0x0) // SAI1 reset This bit is set and cleared by software.
    • [22]SAI2RST (def=0x0) // SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [24]USBRST (def=0x0) // USB reset This bit is set and cleared by software. Note: This bit is only available on some devices
    • [25]GFXTIMRST (def=0x0) // GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some dev
    • [26]LTDCRST (def=0x0) // LTDC reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [27]DSIRST (def=0x0) // DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices
  • 0x46020C80RCC_APB3RSTR// RCC APB3 peripheral reset register

    • [1]SYSCFGRST (def=0x0) // SYSCFG reset This bit is set and cleared by software.
    • [5]SPI3RST (def=0x0) // SPI3 reset This bit is set and cleared by software.
    • [6]LPUART1RST (def=0x0) // LPUART1 reset This bit is set and cleared by software.
    • [7]I2C3RST (def=0x0) // I2C3 reset This bit is set and cleared by software.
    • [11]LPTIM1RST (def=0x0) // LPTIM1 reset This bit is set and cleared by software.
    • [12]LPTIM3RST (def=0x0) // LPTIM3 reset This bit is set and cleared by software.
    • [13]LPTIM4RST (def=0x0) // LPTIM4 reset This bit is set and cleared by software.
    • [14]OPAMPRST (def=0x0) // OPAMP reset This bit is set and cleared by software.
    • [15]COMPRST (def=0x0) // COMP reset This bit is set and cleared by software.
    • [20]VREFRST (def=0x0) // VREFBUF reset This bit is set and cleared by software.
  • 0x46020C88RCC_AHB1ENR// RCC AHB1 peripheral clock enable register

    • [0]GPDMA1EN (def=0x0) // GPDMA1 clock enable This bit is set and cleared by software.
    • [1]CORDICEN (def=0x0) // CORDIC clock enable This bit is set and cleared by software.
    • [2]FMACEN (def=0x0) // FMAC clock enable This bit is set and reset by software.
    • [3]MDF1EN (def=0x0) // MDF1 clock enable This bit is set and reset by software.
    • [8]FLASHEN (def=0x1) // FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the
    • [12]CRCEN (def=0x0) // CRC clock enable This bit is set and cleared by software.
    • [15]JPEGEN (def=0x0) // JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [16]TSCEN (def=0x0) // Touch sensing controller clock enable This bit is set and cleared by software.
    • [17]RAMCFGEN (def=0x0) // RAMCFG clock enable This bit is set and cleared by software.
    • [18]DMA2DEN (def=0x0) // DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [19]GFXMMUEN (def=0x0) // GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [20]GPU2DEN (def=0x0) // GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [21]DCACHE2EN (def=0x1) // DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to
    • [24]GTZC1EN (def=0x0) // GTZC1 clock enable This bit is set and reset by software.
    • [28]BKPSRAMEN (def=0x1) // BKPSRAM clock enable This bit is set and reset by software.
    • [30]DCACHE1EN (def=0x1) // DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled whe
    • [31]SRAM1EN (def=0x1) // SRAM1 clock enable This bit is set and reset by software.
  • 0x46020C8CRCC_AHB2ENR1// RCC AHB2 peripheral clock enable register 1

    • [0]GPIOAEN (def=0x0) // I/O port A clock enable This bit is set and cleared by software.
    • [1]GPIOBEN (def=0x0) // I/O port B clock enable This bit is set and cleared by software.
    • [2]GPIOCEN (def=0x0) // I/O port C clock enable This bit is set and cleared by software.
    • [3]GPIODEN (def=0x0) // I/O port D clock enable This bit is set and cleared by software.
    • [4]GPIOEEN (def=0x0) // I/O port E clock enable This bit is set and cleared by software.
    • [5]GPIOFEN (def=0x0) // I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [6]GPIOGEN (def=0x0) // I/O port G clock enable This bit is set and cleared by software.
    • [7]GPIOHEN (def=0x0) // I/O port H clock enable This bit is set and cleared by software.
    • [8]GPIOIEN (def=0x0) // I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [9]GPIOJEN (def=0x0) // I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [10]ADC12EN (def=0x0) // ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in
    • [12]DCMI_PSSIEN (def=0x0) // DCMI and PSSI clock enable This bit is set and cleared by software.
    • [14]OTGEN (def=0x0) // OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only avail
    • [15]OTGHSPHYEN (def=0x0) // OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [16]AESEN (def=0x0) // AES clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [17]HASHEN (def=0x0) // HASH clock enable This bit is set and cleared by software
    • [18]RNGEN (def=0x0) // RNG clock enable This bit is set and cleared by software.
    • [19]PKAEN (def=0x0) // PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [20]SAESEN (def=0x0) // SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [21]OCTOSPIMEN (def=0x0) // OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on
    • [23]OTFDEC1EN (def=0x0) // OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on s
    • [24]OTFDEC2EN (def=0x0) // OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on s
    • [27]SDMMC1EN (def=0x0) // SDMMC1 clock enable This bit is set and cleared by software.
    • [28]SDMMC2EN (def=0x0) // SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [30]SRAM2EN (def=0x1) // SRAM2 clock enable This bit is set and reset by software.
    • [31]SRAM3EN (def=0x1) // SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some
  • 0x46020C90RCC_AHB2ENR2// RCC AHB2 peripheral clock enable register 2

    • [0]FSMCEN (def=0x0) // FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [4]OCTOSPI1EN (def=0x0) // OCTOSPI1 clock enable This bit is set and cleared by software.
    • [8]OCTOSPI2EN (def=0x0) // OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on
    • [12]HSPI1EN (def=0x0) // HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [30]SRAM6EN (def=0x0) // SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some
    • [31]SRAM5EN (def=0x1) // SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some
  • 0x46020C94RCC_AHB3ENR// RCC AHB3 peripheral clock enable register

    • [0]LPGPIO1EN (def=0x0) // LPGPIO1 enable This bit is set and cleared by software.
    • [2]PWREN (def=0x0) // PWR clock enable This bit is set and cleared by software.
    • [5]ADC4EN (def=0x0) // ADC4 clock enable This bit is set and cleared by software.
    • [6]DAC1EN (def=0x0) // DAC1 clock enable This bit is set and cleared by software.
    • [9]LPDMA1EN (def=0x0) // LPDMA1 clock enable This bit is set and cleared by software.
    • [10]ADF1EN (def=0x0) // ADF1 clock enable This bit is set and cleared by software.
    • [12]GTZC2EN (def=0x0) // GTZC2 clock enable This bit is set and cleared by software.
    • [31]SRAM4EN (def=0x1) // SRAM4 clock enable This bit is set and reset by software.
  • 0x46020C9CRCC_APB1ENR1// RCC APB1 peripheral clock enable register 1

    • [0]TIM2EN (def=0x0) // TIM2 clock enable This bit is set and cleared by software.
    • [1]TIM3EN (def=0x0) // TIM3 clock enable This bit is set and cleared by software.
    • [2]TIM4EN (def=0x0) // TIM4 clock enable This bit is set and cleared by software.
    • [3]TIM5EN (def=0x0) // TIM5 clock enable This bit is set and cleared by software.
    • [4]TIM6EN (def=0x0) // TIM6 clock enable This bit is set and cleared by software.
    • [5]TIM7EN (def=0x0) // TIM7 clock enable This bit is set and cleared by software.
    • [11]WWDGEN (def=0x0) // WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by h
    • [14]SPI2EN (def=0x0) // SPI2 clock enable This bit is set and cleared by software.
    • [17]USART2EN (def=0x0) // USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [18]USART3EN (def=0x0) // USART3 clock enable This bit is set and cleared by software.
    • [19]UART4EN (def=0x0) // UART4 clock enable This bit is set and cleared by software.
    • [20]UART5EN (def=0x0) // UART5 clock enable This bit is set and cleared by software.
    • [21]I2C1EN (def=0x0) // I2C1 clock enable This bit is set and cleared by software.
    • [22]I2C2EN (def=0x0) // I2C2 clock enable This bit is set and cleared by software.
    • [24]CRSEN (def=0x0) // CRS clock enable This bit is set and cleared by software.
    • [25]USART6EN (def=0x0) // USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on so
  • 0x46020CA0RCC_APB1ENR2// RCC APB1 peripheral clock enable register 2

    • [1]I2C4EN (def=0x0) // I2C4 clock enable This bit is set and cleared by software
    • [5]LPTIM2EN (def=0x0) // LPTIM2 clock enable This bit is set and cleared by software.
    • [6]I2C5EN (def=0x0) // I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [7]I2C6EN (def=0x0) // I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [9]FDCAN1EN (def=0x0) // FDCAN1 clock enable This bit is set and cleared by software.
    • [23]UCPD1EN (def=0x0) // UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on som
  • 0x46020CA4RCC_APB2ENR// RCC APB2 peripheral clock enable register

    • [11]TIM1EN (def=0x0) // TIM1 clock enable This bit is set and cleared by software.
    • [12]SPI1EN (def=0x0) // SPI1 clock enable This bit is set and cleared by software.
    • [13]TIM8EN (def=0x0) // TIM8 clock enable This bit is set and cleared by software.
    • [14]USART1EN (def=0x0) // USART1clock enable This bit is set and cleared by software.
    • [16]TIM15EN (def=0x0) // TIM15 clock enable This bit is set and cleared by software.
    • [17]TIM16EN (def=0x0) // TIM16 clock enable This bit is set and cleared by software.
    • [18]TIM17EN (def=0x0) // TIM17 clock enable This bit is set and cleared by software.
    • [21]SAI1EN (def=0x0) // SAI1 clock enable This bit is set and cleared by software.
    • [22]SAI2EN (def=0x0) // SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [24]USBEN (def=0x0) // USB clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [25]GFXTIMEN (def=0x0) // GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [26]LTDCEN (def=0x0) // LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [27]DSIEN (def=0x0) // DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some
  • 0x46020CA8RCC_APB3ENR// RCC APB3 peripheral clock enable register

    • [1]SYSCFGEN (def=0x0) // SYSCFG clock enable This bit is set and cleared by software.
    • [5]SPI3EN (def=0x0) // SPI3 clock enable This bit is set and cleared by software.
    • [6]LPUART1EN (def=0x0) // LPUART1 clock enable This bit is set and cleared by software.
    • [7]I2C3EN (def=0x0) // I2C3 clock enable This bit is set and cleared by software.
    • [11]LPTIM1EN (def=0x0) // LPTIM1 clock enable This bit is set and cleared by software.
    • [12]LPTIM3EN (def=0x0) // LPTIM3 clock enable This bit is set and cleared by software.
    • [13]LPTIM4EN (def=0x0) // LPTIM4 clock enable This bit is set and cleared by software.
    • [14]OPAMPEN (def=0x0) // OPAMP clock enable This bit is set and cleared by software.
    • [15]COMPEN (def=0x0) // COMP clock enable This bit is set and cleared by software.
    • [20]VREFEN (def=0x0) // VREFBUF clock enable This bit is set and cleared by software.
    • [21]RTCAPBEN (def=0x0) // RTC and TAMP APB clock enable This bit is set and cleared by software.
  • 0x46020CB0RCC_AHB1SMENR// RCC AHB1 peripheral clock enable in Sleep and Stop modes register

    • [0]GPDMA1SMEN (def=0x1) // GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [1]CORDICSMEN (def=0x1) // CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sle
    • [2]FMACSMEN (def=0x1) // FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software.
    • [3]MDF1SMEN (def=0x1) // MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This
    • [8]FLASHSMEN (def=0x1) // FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [12]CRCSMEN (def=0x1) // CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [15]JPEGSMEN (def=0x1) // JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [16]TSCSMEN (def=0x1) // TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [17]RAMCFGSMEN (def=0x1) // RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [18]DMA2DSMEN (def=0x1) // DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [19]GFXMMUSMEN (def=0x1) // GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [20]GPU2DSMEN (def=0x1) // GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [21]DCACHE2SMEN (def=0x1) // DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [24]GTZC1SMEN (def=0x1) // GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [28]BKPSRAMSMEN (def=0x1) // BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software
    • [29]ICACHESMEN (def=0x1) // ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [30]DCACHE1SMEN (def=0x1) // DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM1SMEN (def=0x1) // SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x46020CB4RCC_AHB2SMENR1// RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1

    • [0]GPIOASMEN (def=0x1) // I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [1]GPIOBSMEN (def=0x1) // I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]GPIOCSMEN (def=0x1) // I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [3]GPIODSMEN (def=0x1) // I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [4]GPIOESMEN (def=0x1) // I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]GPIOFSMEN (def=0x1) // I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [6]GPIOGSMEN (def=0x1) // I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [7]GPIOHSMEN (def=0x1) // I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [8]GPIOISMEN (def=0x1) // I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [9]GPIOJSMEN (def=0x1) // I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [10]ADC12SMEN (def=0x1) // ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Not
    • [12]DCMI_PSSISMEN (def=0x1) // DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [14]OTGSMEN (def=0x1) // OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software
    • [15]OTGHSPHYSMEN (def=0x1) // OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: T
    • [16]AESSMEN (def=0x1) // AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit
    • [17]HASHSMEN (def=0x1) // HASH clock enable during Sleep and Stop modes This bit is set and cleared by software
    • [18]RNGSMEN (def=0x1) // RNG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [19]PKASMEN (def=0x1) // PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
    • [20]SAESSMEN (def=0x1) // SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]OCTOSPIMSMEN (def=0x1) // OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Th
    • [23]OTFDEC1SMEN (def=0x1) // OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [24]OTFDEC2SMEN (def=0x1) // OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [27]SDMMC1SMEN (def=0x1) // SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [28]SDMMC2SMEN (def=0x1) // SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [30]SRAM2SMEN (def=0x1) // SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM3SMEN (def=0x1) // SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x46020CB8RCC_AHB2SMENR2// RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2

    • [0]FSMCSMEN (def=0x1) // FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [4]OCTOSPI1SMEN (def=0x1) // OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [8]OCTOSPI2SMEN (def=0x1) // OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Th
    • [12]HSPI1SMEN (def=0x1) // HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [30]SRAM6SMEN (def=0x1) // SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [31]SRAM5SMEN (def=0x1) // SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x46020CBCRCC_AHB3SMENR// RCC AHB3 peripheral clock enable in Sleep and Stop modes register

    • [0]LPGPIO1SMEN (def=0x1) // LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]PWRSMEN (def=0x1) // PWR clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]ADC4SMEN (def=0x1) // ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [6]DAC1SMEN (def=0x1) // DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [9]LPDMA1SMEN (def=0x1) // LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [10]ADF1SMEN (def=0x1) // ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [12]GTZC2SMEN (def=0x1) // GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM4SMEN (def=0x1) // SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x46020CC4RCC_APB1SMENR1// RCC APB1 peripheral clock enable in Sleep and Stop modes register 1

    • [0]TIM2SMEN (def=0x1) // TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [1]TIM3SMEN (def=0x1) // TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]TIM4SMEN (def=0x1) // TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [3]TIM5SMEN (def=0x1) // TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [4]TIM6SMEN (def=0x1) // TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]TIM7SMEN (def=0x1) // TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [11]WWDGSMEN (def=0x1) // Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. I
    • [14]SPI2SMEN (def=0x1) // SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [17]USART2SMEN (def=0x1) // USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [18]USART3SMEN (def=0x1) // USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [19]UART4SMEN (def=0x1) // UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [20]UART5SMEN (def=0x1) // UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [21]I2C1SMEN (def=0x1) // I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [22]I2C2SMEN (def=0x1) // I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [24]CRSSMEN (def=0x1) // CRS clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [25]USART6SMEN (def=0x1) // USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x46020CC8RCC_APB1SMENR2// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

    • [1]I2C4SMEN (def=0x1) // I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [5]LPTIM2SMEN (def=0x1) // LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [6]I2C5SMEN (def=0x1) // I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [7]I2C6SMEN (def=0x1) // I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [9]FDCAN1SMEN (def=0x1) // FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [23]UCPD1SMEN (def=0x1) // UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x46020CCCRCC_APB2SMENR// RCC APB2 peripheral clocks enable in Sleep and Stop modes register

    • [11]TIM1SMEN (def=0x1) // TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [12]SPI1SMEN (def=0x1) // SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [13]TIM8SMEN (def=0x1) // TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [14]USART1SMEN (def=0x1) // USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [16]TIM15SMEN (def=0x1) // TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [17]TIM16SMEN (def=0x1) // TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [18]TIM17SMEN (def=0x1) // TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]SAI1SMEN (def=0x1) // SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [22]SAI2SMEN (def=0x1) // SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [24]USBSMEN (def=0x1) // USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
    • [25]GFXTIMSMEN (def=0x1) // GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [26]LTDCSMEN (def=0x1) // LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [27]DSISMEN (def=0x1) // DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
  • 0x46020CD0RCC_APB3SMENR// RCC APB3 peripheral clock enable in Sleep and Stop modes register

    • [1]SYSCFGSMEN (def=0x1) // SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]SPI3SMEN (def=0x1) // SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [6]LPUART1SMEN (def=0x1) // LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [7]I2C3SMEN (def=0x1) // I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [11]LPTIM1SMEN (def=0x1) // LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [12]LPTIM3SMEN (def=0x1) // LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [13]LPTIM4SMEN (def=0x1) // LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [14]OPAMPSMEN (def=0x1) // OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [15]COMPSMEN (def=0x1) // COMP clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [20]VREFSMEN (def=0x1) // VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]RTCAPBSMEN (def=0x1) // RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x46020CD8RCC_SRDAMR// RCC SmartRun domain peripheral autonomous mode register

    • [5]SPI3AMEN (def=0x0) // SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This
    • [6]LPUART1AMEN (def=0x0) // LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Th
    • [7]I2C3AMEN (def=0x0) // I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [11]LPTIM1AMEN (def=0x0) // LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [12]LPTIM3AMEN (def=0x0) // LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [13]LPTIM4AMEN (def=0x0) // LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [14]OPAMPAMEN (def=0x0) // OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [15]COMPAMEN (def=0x0) // COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [20]VREFAMEN (def=0x0) // VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [21]RTCAPBAMEN (def=0x0) // RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Not
    • [25]ADC4AMEN (def=0x0) // ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [26]LPGPIO1AMEN (def=0x0) // LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [27]DAC1AMEN (def=0x0) // DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [28]LPDMA1AMEN (def=0x0) // LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [29]ADF1AMEN (def=0x0) // ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [31]SRAM4AMEN (def=0x0) // SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
  • 0x46020CE0RCC_CCIPR1// RCC peripherals independent clock configuration register 1

    • [0:1]USART1SEL (def=0x0) // USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source.
    • [2:3]USART2SEL (def=0x0) // USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source.
    • [4:5]USART3SEL (def=0x0) // USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source.
    • [6:7]UART4SEL (def=0x0) // UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. No
    • [8:9]UART5SEL (def=0x0) // UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. No
    • [10:11]I2C1SEL (def=0x0) // I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note
    • [12:13]I2C2SEL (def=0x0) // I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note
    • [14:15]I2C4SEL (def=0x0) // I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note
    • [16:17]SPI2SEL (def=0x0) // SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note
    • [18:19]LPTIM2SEL (def=0x0) // Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clo
    • [20:21]SPI1SEL (def=0x0) // SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note
    • [22:23]SYSTICKSEL (def=0x0) // SysTick clock source selection These bits are used to select the SysTick clock source. Note: When L
    • [24:25]FDCAN1SEL (def=0x0) // FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source.
    • [26:27]ICLKSEL (def=0x0) // Intermediate clock source selection These bits are used to select the clock source for the OTG_FS,
    • [29:31]TIMICSEL (def=0x0) // Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16,
  • 0x46020CE4RCC_CCIPR2// RCC peripherals independent clock configuration register 2

    • [0:2]MDF1SEL (def=0x0) // MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. othe
    • [5:7]SAI1SEL (def=0x0) // SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. othe
    • [8:10]SAI2SEL (def=0x0) // SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. othe
    • [11]SAESSEL (def=0x0) // SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: T
    • [12:13]RNGSEL (def=0x0) // RNG kernel clock source selection These bits are used to select the RNG kernel clock source.
    • [14]SDMMCSEL (def=0x0) // SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock s
    • [15]DSISEL (def=0x0) // DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit
    • [16:17]USART6SEL (def=0x0) // USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source.
    • [18]LTDCSEL (def=0x0) // LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: T
    • [20:21]OCTOSPISEL (def=0x0) // OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and
    • [22:23]HSPI1SEL (def=0x0) // HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. No
    • [24:25]I2C5SEL (def=0x0) // I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The
    • [26:27]I2C6SEL (def=0x0) // I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The
    • [30:31]OTGHSSEL (def=0x0) // OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock
  • 0x46020CE8RCC_CCIPR3// RCC peripherals independent clock configuration register 3

    • [0:2]LPUART1SEL (def=0x0) // LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source
    • [3:4]SPI3SEL (def=0x0) // SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note
    • [6:7]I2C3SEL (def=0x0) // I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note
    • [8:9]LPTIM34SEL (def=0x0) // LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4
    • [10:11]LPTIM1SEL (def=0x0) // LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source.
    • [12:14]ADCDACSEL (def=0x0) // ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC
    • [15]DAC1SEL (def=0x0) // DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clo
    • [16:18]ADF1SEL (def=0x0) // ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. othe
  • 0x46020CF0RCC_BDCR// RCC backup domain control register

    • [0]LSEON (def=0x0) // LSE oscillator enable This bit is set and cleared by software.
    • [1]LSERDY (def=0x0) // LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz
    • [2]LSEBYP (def=0x0) // LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. I
    • [3:4]LSEDRV (def=0x0) // LSE oscillator drive capability This bitfield is set by software to modulate the drive capability o
    • [5]LSECSSON (def=0x0) // CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after th
    • [6]LSECSSD (def=0x0) // CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by
    • [7]LSESYSEN (def=0x0) // LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock
    • [8:9]RTCSEL (def=0x0) // RTC and TAMP clock source selection This bit is set by software to select the clock source for the
    • [11]LSESYSRDY (def=0x0) // LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE sy
    • [12]LSEGFON (def=0x0) // LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch fil
    • [15]RTCEN (def=0x0) // RTC and TAMP clock enable This bit is set and cleared by software.
    • [16]BDRST (def=0x0) // Backup domain software reset This bit is set and cleared by software.
    • [24]LSCOEN (def=0x0) // Low-speed clock output (LSCO) enable This bit is set and cleared by software.
    • [25]LSCOSEL (def=0x0) // Low-speed clock output selection This bit is set and cleared by software.
    • [26]LSION (def=0x0) // LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60�
    • [27]LSIRDY (def=0x0) // LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is
    • [28]LSIPREDIV (def=0x0) // Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI div
  • 0x46020CF4RCC_CSR// RCC control/status register

    • [8:11]MSIKSRANGE (def=0x4) // MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. I
    • [12:15]MSISSRANGE (def=0x4) // MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at start
    • [23]RMVF (def=0x0) // Remove reset flag This bit is set by software to clear the reset flags.
    • [25]OBLRSTF (def=0x0) // Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading
    • [26]PINRSTF (def=0x1) // NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleare
    • [27]BORRSTF (def=0x1) // Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout
    • [28]SFTRSTF (def=0x0) // Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writ
    • [29]IWDGRSTF (def=0x0) // Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset doma
    • [30]WWDGRSTF (def=0x0) // Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is c
    • [31]LPWRRSTF (def=0x0) // Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shu
  • 0x46020D10RCC_SECCFGR// RCC secure configuration register

    • [0]HSISEC (def=0x0) // HSI clock configuration and status bit security This bit is set and reset by software.
    • [1]HSESEC (def=0x0) // HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software
    • [2]MSISEC (def=0x0) // MSI clock configuration and status bit security This bit is set and reset by software.
    • [3]LSISEC (def=0x0) // LSI clock configuration and status bit security This bit is set and reset by software.
    • [4]LSESEC (def=0x0) // LSE clock configuration and status bit security This bit is set and reset by software.
    • [5]SYSCLKSEC (def=0x0) // SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set an
    • [6]PRESCSEC (def=0x0) // AHBx/APBx prescaler configuration bits security This bit is set and reset by software.
    • [7]PLL1SEC (def=0x0) // PLL1 clock configuration and status bit security This bit is set and reset by software.
    • [8]PLL2SEC (def=0x0) // PLL2 clock configuration and status bit security Set and reset by software.
    • [9]PLL3SEC (def=0x0) // PLL3 clock configuration and status bit security This bit is set and reset by software.
    • [10]ICLKSEC (def=0x0) // Intermediate clock source selection security This bit is set and reset by software.
    • [11]HSI48SEC (def=0x0) // HSI48 clock configuration and status bit security This bit is set and reset by software.
    • [12]RMVFSEC (def=0x0) // Remove reset flag security This bit is set and reset by software.
  • 0x46020D14RCC_PRIVCFGR// RCC privilege configuration register

    • [0]SPRIV (def=0x0) // RCC secure function privilege configuration This bit is set and reset by software. It can be writte
    • [1]NSPRIV (def=0x0) // RCC non-secure function privilege configuration This bit is set and reset by software. It can be wr
  interrupts:
  • [0] RCC // RCC non-secure global interrupt
  • [8] RCC_S // RCC secure global interrupt
• 0x56020C00SEC_RCC//

  • 0x56020C00RCC_CR// RCC clock control register

    • [0]MSISON (def=0x1) // MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MS
    • [1]MSIKERON (def=0x0) // MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even
    • [2]MSISRDY (def=0x1) // MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. I
    • [3]MSIPLLEN (def=0x0) // MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of
    • [4]MSIKON (def=0x1) // MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MS
    • [5]MSIKRDY (def=0x1) // MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set on
    • [6]MSIPLLSEL (def=0x0) // MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI outpu
    • [7]MSIPLLFAST (def=0x0) // MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode
    • [8]HSION (def=0x0) // HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the H
    • [9]HSIKERON (def=0x0) // HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON
    • [10]HSIRDY (def=0x0) // HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It
    • [12]HSI48ON (def=0x0) // HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the H
    • [13]HSI48RDY (def=0x0) // HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Iti
    • [14]SHSION (def=0x0) // SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SH
    • [15]SHSIRDY (def=0x0) // SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. I
    • [16]HSEON (def=0x0) // HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE
    • [17]HSERDY (def=0x0) // HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Not
    • [18]HSEBYP (def=0x0) // HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with
    • [19]CSSON (def=0x0) // Clock security system enable This bit is set by software to enable the clock security system. When
    • [20]HSEEXT (def=0x0) // HSE external clock bypass mode This bit is set and reset by software to select the external clock m
    • [24]PLL1ON (def=0x0) // PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardwa
    • [25]PLL1RDY (def=0x0) // PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked.
    • [26]PLL2ON (def=0x0) // PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when
    • [27]PLL2RDY (def=0x0) // PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked.
    • [28]PLL3ON (def=0x0) // PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when
    • [29]PLL3RDY (def=0x0) // PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked.
  • 0x56020C08RCC_ICSCR1// RCC internal clock sources calibration register 1

    • [0:4]MSICAL3 (def=0x0) // MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the fac
    • [5:9]MSICAL2 (def=0x0) // MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the fact
    • [10:14]MSICAL1 (def=0x0) // MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the facto
    • [15:19]MSICAL0 (def=0x0) // MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the facto
    • [22]MSIBIAS (def=0x0) // MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MS
    • [23]MSIRGSEL (def=0x0) // MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with
    • [24:27]MSIKRANGE (def=0x4) // MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscil
    • [28:31]MSISRANGE (def=0x4) // MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscil
  • 0x56020C0CRCC_ICSCR2// RCC internal clock sources calibration register 2

    • [0:4]MSITRIM3 (def=0x10) // MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming
    • [5:9]MSITRIM2 (def=0x10) // MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming v
    • [10:14]MSITRIM1 (def=0x10) // MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming va
    • [15:19]MSITRIM0 (def=0x10) // MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming va
  • 0x56020C10RCC_ICSCR3// RCC internal clock sources calibration register 3

    • [0:11]HSICAL (def=0x0) // HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibra
    • [16:20]HSITRIM (def=0x10) // HSI clock trimming These bits provide an additional user-programmable trimming value that is added
  • 0x56020C14RCC_CRRCR// RCC clock recovery RC register

    • [0:8]HSI48CAL (def=0x0) // HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 cal
  • 0x56020C1CRCC_CFGR1// RCC clock configuration register 1

    • [0:1]SW (def=0x0) // system clock switch This bitfield is set and cleared by software to select system clock source (SYS
    • [2:3]SWS (def=0x0) // system clock switch status This bitfield is set and cleared by hardware to indicate which clock sou
    • [4]STOPWUCK (def=0x0) // wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select
    • [5]STOPKERWUCK (def=0x0) // wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software t
    • [24:27]MCOSEL (def=0x0) // microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: T
    • [28:30]MCOPRE (def=0x0) // microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly r
  • 0x56020C20RCC_CFGR2// RCC clock configuration register 2

    • [0:3]HPRE (def=0x0) // AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AH
    • [4:6]PPRE1 (def=0x0) // APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1
    • [8:10]PPRE2 (def=0x0) // APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2
    • [12:14]DPRE (def=0x6) // DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DS
    • [16]AHB1DIS (def=0x0) // AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [17]AHB2DIS1 (def=0x0) // AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of
    • [18]AHB2DIS2 (def=0x0) // AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of
    • [19]APB1DIS (def=0x0) // APB1 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [20]APB2DIS (def=0x0) // APB2 clock disable This bit can be set in order to further reduce power consumption, when none of t
  • 0x56020C24RCC_CFGR3// RCC clock configuration register 3

    • [4:6]PPRE3 (def=0x0) // APB3 prescaler This bitfield is set and cleared by software to control the division factor of the A
    • [16]AHB3DIS (def=0x0) // AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of t
    • [17]APB3DIS (def=0x0) // APB3 clock disable This bit can be set in order to further reduce power consumption, when none of t
  • 0x56020C28RCC_PLL1CFGR// RCC PLL1 configuration register

    • [0:1]PLL1SRC (def=0x0) // PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. I
    • [2:3]PLL1RGE (def=0x0) // PLL1 input frequency range This bit is set and reset by software to select the proper reference fre
    • [4]PLL1FRACEN (def=0x0) // PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRAC
    • [8:11]PLL1M (def=0x0) // Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the P
    • [12:15]PLL1MBOOST (def=0x0) // Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure th
    • [16]PLL1PEN (def=0x0) // PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck outpu
    • [17]PLL1QEN (def=0x0) // PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck outpu
    • [18]PLL1REN (def=0x0) // PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck outpu
  • 0x56020C2CRCC_PLL2CFGR// RCC PLL2 configuration register

    • [0:1]PLL2SRC (def=0x0) // PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. I
    • [2:3]PLL2RGE (def=0x0) // PLL2 input frequency range This bitfield is set and reset by software to select the proper referenc
    • [4]PLL2FRACEN (def=0x0) // PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRAC
    • [8:11]PLL2M (def=0x0) // Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the P
    • [16]PLL2PEN (def=0x0) // PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck outpu
    • [17]PLL2QEN (def=0x0) // PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck outpu
    • [18]PLL2REN (def=0x0) // PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck outpu
  • 0x56020C30RCC_PLL3CFGR// RCC PLL3 configuration register

    • [0:1]PLL3SRC (def=0x0) // PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. I
    • [2:3]PLL3RGE (def=0x0) // PLL3 input frequency range This bit is set and reset by software to select the proper reference fre
    • [4]PLL3FRACEN (def=0x0) // PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRAC
    • [8:11]PLL3M (def=0x0) // Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the P
    • [16]PLL3PEN (def=0x0) // PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck outpu
    • [17]PLL3QEN (def=0x0) // PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck outpu
    • [18]PLL3REN (def=0x0) // PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck outpu
  • 0x56020C34RCC_PLL1DIVR// RCC PLL1 dividers register

    • [0:8]PLL1N (def=0x80) // Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL1P (def=0x1) // PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL1Q (def=0x1) // PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL1R (def=0x1) // PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pl
  • 0x56020C38RCC_PLL1FRACR// RCC PLL1 fractional divider register

    • [3:15]PLL1FRACN (def=0x0) // Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by softwar
  • 0x56020C3CRCC_PLL2DIVR// RCC PLL2 dividers configuration register

    • [0:8]PLL2N (def=0x80) // Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL2P (def=0x1) // PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL2Q (def=0x1) // PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL2R (def=0x1) // PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of th
  • 0x56020C40RCC_PLL2FRACR// RCC PLL2 fractional divider register

    • [3:15]PLL2FRACN (def=0x0) // Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by softwar
  • 0x56020C44RCC_PLL3DIVR// RCC PLL3 dividers configuration register

    • [0:8]PLL3N (def=0x80) // Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multip
    • [9:15]PLL3P (def=0x1) // PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of th
    • [16:22]PLL3Q (def=0x1) // PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of th
    • [24:30]PLL3R (def=0x1) // PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of th
  • 0x56020C48RCC_PLL3FRACR// RCC PLL3 fractional divider register

    • [3:15]PLL3FRACN (def=0x0) // Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by softwar
  • 0x56020C50RCC_CIER// RCC clock interrupt enable register

    • [0]LSIRDYIE (def=0x0) // LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [1]LSERDYIE (def=0x0) // LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [2]MSISRDYIE (def=0x0) // MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [3]HSIRDYIE (def=0x0) // HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt ca
    • [4]HSERDYIE (def=0x0) // HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [5]HSI48RDYIE (def=0x0) // HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt ca
    • [6]PLL1RDYIE (def=0x0) // PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caus
    • [7]PLL2RDYIE (def=0x0) // PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [8]PLL3RDYIE (def=0x0) // PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [11]MSIKRDYIE (def=0x0) // MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
    • [12]SHSIRDYIE (def=0x0) // SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt cau
  • 0x56020C54RCC_CIFR// RCC clock interrupt flag register

    • [0]LSIRDYF (def=0x0) // LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE
    • [1]LSERDYF (def=0x0) // LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE
    • [2]MSISRDYF (def=0x0) // MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRD
    • [3]HSIRDYF (def=0x0) // HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIR
    • [4]HSERDYF (def=0x0) // HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE
    • [5]HSI48RDYF (def=0x0) // HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI4
    • [6]PLL1RDYF (def=0x0) // PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It
    • [7]PLL2RDYF (def=0x0) // PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It
    • [8]PLL3RDYF (def=0x0) // PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It
    • [10]CSSF (def=0x0) // Clock security system interrupt flag This bit is set by hardware when a failure is detected in the
    • [11]MSIKRDYF (def=0x0) // MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRD
    • [12]SHSIRDYF (def=0x0) // SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRD
  • 0x56020C58RCC_CICR// RCC clock interrupt clear register

    • [0]LSIRDYC (def=0x0) // LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect.
    • [1]LSERDYC (def=0x0) // LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.
    • [2]MSISRDYC (def=0x0) // MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect.
    • [3]HSIRDYC (def=0x0) // HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.
    • [4]HSERDYC (def=0x0) // HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.
    • [5]HSI48RDYC (def=0x0) // HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effec
    • [6]PLL1RDYC (def=0x0) // PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.
    • [7]PLL2RDYC (def=0x0) // PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect.
    • [8]PLL3RDYC (def=0x0) // PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect.
    • [10]CSSC (def=0x0) // Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no
    • [11]MSIKRDYC (def=0x0) // MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has
    • [12]SHSIRDYC (def=0x0) // SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has
  • 0x56020C60RCC_AHB1RSTR// RCC AHB1 peripheral reset register

    • [0]GPDMA1RST (def=0x0) // GPDMA1 reset This bit is set and cleared by software.
    • [1]CORDICRST (def=0x0) // CORDIC reset This bit is set and cleared by software.
    • [2]FMACRST (def=0x0) // FMAC reset This bit is set and cleared by software.
    • [3]MDF1RST (def=0x0) // MDF1 reset This bit is set and cleared by software.
    • [12]CRCRST (def=0x0) // CRC reset This bit is set and cleared by software.
    • [15]JPEGRST (def=0x0) // JPEG reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [16]TSCRST (def=0x0) // TSC reset This bit is set and cleared by software.
    • [17]RAMCFGRST (def=0x0) // RAMCFG reset This bit is set and cleared by software.
    • [18]DMA2DRST (def=0x0) // DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devic
    • [19]GFXMMURST (def=0x0) // GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devi
    • [20]GPU2DRST (def=0x0) // GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x56020C64RCC_AHB2RSTR1// RCC AHB2 peripheral reset register 1

    • [0]GPIOARST (def=0x0) // I/O port A reset This bit is set and cleared by software.
    • [1]GPIOBRST (def=0x0) // I/O port B reset This bit is set and cleared by software.
    • [2]GPIOCRST (def=0x0) // I/O port C reset This bit is set and cleared by software.
    • [3]GPIODRST (def=0x0) // I/O port D reset This bit is set and cleared by software.
    • [4]GPIOERST (def=0x0) // I/O port E reset This bit is set and cleared by software.
    • [5]GPIOFRST (def=0x0) // I/O port F reset This bit is set and cleared by software. This bit is only available on some device
    • [6]GPIOGRST (def=0x0) // I/O port G reset This bit is set and cleared by software.
    • [7]GPIOHRST (def=0x0) // I/O port H reset This bit is set and cleared by software.
    • [8]GPIOIRST (def=0x0) // I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some
    • [9]GPIOJRST (def=0x0) // I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some
    • [10]ADC12RST (def=0x0) // ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U5
    • [12]DCMI_PSSIRST (def=0x0) // DCMI and PSSI reset This bit is set and cleared by software.
    • [14]OTGRST (def=0x0) // OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on
    • [16]AESRST (def=0x0) // AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only avai
    • [17]HASHRST (def=0x0) // HASH reset This bit is set and cleared by software.
    • [18]RNGRST (def=0x0) // RNG reset This bit is set and cleared by software.
    • [19]PKARST (def=0x0) // PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices
    • [20]SAESRST (def=0x0) // SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only ava
    • [21]OCTOSPIMRST (def=0x0) // OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some de
    • [23]OTFDEC1RST (def=0x0) // OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some dev
    • [24]OTFDEC2RST (def=0x0) // OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some dev
    • [27]SDMMC1RST (def=0x0) // SDMMC1 reset This bit is set and cleared by software.
    • [28]SDMMC2RST (def=0x0) // SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devi
  • 0x56020C68RCC_AHB2RSTR2// RCC AHB2 peripheral reset register 2

    • [0]FSMCRST (def=0x0) // Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only av
    • [4]OCTOSPI1RST (def=0x0) // OCTOSPI1 reset This bit is set and cleared by software.
    • [8]OCTOSPI2RST (def=0x0) // OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some de
    • [12]HSPI1RST (def=0x0) // HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x56020C6CRCC_AHB3RSTR// RCC AHB3 peripheral reset register

    • [0]LPGPIO1RST (def=0x0) // LPGPIO1 reset This bit is set and cleared by software.
    • [5]ADC4RST (def=0x0) // ADC4 reset This bit is set and cleared by software.
    • [6]DAC1RST (def=0x0) // DAC1 reset This bit is set and cleared by software.
    • [9]LPDMA1RST (def=0x0) // LPDMA1 reset This bit is set and cleared by software.
    • [10]ADF1RST (def=0x0) // ADF1 reset This bit is set and cleared by software.
  • 0x56020C74RCC_APB1RSTR1// RCC APB1 peripheral reset register 1

    • [0]TIM2RST (def=0x0) // TIM2 reset This bit is set and cleared by software.
    • [1]TIM3RST (def=0x0) // TIM3 reset This bit is set and cleared by software.
    • [2]TIM4RST (def=0x0) // TIM4 reset This bit is set and cleared by software.
    • [3]TIM5RST (def=0x0) // TIM5 reset This bit is set and cleared by software.
    • [4]TIM6RST (def=0x0) // TIM6 reset This bit is set and cleared by software.
    • [5]TIM7RST (def=0x0) // TIM7 reset This bit is set and cleared by software.
    • [14]SPI2RST (def=0x0) // SPI2 reset This bit is set and cleared by software.
    • [17]USART2RST (def=0x0) // USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devi
    • [18]USART3RST (def=0x0) // USART3 reset This bit is set and cleared by software.
    • [19]UART4RST (def=0x0) // UART4 reset This bit is set and cleared by software.
    • [20]UART5RST (def=0x0) // UART5 reset This bit is set and cleared by software.
    • [21]I2C1RST (def=0x0) // I2C1 reset This bit is set and cleared by software.
    • [22]I2C2RST (def=0x0) // I2C2 reset This bit is set and cleared by software.
    • [24]CRSRST (def=0x0) // CRS reset This bit is set and cleared by software.
    • [25]USART6RST (def=0x0) // USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devi
  • 0x56020C78RCC_APB1RSTR2// RCC APB1 peripheral reset register 2

    • [1]I2C4RST (def=0x0) // I2C4 reset This bit is set and cleared by software
    • [5]LPTIM2RST (def=0x0) // LPTIM2 reset This bit is set and cleared by software.
    • [6]I2C5RST (def=0x0) // I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices
    • [7]I2C6RST (def=0x0) // I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices
    • [9]FDCAN1RST (def=0x0) // FDCAN1 reset This bit is set and cleared by software.
    • [23]UCPD1RST (def=0x0) // UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devic
  • 0x56020C7CRCC_APB2RSTR// RCC APB2 peripheral reset register

    • [11]TIM1RST (def=0x0) // TIM1 reset This bit is set and cleared by software.
    • [12]SPI1RST (def=0x0) // SPI1 reset This bit is set and cleared by software.
    • [13]TIM8RST (def=0x0) // TIM8 reset This bit is set and cleared by software.
    • [14]USART1RST (def=0x0) // USART1 reset This bit is set and cleared by software.
    • [16]TIM15RST (def=0x0) // TIM15 reset This bit is set and cleared by software.
    • [17]TIM16RST (def=0x0) // TIM16 reset This bit is set and cleared by software.
    • [18]TIM17RST (def=0x0) // TIM17 reset This bit is set and cleared by software.
    • [21]SAI1RST (def=0x0) // SAI1 reset This bit is set and cleared by software.
    • [22]SAI2RST (def=0x0) // SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [24]USBRST (def=0x0) // USB reset This bit is set and cleared by software. Note: This bit is only available on some devices
    • [25]GFXTIMRST (def=0x0) // GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some dev
    • [26]LTDCRST (def=0x0) // LTDC reset This bit is set and cleared by software. Note: This bit is only available on some device
    • [27]DSIRST (def=0x0) // DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices
  • 0x56020C80RCC_APB3RSTR// RCC APB3 peripheral reset register

    • [1]SYSCFGRST (def=0x0) // SYSCFG reset This bit is set and cleared by software.
    • [5]SPI3RST (def=0x0) // SPI3 reset This bit is set and cleared by software.
    • [6]LPUART1RST (def=0x0) // LPUART1 reset This bit is set and cleared by software.
    • [7]I2C3RST (def=0x0) // I2C3 reset This bit is set and cleared by software.
    • [11]LPTIM1RST (def=0x0) // LPTIM1 reset This bit is set and cleared by software.
    • [12]LPTIM3RST (def=0x0) // LPTIM3 reset This bit is set and cleared by software.
    • [13]LPTIM4RST (def=0x0) // LPTIM4 reset This bit is set and cleared by software.
    • [14]OPAMPRST (def=0x0) // OPAMP reset This bit is set and cleared by software.
    • [15]COMPRST (def=0x0) // COMP reset This bit is set and cleared by software.
    • [20]VREFRST (def=0x0) // VREFBUF reset This bit is set and cleared by software.
  • 0x56020C88RCC_AHB1ENR// RCC AHB1 peripheral clock enable register

    • [0]GPDMA1EN (def=0x0) // GPDMA1 clock enable This bit is set and cleared by software.
    • [1]CORDICEN (def=0x0) // CORDIC clock enable This bit is set and cleared by software.
    • [2]FMACEN (def=0x0) // FMAC clock enable This bit is set and reset by software.
    • [3]MDF1EN (def=0x0) // MDF1 clock enable This bit is set and reset by software.
    • [8]FLASHEN (def=0x1) // FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the
    • [12]CRCEN (def=0x0) // CRC clock enable This bit is set and cleared by software.
    • [15]JPEGEN (def=0x0) // JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [16]TSCEN (def=0x0) // Touch sensing controller clock enable This bit is set and cleared by software.
    • [17]RAMCFGEN (def=0x0) // RAMCFG clock enable This bit is set and cleared by software.
    • [18]DMA2DEN (def=0x0) // DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [19]GFXMMUEN (def=0x0) // GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [20]GPU2DEN (def=0x0) // GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [21]DCACHE2EN (def=0x1) // DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to
    • [24]GTZC1EN (def=0x0) // GTZC1 clock enable This bit is set and reset by software.
    • [28]BKPSRAMEN (def=0x1) // BKPSRAM clock enable This bit is set and reset by software.
    • [30]DCACHE1EN (def=0x1) // DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled whe
    • [31]SRAM1EN (def=0x1) // SRAM1 clock enable This bit is set and reset by software.
  • 0x56020C8CRCC_AHB2ENR1// RCC AHB2 peripheral clock enable register 1

    • [0]GPIOAEN (def=0x0) // I/O port A clock enable This bit is set and cleared by software.
    • [1]GPIOBEN (def=0x0) // I/O port B clock enable This bit is set and cleared by software.
    • [2]GPIOCEN (def=0x0) // I/O port C clock enable This bit is set and cleared by software.
    • [3]GPIODEN (def=0x0) // I/O port D clock enable This bit is set and cleared by software.
    • [4]GPIOEEN (def=0x0) // I/O port E clock enable This bit is set and cleared by software.
    • [5]GPIOFEN (def=0x0) // I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [6]GPIOGEN (def=0x0) // I/O port G clock enable This bit is set and cleared by software.
    • [7]GPIOHEN (def=0x0) // I/O port H clock enable This bit is set and cleared by software.
    • [8]GPIOIEN (def=0x0) // I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [9]GPIOJEN (def=0x0) // I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [10]ADC12EN (def=0x0) // ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in
    • [12]DCMI_PSSIEN (def=0x0) // DCMI and PSSI clock enable This bit is set and cleared by software.
    • [14]OTGEN (def=0x0) // OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only avail
    • [15]OTGHSPHYEN (def=0x0) // OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available o
    • [16]AESEN (def=0x0) // AES clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [17]HASHEN (def=0x0) // HASH clock enable This bit is set and cleared by software
    • [18]RNGEN (def=0x0) // RNG clock enable This bit is set and cleared by software.
    • [19]PKAEN (def=0x0) // PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [20]SAESEN (def=0x0) // SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [21]OCTOSPIMEN (def=0x0) // OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on
    • [23]OTFDEC1EN (def=0x0) // OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on s
    • [24]OTFDEC2EN (def=0x0) // OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on s
    • [27]SDMMC1EN (def=0x0) // SDMMC1 clock enable This bit is set and cleared by software.
    • [28]SDMMC2EN (def=0x0) // SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [30]SRAM2EN (def=0x1) // SRAM2 clock enable This bit is set and reset by software.
    • [31]SRAM3EN (def=0x1) // SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some
  • 0x56020C90RCC_AHB2ENR2// RCC AHB2 peripheral clock enable register 2

    • [0]FSMCEN (def=0x0) // FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [4]OCTOSPI1EN (def=0x0) // OCTOSPI1 clock enable This bit is set and cleared by software.
    • [8]OCTOSPI2EN (def=0x0) // OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on
    • [12]HSPI1EN (def=0x0) // HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on som
    • [30]SRAM6EN (def=0x0) // SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some
    • [31]SRAM5EN (def=0x1) // SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some
  • 0x56020C94RCC_AHB3ENR// RCC AHB3 peripheral clock enable register

    • [0]LPGPIO1EN (def=0x0) // LPGPIO1 enable This bit is set and cleared by software.
    • [2]PWREN (def=0x0) // PWR clock enable This bit is set and cleared by software.
    • [5]ADC4EN (def=0x0) // ADC4 clock enable This bit is set and cleared by software.
    • [6]DAC1EN (def=0x0) // DAC1 clock enable This bit is set and cleared by software.
    • [9]LPDMA1EN (def=0x0) // LPDMA1 clock enable This bit is set and cleared by software.
    • [10]ADF1EN (def=0x0) // ADF1 clock enable This bit is set and cleared by software.
    • [12]GTZC2EN (def=0x0) // GTZC2 clock enable This bit is set and cleared by software.
    • [31]SRAM4EN (def=0x1) // SRAM4 clock enable This bit is set and reset by software.
  • 0x56020C9CRCC_APB1ENR1// RCC APB1 peripheral clock enable register 1

    • [0]TIM2EN (def=0x0) // TIM2 clock enable This bit is set and cleared by software.
    • [1]TIM3EN (def=0x0) // TIM3 clock enable This bit is set and cleared by software.
    • [2]TIM4EN (def=0x0) // TIM4 clock enable This bit is set and cleared by software.
    • [3]TIM5EN (def=0x0) // TIM5 clock enable This bit is set and cleared by software.
    • [4]TIM6EN (def=0x0) // TIM6 clock enable This bit is set and cleared by software.
    • [5]TIM7EN (def=0x0) // TIM7 clock enable This bit is set and cleared by software.
    • [11]WWDGEN (def=0x0) // WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by h
    • [14]SPI2EN (def=0x0) // SPI2 clock enable This bit is set and cleared by software.
    • [17]USART2EN (def=0x0) // USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [18]USART3EN (def=0x0) // USART3 clock enable This bit is set and cleared by software.
    • [19]UART4EN (def=0x0) // UART4 clock enable This bit is set and cleared by software.
    • [20]UART5EN (def=0x0) // UART5 clock enable This bit is set and cleared by software.
    • [21]I2C1EN (def=0x0) // I2C1 clock enable This bit is set and cleared by software.
    • [22]I2C2EN (def=0x0) // I2C2 clock enable This bit is set and cleared by software.
    • [24]CRSEN (def=0x0) // CRS clock enable This bit is set and cleared by software.
    • [25]USART6EN (def=0x0) // USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on so
  • 0x56020CA0RCC_APB1ENR2// RCC APB1 peripheral clock enable register 2

    • [1]I2C4EN (def=0x0) // I2C4 clock enable This bit is set and cleared by software
    • [5]LPTIM2EN (def=0x0) // LPTIM2 clock enable This bit is set and cleared by software.
    • [6]I2C5EN (def=0x0) // I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [7]I2C6EN (def=0x0) // I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [9]FDCAN1EN (def=0x0) // FDCAN1 clock enable This bit is set and cleared by software.
    • [23]UCPD1EN (def=0x0) // UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on som
  • 0x56020CA4RCC_APB2ENR// RCC APB2 peripheral clock enable register

    • [11]TIM1EN (def=0x0) // TIM1 clock enable This bit is set and cleared by software.
    • [12]SPI1EN (def=0x0) // SPI1 clock enable This bit is set and cleared by software.
    • [13]TIM8EN (def=0x0) // TIM8 clock enable This bit is set and cleared by software.
    • [14]USART1EN (def=0x0) // USART1clock enable This bit is set and cleared by software.
    • [16]TIM15EN (def=0x0) // TIM15 clock enable This bit is set and cleared by software.
    • [17]TIM16EN (def=0x0) // TIM16 clock enable This bit is set and cleared by software.
    • [18]TIM17EN (def=0x0) // TIM17 clock enable This bit is set and cleared by software.
    • [21]SAI1EN (def=0x0) // SAI1 clock enable This bit is set and cleared by software.
    • [22]SAI2EN (def=0x0) // SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [24]USBEN (def=0x0) // USB clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [25]GFXTIMEN (def=0x0) // GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on so
    • [26]LTDCEN (def=0x0) // LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some
    • [27]DSIEN (def=0x0) // DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some
  • 0x56020CA8RCC_APB3ENR// RCC APB3 peripheral clock enable register

    • [1]SYSCFGEN (def=0x0) // SYSCFG clock enable This bit is set and cleared by software.
    • [5]SPI3EN (def=0x0) // SPI3 clock enable This bit is set and cleared by software.
    • [6]LPUART1EN (def=0x0) // LPUART1 clock enable This bit is set and cleared by software.
    • [7]I2C3EN (def=0x0) // I2C3 clock enable This bit is set and cleared by software.
    • [11]LPTIM1EN (def=0x0) // LPTIM1 clock enable This bit is set and cleared by software.
    • [12]LPTIM3EN (def=0x0) // LPTIM3 clock enable This bit is set and cleared by software.
    • [13]LPTIM4EN (def=0x0) // LPTIM4 clock enable This bit is set and cleared by software.
    • [14]OPAMPEN (def=0x0) // OPAMP clock enable This bit is set and cleared by software.
    • [15]COMPEN (def=0x0) // COMP clock enable This bit is set and cleared by software.
    • [20]VREFEN (def=0x0) // VREFBUF clock enable This bit is set and cleared by software.
    • [21]RTCAPBEN (def=0x0) // RTC and TAMP APB clock enable This bit is set and cleared by software.
  • 0x56020CB0RCC_AHB1SMENR// RCC AHB1 peripheral clock enable in Sleep and Stop modes register

    • [0]GPDMA1SMEN (def=0x1) // GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [1]CORDICSMEN (def=0x1) // CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sle
    • [2]FMACSMEN (def=0x1) // FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software.
    • [3]MDF1SMEN (def=0x1) // MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This
    • [8]FLASHSMEN (def=0x1) // FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [12]CRCSMEN (def=0x1) // CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [15]JPEGSMEN (def=0x1) // JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [16]TSCSMEN (def=0x1) // TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [17]RAMCFGSMEN (def=0x1) // RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [18]DMA2DSMEN (def=0x1) // DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [19]GFXMMUSMEN (def=0x1) // GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [20]GPU2DSMEN (def=0x1) // GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [21]DCACHE2SMEN (def=0x1) // DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [24]GTZC1SMEN (def=0x1) // GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [28]BKPSRAMSMEN (def=0x1) // BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software
    • [29]ICACHESMEN (def=0x1) // ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [30]DCACHE1SMEN (def=0x1) // DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM1SMEN (def=0x1) // SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x56020CB4RCC_AHB2SMENR1// RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1

    • [0]GPIOASMEN (def=0x1) // I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [1]GPIOBSMEN (def=0x1) // I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]GPIOCSMEN (def=0x1) // I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [3]GPIODSMEN (def=0x1) // I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [4]GPIOESMEN (def=0x1) // I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]GPIOFSMEN (def=0x1) // I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [6]GPIOGSMEN (def=0x1) // I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [7]GPIOHSMEN (def=0x1) // I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software.
    • [8]GPIOISMEN (def=0x1) // I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [9]GPIOJSMEN (def=0x1) // I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note:
    • [10]ADC12SMEN (def=0x1) // ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Not
    • [12]DCMI_PSSISMEN (def=0x1) // DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [14]OTGSMEN (def=0x1) // OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software
    • [15]OTGHSPHYSMEN (def=0x1) // OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: T
    • [16]AESSMEN (def=0x1) // AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit
    • [17]HASHSMEN (def=0x1) // HASH clock enable during Sleep and Stop modes This bit is set and cleared by software
    • [18]RNGSMEN (def=0x1) // RNG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [19]PKASMEN (def=0x1) // PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
    • [20]SAESSMEN (def=0x1) // SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]OCTOSPIMSMEN (def=0x1) // OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Th
    • [23]OTFDEC1SMEN (def=0x1) // OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [24]OTFDEC2SMEN (def=0x1) // OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [27]SDMMC1SMEN (def=0x1) // SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [28]SDMMC2SMEN (def=0x1) // SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [30]SRAM2SMEN (def=0x1) // SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM3SMEN (def=0x1) // SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x56020CB8RCC_AHB2SMENR2// RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2

    • [0]FSMCSMEN (def=0x1) // FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [4]OCTOSPI1SMEN (def=0x1) // OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [8]OCTOSPI2SMEN (def=0x1) // OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Th
    • [12]HSPI1SMEN (def=0x1) // HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [30]SRAM6SMEN (def=0x1) // SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [31]SRAM5SMEN (def=0x1) // SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x56020CBCRCC_AHB3SMENR// RCC AHB3 peripheral clock enable in Sleep and Stop modes register

    • [0]LPGPIO1SMEN (def=0x1) // LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]PWRSMEN (def=0x1) // PWR clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]ADC4SMEN (def=0x1) // ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [6]DAC1SMEN (def=0x1) // DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [9]LPDMA1SMEN (def=0x1) // LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [10]ADF1SMEN (def=0x1) // ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [12]GTZC2SMEN (def=0x1) // GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [31]SRAM4SMEN (def=0x1) // SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x56020CC4RCC_APB1SMENR1// RCC APB1 peripheral clock enable in Sleep and Stop modes register 1

    • [0]TIM2SMEN (def=0x1) // TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [1]TIM3SMEN (def=0x1) // TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [2]TIM4SMEN (def=0x1) // TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [3]TIM5SMEN (def=0x1) // TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [4]TIM6SMEN (def=0x1) // TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]TIM7SMEN (def=0x1) // TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [11]WWDGSMEN (def=0x1) // Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. I
    • [14]SPI2SMEN (def=0x1) // SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [17]USART2SMEN (def=0x1) // USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [18]USART3SMEN (def=0x1) // USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [19]UART4SMEN (def=0x1) // UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [20]UART5SMEN (def=0x1) // UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [21]I2C1SMEN (def=0x1) // I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [22]I2C2SMEN (def=0x1) // I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [24]CRSSMEN (def=0x1) // CRS clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [25]USART6SMEN (def=0x1) // USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x56020CC8RCC_APB1SMENR2// RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

    • [1]I2C4SMEN (def=0x1) // I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [5]LPTIM2SMEN (def=0x1) // LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [6]I2C5SMEN (def=0x1) // I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [7]I2C6SMEN (def=0x1) // I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bi
    • [9]FDCAN1SMEN (def=0x1) // FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [23]UCPD1SMEN (def=0x1) // UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
  • 0x56020CCCRCC_APB2SMENR// RCC APB2 peripheral clocks enable in Sleep and Stop modes register

    • [11]TIM1SMEN (def=0x1) // TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [12]SPI1SMEN (def=0x1) // SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [13]TIM8SMEN (def=0x1) // TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [14]USART1SMEN (def=0x1) // USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [16]TIM15SMEN (def=0x1) // TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [17]TIM16SMEN (def=0x1) // TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [18]TIM17SMEN (def=0x1) // TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]SAI1SMEN (def=0x1) // SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [22]SAI2SMEN (def=0x1) // SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [24]USBSMEN (def=0x1) // USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
    • [25]GFXTIMSMEN (def=0x1) // GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [26]LTDCSMEN (def=0x1) // LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [27]DSISMEN (def=0x1) // DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bi
  • 0x56020CD0RCC_APB3SMENR// RCC APB3 peripheral clock enable in Sleep and Stop modes register

    • [1]SYSCFGSMEN (def=0x1) // SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [5]SPI3SMEN (def=0x1) // SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [6]LPUART1SMEN (def=0x1) // LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: Thi
    • [7]I2C3SMEN (def=0x1) // I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This b
    • [11]LPTIM1SMEN (def=0x1) // LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [12]LPTIM3SMEN (def=0x1) // LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [13]LPTIM4SMEN (def=0x1) // LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This
    • [14]OPAMPSMEN (def=0x1) // OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [15]COMPSMEN (def=0x1) // COMP clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [20]VREFSMEN (def=0x1) // VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software.
    • [21]RTCAPBSMEN (def=0x1) // RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software.
  • 0x56020CD8RCC_SRDAMR// RCC SmartRun domain peripheral autonomous mode register

    • [5]SPI3AMEN (def=0x0) // SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This
    • [6]LPUART1AMEN (def=0x0) // LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Th
    • [7]I2C3AMEN (def=0x0) // I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [11]LPTIM1AMEN (def=0x0) // LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [12]LPTIM3AMEN (def=0x0) // LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [13]LPTIM4AMEN (def=0x0) // LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [14]OPAMPAMEN (def=0x0) // OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [15]COMPAMEN (def=0x0) // COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [20]VREFAMEN (def=0x0) // VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [21]RTCAPBAMEN (def=0x0) // RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Not
    • [25]ADC4AMEN (def=0x0) // ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [26]LPGPIO1AMEN (def=0x0) // LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
    • [27]DAC1AMEN (def=0x0) // DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [28]LPDMA1AMEN (def=0x0) // LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: Thi
    • [29]ADF1AMEN (def=0x0) // ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This
    • [31]SRAM4AMEN (def=0x0) // SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software.
  • 0x56020CE0RCC_CCIPR1// RCC peripherals independent clock configuration register 1

    • [0:1]USART1SEL (def=0x0) // USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source.
    • [2:3]USART2SEL (def=0x0) // USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source.
    • [4:5]USART3SEL (def=0x0) // USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source.
    • [6:7]UART4SEL (def=0x0) // UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. No
    • [8:9]UART5SEL (def=0x0) // UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. No
    • [10:11]I2C1SEL (def=0x0) // I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note
    • [12:13]I2C2SEL (def=0x0) // I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note
    • [14:15]I2C4SEL (def=0x0) // I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note
    • [16:17]SPI2SEL (def=0x0) // SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note
    • [18:19]LPTIM2SEL (def=0x0) // Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clo
    • [20:21]SPI1SEL (def=0x0) // SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note
    • [22:23]SYSTICKSEL (def=0x0) // SysTick clock source selection These bits are used to select the SysTick clock source. Note: When L
    • [24:25]FDCAN1SEL (def=0x0) // FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source.
    • [26:27]ICLKSEL (def=0x0) // Intermediate clock source selection These bits are used to select the clock source for the OTG_FS,
    • [29:31]TIMICSEL (def=0x0) // Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16,
  • 0x56020CE4RCC_CCIPR2// RCC peripherals independent clock configuration register 2

    • [0:2]MDF1SEL (def=0x0) // MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. othe
    • [5:7]SAI1SEL (def=0x0) // SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. othe
    • [8:10]SAI2SEL (def=0x0) // SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. othe
    • [11]SAESSEL (def=0x0) // SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: T
    • [12:13]RNGSEL (def=0x0) // RNG kernel clock source selection These bits are used to select the RNG kernel clock source.
    • [14]SDMMCSEL (def=0x0) // SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock s
    • [15]DSISEL (def=0x0) // DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit
    • [16:17]USART6SEL (def=0x0) // USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source.
    • [18]LTDCSEL (def=0x0) // LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: T
    • [20:21]OCTOSPISEL (def=0x0) // OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and
    • [22:23]HSPI1SEL (def=0x0) // HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. No
    • [24:25]I2C5SEL (def=0x0) // I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The
    • [26:27]I2C6SEL (def=0x0) // I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The
    • [30:31]OTGHSSEL (def=0x0) // OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock
  • 0x56020CE8RCC_CCIPR3// RCC peripherals independent clock configuration register 3

    • [0:2]LPUART1SEL (def=0x0) // LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source
    • [3:4]SPI3SEL (def=0x0) // SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note
    • [6:7]I2C3SEL (def=0x0) // I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note
    • [8:9]LPTIM34SEL (def=0x0) // LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4
    • [10:11]LPTIM1SEL (def=0x0) // LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source.
    • [12:14]ADCDACSEL (def=0x0) // ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC
    • [15]DAC1SEL (def=0x0) // DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clo
    • [16:18]ADF1SEL (def=0x0) // ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. othe
  • 0x56020CF0RCC_BDCR// RCC backup domain control register

    • [0]LSEON (def=0x0) // LSE oscillator enable This bit is set and cleared by software.
    • [1]LSERDY (def=0x0) // LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz
    • [2]LSEBYP (def=0x0) // LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. I
    • [3:4]LSEDRV (def=0x0) // LSE oscillator drive capability This bitfield is set by software to modulate the drive capability o
    • [5]LSECSSON (def=0x0) // CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after th
    • [6]LSECSSD (def=0x0) // CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by
    • [7]LSESYSEN (def=0x0) // LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock
    • [8:9]RTCSEL (def=0x0) // RTC and TAMP clock source selection This bit is set by software to select the clock source for the
    • [11]LSESYSRDY (def=0x0) // LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE sy
    • [12]LSEGFON (def=0x0) // LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch fil
    • [15]RTCEN (def=0x0) // RTC and TAMP clock enable This bit is set and cleared by software.
    • [16]BDRST (def=0x0) // Backup domain software reset This bit is set and cleared by software.
    • [24]LSCOEN (def=0x0) // Low-speed clock output (LSCO) enable This bit is set and cleared by software.
    • [25]LSCOSEL (def=0x0) // Low-speed clock output selection This bit is set and cleared by software.
    • [26]LSION (def=0x0) // LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60�
    • [27]LSIRDY (def=0x0) // LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is
    • [28]LSIPREDIV (def=0x0) // Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI div
  • 0x56020CF4RCC_CSR// RCC control/status register

    • [8:11]MSIKSRANGE (def=0x4) // MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. I
    • [12:15]MSISSRANGE (def=0x4) // MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at start
    • [23]RMVF (def=0x0) // Remove reset flag This bit is set by software to clear the reset flags.
    • [25]OBLRSTF (def=0x0) // Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading
    • [26]PINRSTF (def=0x1) // NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleare
    • [27]BORRSTF (def=0x1) // Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout
    • [28]SFTRSTF (def=0x0) // Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writ
    • [29]IWDGRSTF (def=0x0) // Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset doma
    • [30]WWDGRSTF (def=0x0) // Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is c
    • [31]LPWRRSTF (def=0x0) // Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shu
  • 0x56020D10RCC_SECCFGR// RCC secure configuration register

    • [0]HSISEC (def=0x0) // HSI clock configuration and status bit security This bit is set and reset by software.
    • [1]HSESEC (def=0x0) // HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software
    • [2]MSISEC (def=0x0) // MSI clock configuration and status bit security This bit is set and reset by software.
    • [3]LSISEC (def=0x0) // LSI clock configuration and status bit security This bit is set and reset by software.
    • [4]LSESEC (def=0x0) // LSE clock configuration and status bit security This bit is set and reset by software.
    • [5]SYSCLKSEC (def=0x0) // SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set an
    • [6]PRESCSEC (def=0x0) // AHBx/APBx prescaler configuration bits security This bit is set and reset by software.
    • [7]PLL1SEC (def=0x0) // PLL1 clock configuration and status bit security This bit is set and reset by software.
    • [8]PLL2SEC (def=0x0) // PLL2 clock configuration and status bit security Set and reset by software.
    • [9]PLL3SEC (def=0x0) // PLL3 clock configuration and status bit security This bit is set and reset by software.
    • [10]ICLKSEC (def=0x0) // Intermediate clock source selection security This bit is set and reset by software.
    • [11]HSI48SEC (def=0x0) // HSI48 clock configuration and status bit security This bit is set and reset by software.
    • [12]RMVFSEC (def=0x0) // Remove reset flag security This bit is set and reset by software.
  • 0x56020D14RCC_PRIVCFGR// RCC privilege configuration register

    • [0]SPRIV (def=0x0) // RCC secure function privilege configuration This bit is set and reset by software. It can be writte
    • [1]NSPRIV (def=0x0) // RCC non-secure function privilege configuration This bit is set and reset by software. It can be wr
• 0x46007800RTC// Real-time clock

  • 0x46007800TR// time register

    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x46007804DR// date register

    • [20:23]YT (def=0x0) // Year tens in BCD format
    • [16:19]YU (def=0x0) // Year units in BCD format
    • [13:15]WDU (def=0x1) // Week day units
    • [12]MT (def=0x0) // Month tens in BCD format
    • [8:11]MU (def=0x1) // Month units in BCD format
    • [4:5]DT (def=0x0) // Date tens in BCD format
    • [0:3]DU (def=0x1) // Date units in BCD format
  • 0x46007808SSR// RTC sub second register

    • [0:31]SS (def=0x0) // SS
  • 0x4600780CICSR// RTC initialization control and status register

    • [2]WUTWF (def=0x1) // Wakeup timer write flag
    • [3]SHPF (def=0x0) // Shift operation pending
    • [4]INITS (def=0x0) // Initialization status flag
    • [5]RSF (def=0x0) // Registers synchronization flag
    • [6]INITF (def=0x0) // Initialization flag
    • [7]INIT (def=0x0) // Initialization mode
    • [8:9]BIN (def=0x0) // BIN
    • [10:12]BCDU (def=0x0) // BCDU
    • [16]RECALPF (def=0x0) // Recalibration pending Flag
  • 0x46007810PRER// prescaler register

    • [16:22]PREDIV_A (def=0x7F) // Asynchronous prescaler factor
    • [0:14]PREDIV_S (def=0xFF) // Synchronous prescaler factor
  • 0x46007814WUTR// wakeup timer register

    • [0:15]WUT (def=0xFFFF) // Wakeup auto-reload value bits
    • [16:31]WUTOCLR (def=0x0) // WUTOCLR
  • 0x46007818CR// RTC control register

    • [0:2]WUCKSEL (def=0x0) // WUCKSEL
    • [3]TSEDGE (def=0x0) // TSEDGE
    • [4]REFCKON (def=0x0) // REFCKON
    • [5]BYPSHAD (def=0x0) // BYPSHAD
    • [6]FMT (def=0x0) // FMT
    • [7]SSRUIE (def=0x0) // SSRUIE
    • [8]ALRAE (def=0x0) // ALRAE
    • [9]ALRBE (def=0x0) // ALRBE
    • [10]WUTE (def=0x0) // WUTE
    • [11]TSE (def=0x0) // TSE
    • [12]ALRAIE (def=0x0) // ALRAIE
    • [13]ALRBIE (def=0x0) // ALRBIE
    • [14]WUTIE (def=0x0) // WUTIE
    • [15]TSIE (def=0x0) // TSIE
    • [16]ADD1H (def=0x0) // ADD1H
    • [17]SUB1H (def=0x0) // SUB1H
    • [18]BKP (def=0x0) // BKP
    • [19]COSEL (def=0x0) // COSEL
    • [20]POL (def=0x0) // POL
    • [21:22]OSEL (def=0x0) // OSEL
    • [23]COE (def=0x0) // COE
    • [24]ITSE (def=0x0) // ITSE
    • [25]TAMPTS (def=0x0) // TAMPTS
    • [26]TAMPOE (def=0x0) // TAMPOE
    • [27]ALRAFCLR (def=0x0) // ALRAFCLR
    • [28]ALRBFCLR (def=0x0) // ALRBFCLR
    • [29]TAMPALRM_PU (def=0x0) // TAMPALRM_PU
    • [30]TAMPALRM_TYPE (def=0x0) // TAMPALRM_TYPE
    • [31]OUT2EN (def=0x0) // OUT2EN
  • 0x4600781CPRIVCR// RTC privilege mode control register

    • [15]PRIV (def=0x0) // PRIV
    • [14]INITPRIV (def=0x0) // INITPRIV
    • [13]CALPRIV (def=0x0) // CALPRIV
    • [3]TSPRIV (def=0x0) // TSPRIV
    • [2]WUTPRIV (def=0x0) // WUTPRIV
    • [1]ALRBPRIV (def=0x0) // ALRBPRIV
    • [0]ALRAPRIV (def=0x0) // ALRAPRIV
  • 0x46007820SECCFGR// RTC secure mode control register

    • [15]SEC (def=0x0) // SEC
    • [14]INITSEC (def=0x0) // INITSEC
    • [13]CALSEC (def=0x0) // CALSEC
    • [3]TSSEC (def=0x0) // TSSEC
    • [2]WUTSEC (def=0x0) // WUTSEC
    • [1]ALRBSEC (def=0x0) // ALRBSEC
    • [0]ALRASEC (def=0x0) // ALRASEC
  • 0x46007824WPR// write protection register

    • [0:7]KEY (def=0x0) // Write protection key
  • 0x46007828CALR// calibration register

    • [15]CALP (def=0x0) // Increase frequency of RTC by 488.5 ppm
    • [14]CALW8 (def=0x0) // Use an 8-second calibration cycle period
    • [13]CALW16 (def=0x0) // Use a 16-second calibration cycle period
    • [12]LPCAL (def=0x0) // LPCAL
    • [0:8]CALM (def=0x0) // Calibration minus
  • 0x4600782CSHIFTR// shift control register

    • [31]ADD1S (def=0x0) // Add one second
    • [0:14]SUBFS (def=0x0) // Subtract a fraction of a second
  • 0x46007830TSTR// time stamp time register

    • [0:3]SU (def=0x0) // Second units in BCD format
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [22]PM (def=0x0) // AM/PM notation
  • 0x46007834TSDR// time stamp date register

    • [13:15]WDU (def=0x0) // Week day units
    • [12]MT (def=0x0) // Month tens in BCD format
    • [8:11]MU (def=0x0) // Month units in BCD format
    • [4:5]DT (def=0x0) // Date tens in BCD format
    • [0:3]DU (def=0x0) // Date units in BCD format
  • 0x46007838TSSSR// timestamp sub second register

    • [0:31]SS (def=0x0) // Sub second value
  • 0x46007840ALRMAR// alarm A register

    • [31]MSK4 (def=0x0) // Alarm A date mask
    • [30]WDSEL (def=0x0) // Week day selection
    • [28:29]DT (def=0x0) // Date tens in BCD format
    • [24:27]DU (def=0x0) // Date units or day in BCD format
    • [23]MSK3 (def=0x0) // Alarm A hours mask
    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [15]MSK2 (def=0x0) // Alarm A minutes mask
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [7]MSK1 (def=0x0) // Alarm A seconds mask
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x46007844ALRMASSR// alarm A sub second register

    • [31]SSCLR (def=0x0) // SSCLR
    • [24:29]MASKSS (def=0x0) // Mask the most-significant bits starting at this bit
    • [0:14]SS (def=0x0) // Sub seconds value
  • 0x46007848ALRMBR// alarm B register

    • [31]MSK4 (def=0x0) // Alarm B date mask
    • [30]WDSEL (def=0x0) // Week day selection
    • [28:29]DT (def=0x0) // Date tens in BCD format
    • [24:27]DU (def=0x0) // Date units or day in BCD format
    • [23]MSK3 (def=0x0) // Alarm B hours mask
    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [15]MSK2 (def=0x0) // Alarm B minutes mask
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [7]MSK1 (def=0x0) // Alarm B seconds mask
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x4600784CALRMBSSR// alarm B sub second register

    • [31]SSCLR (def=0x0) // SSCLR
    • [24:29]MASKSS (def=0x0) // Mask the most-significant bits starting at this bit
    • [0:14]SS (def=0x0) // Sub seconds value
  • 0x46007850SR// RTC status register

    • [0]ALRAF (def=0x0) // ALRAF
    • [1]ALRBF (def=0x0) // ALRBF
    • [2]WUTF (def=0x0) // WUTF
    • [3]TSF (def=0x0) // TSF
    • [4]TSOVF (def=0x0) // TSOVF
    • [5]ITSF (def=0x0) // ITSF
    • [6]SSRUF (def=0x0) // SSRUF
  • 0x46007854MISR// RTC non-secure masked interrupt status register

    • [0]ALRAMF (def=0x0) // ALRAMF
    • [1]ALRBMF (def=0x0) // ALRBMF
    • [2]WUTMF (def=0x0) // WUTMF
    • [3]TSMF (def=0x0) // TSMF
    • [4]TSOVMF (def=0x0) // TSOVMF
    • [5]ITSMF (def=0x0) // ITSMF
    • [6]SSRUMF (def=0x0) // SSRUMF
  • 0x46007858SMISR// RTC secure masked interrupt status register

    • [0]ALRAMF (def=0x0) // ALRAMF
    • [1]ALRBMF (def=0x0) // ALRBMF
    • [2]WUTMF (def=0x0) // WUTMF
    • [3]TSMF (def=0x0) // TSMF
    • [4]TSOVMF (def=0x0) // TSOVMF
    • [5]ITSMF (def=0x0) // ITSMF
    • [6]SSRUMF (def=0x0) // SSRUMF
  • 0x4600785CSCR// RTC status clear register

    • [0]CALRAF (def=0x0) // CALRAF
    • [1]CALRBF (def=0x0) // CALRBF
    • [2]CWUTF (def=0x0) // CWUTF
    • [3]CTSF (def=0x0) // CTSF
    • [4]CTSOVF (def=0x0) // CTSOVF
    • [5]CITSF (def=0x0) // CITSF
    • [6]CSSRUF (def=0x0) // CSSRUF
  • 0x46007870ALRABINR// RTC alarm A binary mode register

    • [0:31]SS (def=0x0) // Synchronous counter alarm value in Binary mode
  • 0x46007874ALRBBINR// RTC alarm B binary mode register

    • [0:31]SS (def=0x0) // Synchronous counter alarm value in Binary mode
  interrupts:
  • [2] RTC // RTC global non-secure interrupts
  • [3] RTC_S // RTC secure global secure interrupts
• 0x56007800SEC_RTC//

  • 0x56007800TR// time register

    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x56007804DR// date register

    • [20:23]YT (def=0x0) // Year tens in BCD format
    • [16:19]YU (def=0x0) // Year units in BCD format
    • [13:15]WDU (def=0x1) // Week day units
    • [12]MT (def=0x0) // Month tens in BCD format
    • [8:11]MU (def=0x1) // Month units in BCD format
    • [4:5]DT (def=0x0) // Date tens in BCD format
    • [0:3]DU (def=0x1) // Date units in BCD format
  • 0x56007808SSR// RTC sub second register

    • [0:31]SS (def=0x0) // SS
  • 0x5600780CICSR// RTC initialization control and status register

    • [2]WUTWF (def=0x1) // Wakeup timer write flag
    • [3]SHPF (def=0x0) // Shift operation pending
    • [4]INITS (def=0x0) // Initialization status flag
    • [5]RSF (def=0x0) // Registers synchronization flag
    • [6]INITF (def=0x0) // Initialization flag
    • [7]INIT (def=0x0) // Initialization mode
    • [8:9]BIN (def=0x0) // BIN
    • [10:12]BCDU (def=0x0) // BCDU
    • [16]RECALPF (def=0x0) // Recalibration pending Flag
  • 0x56007810PRER// prescaler register

    • [16:22]PREDIV_A (def=0x7F) // Asynchronous prescaler factor
    • [0:14]PREDIV_S (def=0xFF) // Synchronous prescaler factor
  • 0x56007814WUTR// wakeup timer register

    • [0:15]WUT (def=0xFFFF) // Wakeup auto-reload value bits
    • [16:31]WUTOCLR (def=0x0) // WUTOCLR
  • 0x56007818CR// RTC control register

    • [0:2]WUCKSEL (def=0x0) // WUCKSEL
    • [3]TSEDGE (def=0x0) // TSEDGE
    • [4]REFCKON (def=0x0) // REFCKON
    • [5]BYPSHAD (def=0x0) // BYPSHAD
    • [6]FMT (def=0x0) // FMT
    • [7]SSRUIE (def=0x0) // SSRUIE
    • [8]ALRAE (def=0x0) // ALRAE
    • [9]ALRBE (def=0x0) // ALRBE
    • [10]WUTE (def=0x0) // WUTE
    • [11]TSE (def=0x0) // TSE
    • [12]ALRAIE (def=0x0) // ALRAIE
    • [13]ALRBIE (def=0x0) // ALRBIE
    • [14]WUTIE (def=0x0) // WUTIE
    • [15]TSIE (def=0x0) // TSIE
    • [16]ADD1H (def=0x0) // ADD1H
    • [17]SUB1H (def=0x0) // SUB1H
    • [18]BKP (def=0x0) // BKP
    • [19]COSEL (def=0x0) // COSEL
    • [20]POL (def=0x0) // POL
    • [21:22]OSEL (def=0x0) // OSEL
    • [23]COE (def=0x0) // COE
    • [24]ITSE (def=0x0) // ITSE
    • [25]TAMPTS (def=0x0) // TAMPTS
    • [26]TAMPOE (def=0x0) // TAMPOE
    • [27]ALRAFCLR (def=0x0) // ALRAFCLR
    • [28]ALRBFCLR (def=0x0) // ALRBFCLR
    • [29]TAMPALRM_PU (def=0x0) // TAMPALRM_PU
    • [30]TAMPALRM_TYPE (def=0x0) // TAMPALRM_TYPE
    • [31]OUT2EN (def=0x0) // OUT2EN
  • 0x5600781CPRIVCR// RTC privilege mode control register

    • [15]PRIV (def=0x0) // PRIV
    • [14]INITPRIV (def=0x0) // INITPRIV
    • [13]CALPRIV (def=0x0) // CALPRIV
    • [3]TSPRIV (def=0x0) // TSPRIV
    • [2]WUTPRIV (def=0x0) // WUTPRIV
    • [1]ALRBPRIV (def=0x0) // ALRBPRIV
    • [0]ALRAPRIV (def=0x0) // ALRAPRIV
  • 0x56007820SECCFGR// RTC secure mode control register

    • [15]SEC (def=0x0) // SEC
    • [14]INITSEC (def=0x0) // INITSEC
    • [13]CALSEC (def=0x0) // CALSEC
    • [3]TSSEC (def=0x0) // TSSEC
    • [2]WUTSEC (def=0x0) // WUTSEC
    • [1]ALRBSEC (def=0x0) // ALRBSEC
    • [0]ALRASEC (def=0x0) // ALRASEC
  • 0x56007824WPR// write protection register

    • [0:7]KEY (def=0x0) // Write protection key
  • 0x56007828CALR// calibration register

    • [15]CALP (def=0x0) // Increase frequency of RTC by 488.5 ppm
    • [14]CALW8 (def=0x0) // Use an 8-second calibration cycle period
    • [13]CALW16 (def=0x0) // Use a 16-second calibration cycle period
    • [12]LPCAL (def=0x0) // LPCAL
    • [0:8]CALM (def=0x0) // Calibration minus
  • 0x5600782CSHIFTR// shift control register

    • [31]ADD1S (def=0x0) // Add one second
    • [0:14]SUBFS (def=0x0) // Subtract a fraction of a second
  • 0x56007830TSTR// time stamp time register

    • [0:3]SU (def=0x0) // Second units in BCD format
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [22]PM (def=0x0) // AM/PM notation
  • 0x56007834TSDR// time stamp date register

    • [13:15]WDU (def=0x0) // Week day units
    • [12]MT (def=0x0) // Month tens in BCD format
    • [8:11]MU (def=0x0) // Month units in BCD format
    • [4:5]DT (def=0x0) // Date tens in BCD format
    • [0:3]DU (def=0x0) // Date units in BCD format
  • 0x56007838TSSSR// timestamp sub second register

    • [0:31]SS (def=0x0) // Sub second value
  • 0x56007840ALRMAR// alarm A register

    • [31]MSK4 (def=0x0) // Alarm A date mask
    • [30]WDSEL (def=0x0) // Week day selection
    • [28:29]DT (def=0x0) // Date tens in BCD format
    • [24:27]DU (def=0x0) // Date units or day in BCD format
    • [23]MSK3 (def=0x0) // Alarm A hours mask
    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [15]MSK2 (def=0x0) // Alarm A minutes mask
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [7]MSK1 (def=0x0) // Alarm A seconds mask
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x56007844ALRMASSR// alarm A sub second register

    • [31]SSCLR (def=0x0) // SSCLR
    • [24:29]MASKSS (def=0x0) // Mask the most-significant bits starting at this bit
    • [0:14]SS (def=0x0) // Sub seconds value
  • 0x56007848ALRMBR// alarm B register

    • [31]MSK4 (def=0x0) // Alarm B date mask
    • [30]WDSEL (def=0x0) // Week day selection
    • [28:29]DT (def=0x0) // Date tens in BCD format
    • [24:27]DU (def=0x0) // Date units or day in BCD format
    • [23]MSK3 (def=0x0) // Alarm B hours mask
    • [22]PM (def=0x0) // AM/PM notation
    • [20:21]HT (def=0x0) // Hour tens in BCD format
    • [16:19]HU (def=0x0) // Hour units in BCD format
    • [15]MSK2 (def=0x0) // Alarm B minutes mask
    • [12:14]MNT (def=0x0) // Minute tens in BCD format
    • [8:11]MNU (def=0x0) // Minute units in BCD format
    • [7]MSK1 (def=0x0) // Alarm B seconds mask
    • [4:6]ST (def=0x0) // Second tens in BCD format
    • [0:3]SU (def=0x0) // Second units in BCD format
  • 0x5600784CALRMBSSR// alarm B sub second register

    • [31]SSCLR (def=0x0) // SSCLR
    • [24:29]MASKSS (def=0x0) // Mask the most-significant bits starting at this bit
    • [0:14]SS (def=0x0) // Sub seconds value
  • 0x56007850SR// RTC status register

    • [0]ALRAF (def=0x0) // ALRAF
    • [1]ALRBF (def=0x0) // ALRBF
    • [2]WUTF (def=0x0) // WUTF
    • [3]TSF (def=0x0) // TSF
    • [4]TSOVF (def=0x0) // TSOVF
    • [5]ITSF (def=0x0) // ITSF
    • [6]SSRUF (def=0x0) // SSRUF
  • 0x56007854MISR// RTC non-secure masked interrupt status register

    • [0]ALRAMF (def=0x0) // ALRAMF
    • [1]ALRBMF (def=0x0) // ALRBMF
    • [2]WUTMF (def=0x0) // WUTMF
    • [3]TSMF (def=0x0) // TSMF
    • [4]TSOVMF (def=0x0) // TSOVMF
    • [5]ITSMF (def=0x0) // ITSMF
    • [6]SSRUMF (def=0x0) // SSRUMF
  • 0x56007858SMISR// RTC secure masked interrupt status register

    • [0]ALRAMF (def=0x0) // ALRAMF
    • [1]ALRBMF (def=0x0) // ALRBMF
    • [2]WUTMF (def=0x0) // WUTMF
    • [3]TSMF (def=0x0) // TSMF
    • [4]TSOVMF (def=0x0) // TSOVMF
    • [5]ITSMF (def=0x0) // ITSMF
    • [6]SSRUMF (def=0x0) // SSRUMF
  • 0x5600785CSCR// RTC status clear register

    • [0]CALRAF (def=0x0) // CALRAF
    • [1]CALRBF (def=0x0) // CALRBF
    • [2]CWUTF (def=0x0) // CWUTF
    • [3]CTSF (def=0x0) // CTSF
    • [4]CTSOVF (def=0x0) // CTSOVF
    • [5]CITSF (def=0x0) // CITSF
    • [6]CSSRUF (def=0x0) // CSSRUF
  • 0x56007870ALRABINR// RTC alarm A binary mode register

    • [0:31]SS (def=0x0) // Synchronous counter alarm value in Binary mode
  • 0x56007874ALRBBINR// RTC alarm B binary mode register

    • [0:31]SS (def=0x0) // Synchronous counter alarm value in Binary mode
• 0x40015400SAI1// Serial audio interface

  • 0x40015400GCR// Global configuration register

    • [0:1]SYNCIN (def=0x0) // Synchronization inputs
    • [4:5]SYNCOUT (def=0x0) // Synchronization outputs
  • 0x40015404ACR1// A Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x40015424BCR1// B Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x40015408ACR2// A Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x40015428BCR2// B Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x4001540CAFRCR// A frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x4001542CBFRCR// B frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x40015410ASLOTR// A Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x40015430BSLOTR// B Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x40015414AIM// A Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x40015434BIM// B Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x40015418ASR// A Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag. This bit is read only
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x40015438BSR// B Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x4001541CACLRFR// A Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x4001543CBCLRFR// B Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x40015420ADR// A Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40015440BDR// B Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40015444PDMCR// PDM control register

    • [0]PDMEN (def=0x0) // PDM enable
    • [4:5]MICNBR (def=0x0) // MICNBR
    • [8]CKEN1 (def=0x0) // Clock enable of bitstream clock number 1
    • [9]CKEN2 (def=0x0) // CKEN2
    • [10]CKEN3 (def=0x0) // CKEN3
    • [11]CKEN4 (def=0x0) // CKEN4
  • 0x40015448PDMDLY// PDM delay register

    • [0:2]DLYM1L (def=0x0) // Delay line adjust for first microphone of pair 1
    • [4:6]DLYM1R (def=0x0) // Delay line adjust for second microphone of pair 1
    • [8:10]DLYM2L (def=0x0) // Delay line for first microphone of pair 2
    • [12:14]DLYM2R (def=0x0) // Delay line for second microphone of pair 2
    • [16:18]DLYM3L (def=0x0) // DLYM3L
    • [20:22]DLYM3R (def=0x0) // DLYM3R
    • [24:26]DLYM4L (def=0x0) // DLYM4L
    • [28:30]DLYM4R (def=0x0) // DLYM4R
  interrupts:
  • [0] SAI1 // SAI1 global interrupt
• 0x50015400SEC_SAI1//

  • 0x50015400GCR// Global configuration register

    • [0:1]SYNCIN (def=0x0) // Synchronization inputs
    • [4:5]SYNCOUT (def=0x0) // Synchronization outputs
  • 0x50015404ACR1// A Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x50015424BCR1// B Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x50015408ACR2// A Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x50015428BCR2// B Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x5001540CAFRCR// A frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x5001542CBFRCR// B frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x50015410ASLOTR// A Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x50015430BSLOTR// B Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x50015414AIM// A Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x50015434BIM// B Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x50015418ASR// A Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag. This bit is read only
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x50015438BSR// B Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x5001541CACLRFR// A Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x5001543CBCLRFR// B Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x50015420ADR// A Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x50015440BDR// B Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x50015444PDMCR// PDM control register

    • [0]PDMEN (def=0x0) // PDM enable
    • [4:5]MICNBR (def=0x0) // MICNBR
    • [8]CKEN1 (def=0x0) // Clock enable of bitstream clock number 1
    • [9]CKEN2 (def=0x0) // CKEN2
    • [10]CKEN3 (def=0x0) // CKEN3
    • [11]CKEN4 (def=0x0) // CKEN4
  • 0x50015448PDMDLY// PDM delay register

    • [0:2]DLYM1L (def=0x0) // Delay line adjust for first microphone of pair 1
    • [4:6]DLYM1R (def=0x0) // Delay line adjust for second microphone of pair 1
    • [8:10]DLYM2L (def=0x0) // Delay line for first microphone of pair 2
    • [12:14]DLYM2R (def=0x0) // Delay line for second microphone of pair 2
    • [16:18]DLYM3L (def=0x0) // DLYM3L
    • [20:22]DLYM3R (def=0x0) // DLYM3R
    • [24:26]DLYM4L (def=0x0) // DLYM4L
    • [28:30]DLYM4R (def=0x0) // DLYM4R
• 0x40015800SAI2//

  • 0x40015800GCR// Global configuration register

    • [0:1]SYNCIN (def=0x0) // Synchronization inputs
    • [4:5]SYNCOUT (def=0x0) // Synchronization outputs
  • 0x40015804ACR1// A Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x40015824BCR1// B Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x40015808ACR2// A Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x40015828BCR2// B Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x4001580CAFRCR// A frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x4001582CBFRCR// B frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x40015810ASLOTR// A Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x40015830BSLOTR// B Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x40015814AIM// A Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x40015834BIM// B Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x40015818ASR// A Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag. This bit is read only
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x40015838BSR// B Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x4001581CACLRFR// A Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x4001583CBCLRFR// B Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x40015820ADR// A Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40015840BDR// B Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40015844PDMCR// PDM control register

    • [0]PDMEN (def=0x0) // PDM enable
    • [4:5]MICNBR (def=0x0) // MICNBR
    • [8]CKEN1 (def=0x0) // Clock enable of bitstream clock number 1
    • [9]CKEN2 (def=0x0) // CKEN2
    • [10]CKEN3 (def=0x0) // CKEN3
    • [11]CKEN4 (def=0x0) // CKEN4
  • 0x40015848PDMDLY// PDM delay register

    • [0:2]DLYM1L (def=0x0) // Delay line adjust for first microphone of pair 1
    • [4:6]DLYM1R (def=0x0) // Delay line adjust for second microphone of pair 1
    • [8:10]DLYM2L (def=0x0) // Delay line for first microphone of pair 2
    • [12:14]DLYM2R (def=0x0) // Delay line for second microphone of pair 2
    • [16:18]DLYM3L (def=0x0) // DLYM3L
    • [20:22]DLYM3R (def=0x0) // DLYM3R
    • [24:26]DLYM4L (def=0x0) // DLYM4L
    • [28:30]DLYM4R (def=0x0) // DLYM4R
  interrupts:
  • [0] SAI2 // SAI2 global interrupt
• 0x50015800SEC_SAI2//

  • 0x50015800GCR// Global configuration register

    • [0:1]SYNCIN (def=0x0) // Synchronization inputs
    • [4:5]SYNCOUT (def=0x0) // Synchronization outputs
  • 0x50015804ACR1// A Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x50015824BCR1// B Configuration register 1

    • [27]MCKEN (def=0x0) // MCKEN
    • [26]OSR (def=0x0) // OSR
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [19]NODIV (def=0x0) // No divider
    • [17]DMAEN (def=0x0) // DMA enable
    • [16]SAIAEN (def=0x0) // Audio block A enable
    • [13]OUTDRIV (def=0x0) // Output drive
    • [12]MONO (def=0x0) // Mono mode
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [5:7]DS (def=0x2) // Data size
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [0:1]MODE (def=0x0) // Audio block mode
  • 0x50015808ACR2// A Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x50015828BCR2// B Configuration register 2

    • [14:15]COMP (def=0x0) // Companding mode
    • [13]CPL (def=0x0) // Complement bit
    • [7:12]MUTECN (def=0x0) // Mute counter
    • [6]MUTEVAL (def=0x0) // Mute value
    • [5]MUTE (def=0x0) // Mute
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [0:2]FTH (def=0x0) // FIFO threshold
  • 0x5001580CAFRCR// A frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x5001582CBFRCR// B frame configuration register

    • [18]FSOFF (def=0x0) // Frame synchronization offset
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [0:7]FRL (def=0x7) // Frame length
  • 0x50015810ASLOTR// A Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x50015830BSLOTR// B Slot register

    • [16:31]SLOTEN (def=0x0) // Slot enable
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [0:4]FBOFF (def=0x0) // First bit offset
  • 0x50015814AIM// A Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x50015834BIM// B Interrupt mask register

    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
  • 0x50015818ASR// A Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag. This bit is read only
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x50015838BSR// B Status register

    • [16:18]FLVL (def=0x0) // FIFO level threshold
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [4]CNRDY (def=0x0) // Codec not ready
    • [3]FREQ (def=0x1) // FIFO request
    • [2]WCKCFG (def=0x0) // Wrong clock configuration flag
    • [1]MUTEDET (def=0x0) // Mute detection
    • [0]OVRUDR (def=0x0) // Overrun / underrun
  • 0x5001581CACLRFR// A Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x5001583CBCLRFR// B Clear flag register

    • [6]CLFSDET (def=0x0) // Clear late frame synchronization detection flag
    • [5]CAFSDET (def=0x0) // Clear anticipated frame synchronization detection flag
    • [4]CCNRDY (def=0x0) // Clear codec not ready flag
    • [2]CWCKCFG (def=0x0) // Clear wrong clock configuration flag
    • [1]CMUTEDET (def=0x0) // Mute detection flag
    • [0]COVRUDR (def=0x0) // Clear overrun / underrun
  • 0x50015820ADR// A Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x50015840BDR// B Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x50015844PDMCR// PDM control register

    • [0]PDMEN (def=0x0) // PDM enable
    • [4:5]MICNBR (def=0x0) // MICNBR
    • [8]CKEN1 (def=0x0) // Clock enable of bitstream clock number 1
    • [9]CKEN2 (def=0x0) // CKEN2
    • [10]CKEN3 (def=0x0) // CKEN3
    • [11]CKEN4 (def=0x0) // CKEN4
  • 0x50015848PDMDLY// PDM delay register

    • [0:2]DLYM1L (def=0x0) // Delay line adjust for first microphone of pair 1
    • [4:6]DLYM1R (def=0x0) // Delay line adjust for second microphone of pair 1
    • [8:10]DLYM2L (def=0x0) // Delay line for first microphone of pair 2
    • [12:14]DLYM2R (def=0x0) // Delay line for second microphone of pair 2
    • [16:18]DLYM3L (def=0x0) // DLYM3L
    • [20:22]DLYM3R (def=0x0) // DLYM3R
    • [24:26]DLYM4L (def=0x0) // DLYM4L
    • [28:30]DLYM4R (def=0x0) // DLYM4R
• 0x40020000GPDMA1// GPDMA1

  • 0x40020000GPDMA_SECCFGR// GPDMA secure configuration register

    • [0]SEC0 (def=0x0) // SEC0
    • [1]SEC1 (def=0x0) // SEC1
    • [2]SEC2 (def=0x0) // SEC2
    • [3]SEC3 (def=0x0) // SEC3
    • [4]SEC4 (def=0x0) // SEC4
    • [5]SEC5 (def=0x0) // SEC5
    • [6]SEC6 (def=0x0) // SEC6
    • [7]SEC7 (def=0x0) // SEC7
    • [8]SEC8 (def=0x0) // SEC8
    • [9]SEC9 (def=0x0) // SEC9
    • [10]SEC10 (def=0x0) // SEC10
    • [11]SEC11 (def=0x0) // SEC11
    • [12]SEC12 (def=0x0) // SEC12
    • [13]SEC13 (def=0x0) // SEC13
    • [14]SEC14 (def=0x0) // SEC14
    • [15]SEC15 (def=0x0) // SEC15
  • 0x40020004GPDMA_PRIVCFGR// GPDMA privileged configuration register

    • [0]PRIV0 (def=0x0) // PRIV0
    • [1]PRIV1 (def=0x0) // PRIV1
    • [2]PRIV2 (def=0x0) // PRIV2
    • [3]PRIV3 (def=0x0) // PRIV3
    • [4]PRIV4 (def=0x0) // PRIV4
    • [5]PRIV5 (def=0x0) // PRIV5
    • [6]PRIV6 (def=0x0) // PRIV6
    • [7]PRIV7 (def=0x0) // PRIV7
    • [8]PRIV8 (def=0x0) // PRIV8
    • [9]PRIV9 (def=0x0) // PRIV9
    • [10]PRIV10 (def=0x0) // PRIV10
    • [11]PRIV11 (def=0x0) // PRIV11
    • [12]PRIV12 (def=0x0) // PRIV12
    • [13]PRIV13 (def=0x0) // PRIV13
    • [14]PRIV14 (def=0x0) // PRIV14
    • [15]PRIV15 (def=0x0) // PRIV15
  • 0x40020008GPDMA_RCFGLOCKR// GPDMA configuration lock register

    • [0]LOCK0 (def=0x0) // LOCK0
    • [1]LOCK1 (def=0x0) // LOCK1
    • [2]LOCK2 (def=0x0) // LOCK2
    • [3]LOCK3 (def=0x0) // LOCK3
    • [4]LOCK4 (def=0x0) // LOCK4
    • [5]LOCK5 (def=0x0) // LOCK5
    • [6]LOCK6 (def=0x0) // LOCK6
    • [7]LOCK7 (def=0x0) // LOCK7
    • [8]LOCK8 (def=0x0) // LOCK8
    • [9]LOCK9 (def=0x0) // LOCK9
    • [10]LOCK10 (def=0x0) // LOCK10
    • [11]LOCK11 (def=0x0) // LOCK11
    • [12]LOCK12 (def=0x0) // LOCK12
    • [13]LOCK13 (def=0x0) // LOCK13
    • [14]LOCK14 (def=0x0) // LOCK14
    • [15]LOCK15 (def=0x0) // LOCK15
  • 0x4002000CGPDMA_MISR// GPDMA non-secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
    • [4]MIS4 (def=0x0) // MIS4
    • [5]MIS5 (def=0x0) // MIS5
    • [6]MIS6 (def=0x0) // MIS6
    • [7]MIS7 (def=0x0) // MIS7
    • [8]MIS8 (def=0x0) // MIS8
    • [9]MIS9 (def=0x0) // MIS9
    • [10]MIS10 (def=0x0) // MIS10
    • [11]MIS11 (def=0x0) // MIS11
    • [12]MIS12 (def=0x0) // MIS12
    • [13]MIS13 (def=0x0) // MIS13
    • [14]MIS14 (def=0x0) // MIS14
    • [15]MIS15 (def=0x0) // MIS15
  • 0x40020010GPDMA_SMISR// GPDMA secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
    • [4]MIS4 (def=0x0) // MIS4
    • [5]MIS5 (def=0x0) // MIS5
    • [6]MIS6 (def=0x0) // MIS6
    • [7]MIS7 (def=0x0) // MIS7
    • [8]MIS8 (def=0x0) // MIS8
    • [9]MIS9 (def=0x0) // MIS9
    • [10]MIS10 (def=0x0) // MIS10
    • [11]MIS11 (def=0x0) // MIS11
    • [12]MIS12 (def=0x0) // MIS12
    • [13]MIS13 (def=0x0) // MIS13
    • [14]MIS14 (def=0x0) // MIS14
    • [15]MIS15 (def=0x0) // MIS15
  • 0x40020050GPDMA_C0LBAR// GPDMA channel 0 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002005CGPDMA_C0FCR// GPDMA channel 0 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020060GPDMA_C0SR// GPDMA channel 0 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020064GPDMA_C0CR// GPDMA channel 0 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020090GPDMA_C0TR1// GPDMA channel 0 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020094GPDMA_C0TR2// GPDMA channel 0 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020098GPDMA_C0BR1// GPDMA channel 0 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002009CGPDMA_C0SAR// GPDMA channel 0 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400200A0GPDMA_C0DAR// GPDMA channel 0 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400200CCGPDMA_C0LLR// GPDMA channel 0 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400200D0GPDMA_C1LBAR// GPDMA channel 1 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400200DCGPDMA_C1FCR// GPDMA channel 1 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400200E0GPDMA_C1SR// GPDMA channel 1 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400200E4GPDMA_C1CR// GPDMA channel 1 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020110GPDMA_C1TR1// GPDMA channel 1 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020114GPDMA_C1TR2// GPDMA channel 1 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020118GPDMA_C1BR1// GPDMA channel 1 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002011CGPDMA_C1SAR// GPDMA channel 1 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020120GPDMA_C1DAR// GPDMA channel 1 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002014CGPDMA_C1LLR// GPDMA channel 1 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020150GPDMA_C2LBAR// GPDMA channel 2 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002015CGPDMA_C2FCR// GPDMA channel 2 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020160GPDMA_C2SR// GPDMA channel 2 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020164GPDMA_C2CR// GPDMA channel 2 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020190GPDMA_C2TR1// GPDMA channel 2 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020194GPDMA_C2TR2// GPDMA channel 2 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020198GPDMA_C2BR1// GPDMA channel 2 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002019CGPDMA_C2SAR// GPDMA channel 2 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400201A0GPDMA_C2DAR// GPDMA channel 2 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400201CCGPDMA_C2LLR// GPDMA channel 2 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400201D0GPDMA_C3LBAR// GPDMA channel 3 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400201DCGPDMA_C3FCR// GPDMA channel 3 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400201E0GPDMA_C3SR// GPDMA channel 3 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400201E4GPDMA_C3CR// GPDMA channel 3 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020210GPDMA_C3TR1// GPDMA channel 3 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020214GPDMA_C3TR2// GPDMA channel 3 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020218GPDMA_C3BR1// GPDMA channel 3 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002021CGPDMA_C3SAR// GPDMA channel 3 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020220GPDMA_C3DAR// GPDMA channel 3 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002024CGPDMA_C3LLR// GPDMA channel 3 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020250GPDMA_C4LBAR// GPDMA channel 4 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002025CGPDMA_C4FCR// GPDMA channel 4 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020260GPDMA_C4SR// GPDMA channel 4 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020264GPDMA_C4CR// GPDMA channel 4 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020290GPDMA_C4TR1// GPDMA channel 4 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020294GPDMA_C4TR2// GPDMA channel 4 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020298GPDMA_C4BR1// GPDMA channel 4 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002029CGPDMA_C4SAR// GPDMA channel 4 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400202A0GPDMA_C4DAR// GPDMA channel 4 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400202CCGPDMA_C4LLR// GPDMA channel 4 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400202D0GPDMA_C5LBAR// GPDMA channel 5 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400202DCGPDMA_C5FCR// GPDMA channel 5 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400202E0GPDMA_C5SR// GPDMA channel 5 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400202E4GPDMA_C5CR// GPDMA channel 5 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020310GPDMA_C5TR1// GPDMA channel 5 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020314GPDMA_C5TR2// GPDMA channel 5 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020318GPDMA_C5BR1// GPDMA channel 5 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002031CGPDMA_C5SAR// GPDMA channel 5 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020320GPDMA_C5DAR// GPDMA channel 5 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002034CGPDMA_C5LLR// GPDMA channel 5 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020350GPDMA_C6LBAR// GPDMA channel 6 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002035CGPDMA_C6FCR// GPDMA channel 6 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020360GPDMA_C6SR// GPDMA channel 6 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020364GPDMA_C6CR// GPDMA channel 6 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020390GPDMA_C6TR1// GPDMA channel 6 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020394GPDMA_C6TR2// GPDMA channel 6 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020398GPDMA_C6BR1// GPDMA channel 6 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002039CGPDMA_C6SAR// GPDMA channel 6 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400203A0GPDMA_C6DAR// GPDMA channel 6 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400203CCGPDMA_C6LLR// GPDMA channel 6 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400203D0GPDMA_C7LBAR// GPDMA channel 7 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400203DCGPDMA_C7FCR// GPDMA channel 7 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400203E0GPDMA_C7SR// GPDMA channel 7 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400203E4GPDMA_C7CR// GPDMA channel 7 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020410GPDMA_C7TR1// GPDMA channel 7 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020414GPDMA_C7TR2// GPDMA channel 7 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020418GPDMA_C7BR1// GPDMA channel 7 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002041CGPDMA_C7SAR// GPDMA channel 7 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020420GPDMA_C7DAR// GPDMA channel 7 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002044CGPDMA_C7LLR// GPDMA channel 7 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020450GPDMA_C8LBAR// GPDMA channel 8 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002045CGPDMA_C8FCR// GPDMA channel 8 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020460GPDMA_C8SR// GPDMA channel 8 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020464GPDMA_C8CR// GPDMA channel 8 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020490GPDMA_C8TR1// GPDMA channel 8 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020494GPDMA_C8TR2// GPDMA channel 8 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020498GPDMA_C8BR1// GPDMA channel 8 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002049CGPDMA_C8SAR// GPDMA channel 8 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400204A0GPDMA_C8DAR// GPDMA channel 8 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400204CCGPDMA_C8LLR// GPDMA channel 8 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400204D0GPDMA_C9LBAR// GPDMA channel 9 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400204DCGPDMA_C9FCR// GPDMA channel 9 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400204E0GPDMA_C9SR// GPDMA channel 9 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400204E4GPDMA_C9CR// GPDMA channel 9 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020510GPDMA_C9TR1// GPDMA channel 9 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020514GPDMA_C9TR2// GPDMA channel 9 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020518GPDMA_C9BR1// GPDMA channel 9 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002051CGPDMA_C9SAR// GPDMA channel 9 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020520GPDMA_C9DAR// GPDMA channel 9 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002054CGPDMA_C9LLR// GPDMA channel 9 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020550GPDMA_C10LBAR// GPDMA channel 10 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002055CGPDMA_C10FCR// GPDMA channel 10 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020560GPDMA_C10SR// GPDMA channel 10 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020564GPDMA_C10CR// GPDMA channel 10 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020590GPDMA_C10TR1// GPDMA channel 10 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020594GPDMA_C10TR2// GPDMA channel 10 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020598GPDMA_C10BR1// GPDMA channel 10 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002059CGPDMA_C10SAR// GPDMA channel 10 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400205A0GPDMA_C10DAR// GPDMA channel 10 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400205CCGPDMA_C10LLR// GPDMA channel 10 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400205D0GPDMA_C11LBAR// GPDMA channel 11 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400205DCGPDMA_C11FCR// GPDMA channel 11 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400205E0GPDMA_C11SR// GPDMA channel 11 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400205E4GPDMA_C11CR// GPDMA channel 11 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020610GPDMA_C11TR1// GPDMA channel 11 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020614GPDMA_C11TR2// GPDMA channel 11 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020618GPDMA_C11BR1// GPDMA channel 11 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x4002061CGPDMA_C11SAR// GPDMA channel 11 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020620GPDMA_C11DAR// GPDMA channel 11 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x4002064CGPDMA_C11LLR// GPDMA channel 11 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020650GPDMA_C12LBAR// GPDMA channel 12 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002065CGPDMA_C12FCR// GPDMA channel 12 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020660GPDMA_C12SR// GPDMA channel 12 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020664GPDMA_C12CR// GPDMA channel 12 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020690GPDMA_C12TR1// GPDMA channel 12 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020694GPDMA_C12TR2// GPDMA channel 12 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020698GPDMA_C12BR1// GPDMA channel 12 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x4002069CGPDMA_C12SAR// GPDMA channel 12 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400206A0GPDMA_C12DAR// GPDMA channel 12 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400206A4GPDMA_C12TR3// GPDMA channel 12 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x400206A8GPDMA_C12BR2// GPDMA channel 12 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x400206CCGPDMA_C12LLR// GPDMA channel 12 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400206D0GPDMA_C13LBAR// GPDMA channel 13 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400206DCGPDMA_C13FCR// GPDMA channel 13 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400206E0GPDMA_C13SR// GPDMA channel 13 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400206E4GPDMA_C13CR// GPDMA channel 13 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020710GPDMA_C13TR1// GPDMA channel 13 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020714GPDMA_C13TR2// GPDMA channel 13 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020718GPDMA_C13BR1// GPDMA channel 13 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x4002071CGPDMA_C13SAR// GPDMA channel 13 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020720GPDMA_C13DAR// GPDMA channel 13 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x40020724GPDMA_C13TR3// GPDMA channel 13 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x40020728GPDMA_C13BR2// GPDMA channel 13 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x4002074CGPDMA_C13LLR// GPDMA channel 13 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x40020750GPDMA_C14LBAR// GPDMA channel 14 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x4002075CGPDMA_C14FCR// GPDMA channel 14 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x40020760GPDMA_C14SR// GPDMA channel 14 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x40020764GPDMA_C14CR// GPDMA channel 14 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020790GPDMA_C14TR1// GPDMA channel 14 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020794GPDMA_C14TR2// GPDMA channel 14 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020798GPDMA_C14BR1// GPDMA channel 14 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x4002079CGPDMA_C14SAR// GPDMA channel 14 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x400207A0GPDMA_C14DAR// GPDMA channel 14 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x400207A4GPDMA_C14TR3// GPDMA channel 14 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x400207A8GPDMA_C14BR2// GPDMA channel 14 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x400207CCGPDMA_C14LLR// GPDMA channel 14 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x400207D0GPDMA_C15LBAR// GPDMA channel 15 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x400207DCGPDMA_C15FCR// GPDMA channel 15 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x400207E0GPDMA_C15SR// GPDMA channel 15 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x400207E4GPDMA_C15CR// GPDMA channel 15 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x40020810GPDMA_C15TR1// GPDMA channel 15 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x40020814GPDMA_C15TR2// GPDMA channel 15 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x40020818GPDMA_C15BR1// GPDMA channel 15 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x4002081CGPDMA_C15SAR// GPDMA channel 15 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x40020820GPDMA_C15DAR// GPDMA channel 15 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x40020824GPDMA_C15TR3// GPDMA channel 15 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x40020828GPDMA_C15BR2// GPDMA channel 15 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x4002084CGPDMA_C15LLR// GPDMA channel 15 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  interrupts:
  • [2] GPDMA1_CH0 // GPDMA1 channel 0 global interrupt
  • [24] GPDMA1_CH1 // GPDMA1 channel 1 global interrupt
  • [25] GPDMA1_CH2 // GPDMA1 channel 2 global interrupt
  • [26] GPDMA1_CH3 // GPDMA1 channel 3 global interrupt
  • [27] GPDMA1_CH4 // GPDMA1 channel 4 global interrupt
  • [28] GPDMA1_CH5 // GPDMA1 channel 5 global interrupt
  • [29] GPDMA1_CH6 // GPDMA1 channel 6 global interrupt
  • [30] GPDMA1_CH7 // GPDMA1 channel 7 global interrupt
  • [0] GPDMA1_CH8 // GPDMA1 channel 8 global interrupt
  • [0] GPDMA1_CH9 // GPDMA1 channel 9 global interrupt
  • [0] GPDMA1_CH10 // GPDMA1 channel 10 global interrupt
  • [0] GPDMA1_CH11 // GPDMA1 channel 11 global interrupt
  • [0] GPDMA1_CH12 // GPDMA1 channel 12 global interrupt
  • [0] GPDMA1_CH13 // GPDMA1 channel 13 global interrupt
  • [0] GPDMA1_CH14 // GPDMA1 channel 14 global interrupt
  • [0] GPDMA1_CH15 // GPDMA1 channel 15 global interrupt
• 0x50020000SEC_GPDMA1//

  • 0x50020000GPDMA_SECCFGR// GPDMA secure configuration register

    • [0]SEC0 (def=0x0) // SEC0
    • [1]SEC1 (def=0x0) // SEC1
    • [2]SEC2 (def=0x0) // SEC2
    • [3]SEC3 (def=0x0) // SEC3
    • [4]SEC4 (def=0x0) // SEC4
    • [5]SEC5 (def=0x0) // SEC5
    • [6]SEC6 (def=0x0) // SEC6
    • [7]SEC7 (def=0x0) // SEC7
    • [8]SEC8 (def=0x0) // SEC8
    • [9]SEC9 (def=0x0) // SEC9
    • [10]SEC10 (def=0x0) // SEC10
    • [11]SEC11 (def=0x0) // SEC11
    • [12]SEC12 (def=0x0) // SEC12
    • [13]SEC13 (def=0x0) // SEC13
    • [14]SEC14 (def=0x0) // SEC14
    • [15]SEC15 (def=0x0) // SEC15
  • 0x50020004GPDMA_PRIVCFGR// GPDMA privileged configuration register

    • [0]PRIV0 (def=0x0) // PRIV0
    • [1]PRIV1 (def=0x0) // PRIV1
    • [2]PRIV2 (def=0x0) // PRIV2
    • [3]PRIV3 (def=0x0) // PRIV3
    • [4]PRIV4 (def=0x0) // PRIV4
    • [5]PRIV5 (def=0x0) // PRIV5
    • [6]PRIV6 (def=0x0) // PRIV6
    • [7]PRIV7 (def=0x0) // PRIV7
    • [8]PRIV8 (def=0x0) // PRIV8
    • [9]PRIV9 (def=0x0) // PRIV9
    • [10]PRIV10 (def=0x0) // PRIV10
    • [11]PRIV11 (def=0x0) // PRIV11
    • [12]PRIV12 (def=0x0) // PRIV12
    • [13]PRIV13 (def=0x0) // PRIV13
    • [14]PRIV14 (def=0x0) // PRIV14
    • [15]PRIV15 (def=0x0) // PRIV15
  • 0x50020008GPDMA_RCFGLOCKR// GPDMA configuration lock register

    • [0]LOCK0 (def=0x0) // LOCK0
    • [1]LOCK1 (def=0x0) // LOCK1
    • [2]LOCK2 (def=0x0) // LOCK2
    • [3]LOCK3 (def=0x0) // LOCK3
    • [4]LOCK4 (def=0x0) // LOCK4
    • [5]LOCK5 (def=0x0) // LOCK5
    • [6]LOCK6 (def=0x0) // LOCK6
    • [7]LOCK7 (def=0x0) // LOCK7
    • [8]LOCK8 (def=0x0) // LOCK8
    • [9]LOCK9 (def=0x0) // LOCK9
    • [10]LOCK10 (def=0x0) // LOCK10
    • [11]LOCK11 (def=0x0) // LOCK11
    • [12]LOCK12 (def=0x0) // LOCK12
    • [13]LOCK13 (def=0x0) // LOCK13
    • [14]LOCK14 (def=0x0) // LOCK14
    • [15]LOCK15 (def=0x0) // LOCK15
  • 0x5002000CGPDMA_MISR// GPDMA non-secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
    • [4]MIS4 (def=0x0) // MIS4
    • [5]MIS5 (def=0x0) // MIS5
    • [6]MIS6 (def=0x0) // MIS6
    • [7]MIS7 (def=0x0) // MIS7
    • [8]MIS8 (def=0x0) // MIS8
    • [9]MIS9 (def=0x0) // MIS9
    • [10]MIS10 (def=0x0) // MIS10
    • [11]MIS11 (def=0x0) // MIS11
    • [12]MIS12 (def=0x0) // MIS12
    • [13]MIS13 (def=0x0) // MIS13
    • [14]MIS14 (def=0x0) // MIS14
    • [15]MIS15 (def=0x0) // MIS15
  • 0x50020010GPDMA_SMISR// GPDMA secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
    • [4]MIS4 (def=0x0) // MIS4
    • [5]MIS5 (def=0x0) // MIS5
    • [6]MIS6 (def=0x0) // MIS6
    • [7]MIS7 (def=0x0) // MIS7
    • [8]MIS8 (def=0x0) // MIS8
    • [9]MIS9 (def=0x0) // MIS9
    • [10]MIS10 (def=0x0) // MIS10
    • [11]MIS11 (def=0x0) // MIS11
    • [12]MIS12 (def=0x0) // MIS12
    • [13]MIS13 (def=0x0) // MIS13
    • [14]MIS14 (def=0x0) // MIS14
    • [15]MIS15 (def=0x0) // MIS15
  • 0x50020050GPDMA_C0LBAR// GPDMA channel 0 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002005CGPDMA_C0FCR// GPDMA channel 0 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020060GPDMA_C0SR// GPDMA channel 0 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020064GPDMA_C0CR// GPDMA channel 0 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020090GPDMA_C0TR1// GPDMA channel 0 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020094GPDMA_C0TR2// GPDMA channel 0 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020098GPDMA_C0BR1// GPDMA channel 0 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002009CGPDMA_C0SAR// GPDMA channel 0 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500200A0GPDMA_C0DAR// GPDMA channel 0 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500200CCGPDMA_C0LLR// GPDMA channel 0 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500200D0GPDMA_C1LBAR// GPDMA channel 1 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500200DCGPDMA_C1FCR// GPDMA channel 1 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500200E0GPDMA_C1SR// GPDMA channel 1 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500200E4GPDMA_C1CR// GPDMA channel 1 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020110GPDMA_C1TR1// GPDMA channel 1 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020114GPDMA_C1TR2// GPDMA channel 1 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020118GPDMA_C1BR1// GPDMA channel 1 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002011CGPDMA_C1SAR// GPDMA channel 1 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020120GPDMA_C1DAR// GPDMA channel 1 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002014CGPDMA_C1LLR// GPDMA channel 1 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020150GPDMA_C2LBAR// GPDMA channel 2 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002015CGPDMA_C2FCR// GPDMA channel 2 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020160GPDMA_C2SR// GPDMA channel 2 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020164GPDMA_C2CR// GPDMA channel 2 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020190GPDMA_C2TR1// GPDMA channel 2 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020194GPDMA_C2TR2// GPDMA channel 2 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020198GPDMA_C2BR1// GPDMA channel 2 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002019CGPDMA_C2SAR// GPDMA channel 2 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500201A0GPDMA_C2DAR// GPDMA channel 2 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500201CCGPDMA_C2LLR// GPDMA channel 2 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500201D0GPDMA_C3LBAR// GPDMA channel 3 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500201DCGPDMA_C3FCR// GPDMA channel 3 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500201E0GPDMA_C3SR// GPDMA channel 3 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500201E4GPDMA_C3CR// GPDMA channel 3 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020210GPDMA_C3TR1// GPDMA channel 3 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020214GPDMA_C3TR2// GPDMA channel 3 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020218GPDMA_C3BR1// GPDMA channel 3 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002021CGPDMA_C3SAR// GPDMA channel 3 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020220GPDMA_C3DAR// GPDMA channel 3 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002024CGPDMA_C3LLR// GPDMA channel 3 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020250GPDMA_C4LBAR// GPDMA channel 4 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002025CGPDMA_C4FCR// GPDMA channel 4 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020260GPDMA_C4SR// GPDMA channel 4 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020264GPDMA_C4CR// GPDMA channel 4 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020290GPDMA_C4TR1// GPDMA channel 4 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020294GPDMA_C4TR2// GPDMA channel 4 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020298GPDMA_C4BR1// GPDMA channel 4 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002029CGPDMA_C4SAR// GPDMA channel 4 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500202A0GPDMA_C4DAR// GPDMA channel 4 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500202CCGPDMA_C4LLR// GPDMA channel 4 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500202D0GPDMA_C5LBAR// GPDMA channel 5 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500202DCGPDMA_C5FCR// GPDMA channel 5 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500202E0GPDMA_C5SR// GPDMA channel 5 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500202E4GPDMA_C5CR// GPDMA channel 5 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020310GPDMA_C5TR1// GPDMA channel 5 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020314GPDMA_C5TR2// GPDMA channel 5 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020318GPDMA_C5BR1// GPDMA channel 5 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002031CGPDMA_C5SAR// GPDMA channel 5 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020320GPDMA_C5DAR// GPDMA channel 5 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002034CGPDMA_C5LLR// GPDMA channel 5 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020350GPDMA_C6LBAR// GPDMA channel 6 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002035CGPDMA_C6FCR// GPDMA channel 6 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020360GPDMA_C6SR// GPDMA channel 6 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020364GPDMA_C6CR// GPDMA channel 6 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020390GPDMA_C6TR1// GPDMA channel 6 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020394GPDMA_C6TR2// GPDMA channel 6 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020398GPDMA_C6BR1// GPDMA channel 6 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002039CGPDMA_C6SAR// GPDMA channel 6 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500203A0GPDMA_C6DAR// GPDMA channel 6 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500203CCGPDMA_C6LLR// GPDMA channel 6 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500203D0GPDMA_C7LBAR// GPDMA channel 7 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500203DCGPDMA_C7FCR// GPDMA channel 7 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500203E0GPDMA_C7SR// GPDMA channel 7 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500203E4GPDMA_C7CR// GPDMA channel 7 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020410GPDMA_C7TR1// GPDMA channel 7 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020414GPDMA_C7TR2// GPDMA channel 7 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020418GPDMA_C7BR1// GPDMA channel 7 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002041CGPDMA_C7SAR// GPDMA channel 7 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020420GPDMA_C7DAR// GPDMA channel 7 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002044CGPDMA_C7LLR// GPDMA channel 7 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020450GPDMA_C8LBAR// GPDMA channel 8 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002045CGPDMA_C8FCR// GPDMA channel 8 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020460GPDMA_C8SR// GPDMA channel 8 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020464GPDMA_C8CR// GPDMA channel 8 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020490GPDMA_C8TR1// GPDMA channel 8 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020494GPDMA_C8TR2// GPDMA channel 8 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020498GPDMA_C8BR1// GPDMA channel 8 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002049CGPDMA_C8SAR// GPDMA channel 8 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500204A0GPDMA_C8DAR// GPDMA channel 8 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500204CCGPDMA_C8LLR// GPDMA channel 8 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500204D0GPDMA_C9LBAR// GPDMA channel 9 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500204DCGPDMA_C9FCR// GPDMA channel 9 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500204E0GPDMA_C9SR// GPDMA channel 9 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500204E4GPDMA_C9CR// GPDMA channel 9 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020510GPDMA_C9TR1// GPDMA channel 9 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020514GPDMA_C9TR2// GPDMA channel 9 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020518GPDMA_C9BR1// GPDMA channel 9 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002051CGPDMA_C9SAR// GPDMA channel 9 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020520GPDMA_C9DAR// GPDMA channel 9 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002054CGPDMA_C9LLR// GPDMA channel 9 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020550GPDMA_C10LBAR// GPDMA channel 10 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002055CGPDMA_C10FCR// GPDMA channel 10 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020560GPDMA_C10SR// GPDMA channel 10 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020564GPDMA_C10CR// GPDMA channel 10 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020590GPDMA_C10TR1// GPDMA channel 10 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020594GPDMA_C10TR2// GPDMA channel 10 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020598GPDMA_C10BR1// GPDMA channel 10 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002059CGPDMA_C10SAR// GPDMA channel 10 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500205A0GPDMA_C10DAR// GPDMA channel 10 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500205CCGPDMA_C10LLR// GPDMA channel 10 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500205D0GPDMA_C11LBAR// GPDMA channel 11 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500205DCGPDMA_C11FCR// GPDMA channel 11 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500205E0GPDMA_C11SR// GPDMA channel 11 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500205E4GPDMA_C11CR// GPDMA channel 11 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020610GPDMA_C11TR1// GPDMA channel 11 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020614GPDMA_C11TR2// GPDMA channel 11 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020618GPDMA_C11BR1// GPDMA channel 11 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
  • 0x5002061CGPDMA_C11SAR// GPDMA channel 11 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020620GPDMA_C11DAR// GPDMA channel 11 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x5002064CGPDMA_C11LLR// GPDMA channel 11 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020650GPDMA_C12LBAR// GPDMA channel 12 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002065CGPDMA_C12FCR// GPDMA channel 12 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020660GPDMA_C12SR// GPDMA channel 12 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020664GPDMA_C12CR// GPDMA channel 12 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020690GPDMA_C12TR1// GPDMA channel 12 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020694GPDMA_C12TR2// GPDMA channel 12 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020698GPDMA_C12BR1// GPDMA channel 12 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x5002069CGPDMA_C12SAR// GPDMA channel 12 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500206A0GPDMA_C12DAR// GPDMA channel 12 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500206A4GPDMA_C12TR3// GPDMA channel 12 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x500206A8GPDMA_C12BR2// GPDMA channel 12 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x500206CCGPDMA_C12LLR// GPDMA channel 12 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500206D0GPDMA_C13LBAR// GPDMA channel 13 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500206DCGPDMA_C13FCR// GPDMA channel 13 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500206E0GPDMA_C13SR// GPDMA channel 13 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500206E4GPDMA_C13CR// GPDMA channel 13 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020710GPDMA_C13TR1// GPDMA channel 13 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020714GPDMA_C13TR2// GPDMA channel 13 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020718GPDMA_C13BR1// GPDMA channel 13 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x5002071CGPDMA_C13SAR// GPDMA channel 13 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020720GPDMA_C13DAR// GPDMA channel 13 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x50020724GPDMA_C13TR3// GPDMA channel 13 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x50020728GPDMA_C13BR2// GPDMA channel 13 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x5002074CGPDMA_C13LLR// GPDMA channel 13 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x50020750GPDMA_C14LBAR// GPDMA channel 14 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x5002075CGPDMA_C14FCR// GPDMA channel 14 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x50020760GPDMA_C14SR// GPDMA channel 14 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x50020764GPDMA_C14CR// GPDMA channel 14 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020790GPDMA_C14TR1// GPDMA channel 14 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020794GPDMA_C14TR2// GPDMA channel 14 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020798GPDMA_C14BR1// GPDMA channel 14 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x5002079CGPDMA_C14SAR// GPDMA channel 14 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x500207A0GPDMA_C14DAR// GPDMA channel 14 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x500207A4GPDMA_C14TR3// GPDMA channel 14 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x500207A8GPDMA_C14BR2// GPDMA channel 14 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x500207CCGPDMA_C14LLR// GPDMA channel 14 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
  • 0x500207D0GPDMA_C15LBAR// GPDMA channel 15 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of GPDMA channel x
  • 0x500207DCGPDMA_C15FCR// GPDMA channel 15 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x500207E0GPDMA_C15SR// GPDMA channel 15 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN =�
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeate
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag
    • [16:23]FIFOL (def=0x0) // monitored FIFO level Number of available write beats in the FIFO, in units of the programmed desti
  • 0x500207E4GPDMA_C15CR// GPDMA channel 15 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the followin
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the curre
    • [17]LAP (def=0x0) // linked-list allocated port This bit is used to allocate the master port for the update of the GPDM
    • [22:23]PRIO (def=0x0) // priority level of the channel x GPDMA transfer versus others Note: This bit must be written when E
  • 0x50020810GPDMA_C15TR1// GPDMA channel 15 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a bur
    • [4:9]SBL_1 (def=0x0) // source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within
    • [11:12]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination
    • [13]SBX (def=0x0) // source byte exchange within the unaligned half-word of each source word If the source data width i
    • [14]SAP (def=0x0) // source allocated port This bit is used to allocate the master port for the source transfer Note:
    • [15]SSEC (def=0x0) // security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the acces
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data wi
    • [19]DINC (def=0x0) // destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant a
    • [20:25]DBL_1 (def=0x0) // destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat wi
    • [26]DBX (def=0x0) // destination byte exchange If the destination data size is a byte, this bit is ignored. If the des
    • [27]DHX (def=0x0) // destination half-word exchange If the destination data size is shorter than a word, this bit is ig
    • [30]DAP (def=0x0) // destination allocated port This bit is used to allocate the master port for the destination transf
    • [31]DSEC (def=0x0) // security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the ac
  • 0x50020814GPDMA_C15TR2// GPDMA channel 15 transfer register 2

    • [0:6]REQSEL (def=0x0) // GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN a
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
    • [10]DREQ (def=0x0) // destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted
    • [11]BREQ (def=0x0) // Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (so
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If t
    • [16:21]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the GPDMA transfer (as
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete
  • 0x50020818GPDMA_C15BR1// GPDMA channel 15 alternate block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. Whe
    • [16:26]BRC (def=0x0) // Block repeat counter This field contains the number of repetitions of the current block (0 to 2047
    • [28]SDEC (def=0x0) // source address decrement
    • [29]DDEC (def=0x0) // destination address decrement
    • [30]BRSDEC (def=0x0) // Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDE
    • [31]BRDDEC (def=0x0) // Block repeat destination address decrement Note: On top of this increment/decrement (depending on
  • 0x5002081CGPDMA_C15SAR// GPDMA channel 15 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During
  • 0x50020820GPDMA_C15DAR// GPDMA channel 15 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written.
  • 0x50020824GPDMA_C15TR3// GPDMA channel 15 transfer register 3

    • [0:12]SAO (def=0x0) // source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decr
    • [16:28]DAO (def=0x0) // destination address offset increment The destination address, pointed by GPDMA_CxDAR, is increment
  • 0x50020828GPDMA_C15BR2// GPDMA channel 15 block register 2

    • [0:15]BRSAO (def=0x0) // Block repeated source address offset For a channel with 2D addressing capability, this field is us
    • [16:31]BRDAO (def=0x0) // Block repeated destination address offset For a channel with 2D addressing capability, this field
  • 0x5002084CGPDMA_C15LLR// GPDMA channel 15 alternate linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 =�
    • [16]ULL (def=0x0) // Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from
    • [25]UB2 (def=0x0) // Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during
    • [26]UT3 (def=0x0) // Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during
    • [27]UDA (def=0x0) // Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from
    • [28]USA (def=0x0) // update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during
    • [29]UB1 (def=0x0) // Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during
    • [30]UT2 (def=0x0) // Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during
    • [31]UT1 (def=0x0) // Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during
• 0x46025000LPDMA1// LPDMA1

  • 0x46025000LPDMA_SECCFGR// LPDMA secure configuration register

    • [0]SEC0 (def=0x0) // SEC0
    • [1]SEC1 (def=0x0) // SEC1
    • [2]SEC2 (def=0x0) // SEC2
    • [3]SEC3 (def=0x0) // SEC3
  • 0x46025004LPDMA_PRIVCFGR// LPDMA privileged configuration register

    • [0]PRIV0 (def=0x0) // PRIV0
    • [1]PRIV1 (def=0x0) // PRIV1
    • [2]PRIV2 (def=0x0) // PRIV2
    • [3]PRIV3 (def=0x0) // PRIV3
  • 0x46025008LPDMA_RCFGLOCKR// LPDMA configuration lock register

    • [0]LOCK0 (def=0x0) // LOCK0
    • [1]LOCK1 (def=0x0) // LOCK1
    • [2]LOCK2 (def=0x0) // LOCK2
    • [3]LOCK3 (def=0x0) // LOCK3
  • 0x4602500CLPDMA_MISR// LPDMA non-secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
  • 0x46025010LPDMA_SMISR// LPDMA secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
  • 0x46025050LPDMA_C0LBAR// LPDMA channel 0 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x4602505CLPDMA_C0FCR// LPDMA channel 0 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x46025060LPDMA_C0SR// LPDMA channel 0 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x46025064LPDMA_C0CR// LPDMA channel 0 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x46025090LPDMA_C0TR1// LPDMA channel 0 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x46025094LPDMA_C0TR2// LPDMA channel 0 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x46025098LPDMA_C0BR1// LPDMA channel 0 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x4602509CLPDMA_C0SAR// LPDMA channel 0 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x460250A0LPDMA_C0DAR// LPDMA channel 0 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x460250CCLPDMA_C0LLR// LPDMA channel 0 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x460250D0LPDMA_C1LBAR// LPDMA channel 1 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x460250DCLPDMA_C1FCR// LPDMA channel 1 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x460250E0LPDMA_C1SR// LPDMA channel 1 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x460250E4LPDMA_C1CR// LPDMA channel 1 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x46025110LPDMA_C1TR1// LPDMA channel 1 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x46025114LPDMA_C1TR2// LPDMA channel 1 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x46025118LPDMA_C1BR1// LPDMA channel 1 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x4602511CLPDMA_C1SAR// LPDMA channel 1 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x46025120LPDMA_C1DAR// LPDMA channel 1 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x4602514CLPDMA_C1LLR// LPDMA channel 1 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x46025150LPDMA_C2LBAR// LPDMA channel 2 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x4602515CLPDMA_C2FCR// LPDMA channel 2 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x46025160LPDMA_C2SR// LPDMA channel 2 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x46025164LPDMA_C2CR// LPDMA channel 2 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x46025190LPDMA_C2TR1// LPDMA channel 2 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x46025194LPDMA_C2TR2// LPDMA channel 2 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x46025198LPDMA_C2BR1// LPDMA channel 2 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x4602519CLPDMA_C2SAR// LPDMA channel 2 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x460251A0LPDMA_C2DAR// LPDMA channel 2 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x460251CCLPDMA_C2LLR// LPDMA channel 2 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x460251D0LPDMA_C3LBAR// LPDMA channel 3 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x460251DCLPDMA_C3FCR// LPDMA channel 3 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x460251E0LPDMA_C3SR// LPDMA channel 3 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x460251E4LPDMA_C3CR// LPDMA channel 3 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x46025210LPDMA_C3TR1// LPDMA channel 3 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x46025214LPDMA_C3TR2// LPDMA channel 3 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x46025218LPDMA_C3BR1// LPDMA channel 3 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x4602521CLPDMA_C3SAR// LPDMA channel 3 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x46025220LPDMA_C3DAR// LPDMA channel 3 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x4602524CLPDMA_C3LLR// LPDMA channel 3 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  interrupts:
  • [114] LPDMA1_CH0 // LPDMA1 SmartRun channel 0 global interrupt
  • [115] LPDMA1_CH1 // LPDMA1 SmartRun channel 1 global interrupt
  • [116] LPDMA1_CH2 // LPDMA1 SmartRun channel 2 global interrupt
  • [117] LPDMA1_CH3 // LPDMA1 SmartRun channel 3 global interrupt
• 0x56025000SEC_LPDMA1//

  • 0x56025000LPDMA_SECCFGR// LPDMA secure configuration register

    • [0]SEC0 (def=0x0) // SEC0
    • [1]SEC1 (def=0x0) // SEC1
    • [2]SEC2 (def=0x0) // SEC2
    • [3]SEC3 (def=0x0) // SEC3
  • 0x56025004LPDMA_PRIVCFGR// LPDMA privileged configuration register

    • [0]PRIV0 (def=0x0) // PRIV0
    • [1]PRIV1 (def=0x0) // PRIV1
    • [2]PRIV2 (def=0x0) // PRIV2
    • [3]PRIV3 (def=0x0) // PRIV3
  • 0x56025008LPDMA_RCFGLOCKR// LPDMA configuration lock register

    • [0]LOCK0 (def=0x0) // LOCK0
    • [1]LOCK1 (def=0x0) // LOCK1
    • [2]LOCK2 (def=0x0) // LOCK2
    • [3]LOCK3 (def=0x0) // LOCK3
  • 0x5602500CLPDMA_MISR// LPDMA non-secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
  • 0x56025010LPDMA_SMISR// LPDMA secure masked interrupt status register

    • [0]MIS0 (def=0x0) // MIS0
    • [1]MIS1 (def=0x0) // MIS1
    • [2]MIS2 (def=0x0) // MIS2
    • [3]MIS3 (def=0x0) // MIS3
  • 0x56025050LPDMA_C0LBAR// LPDMA channel 0 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x5602505CLPDMA_C0FCR// LPDMA channel 0 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x56025060LPDMA_C0SR// LPDMA channel 0 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x56025064LPDMA_C0CR// LPDMA channel 0 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x56025090LPDMA_C0TR1// LPDMA channel 0 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x56025094LPDMA_C0TR2// LPDMA channel 0 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x56025098LPDMA_C0BR1// LPDMA channel 0 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x5602509CLPDMA_C0SAR// LPDMA channel 0 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x560250A0LPDMA_C0DAR// LPDMA channel 0 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x560250CCLPDMA_C0LLR// LPDMA channel 0 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x560250D0LPDMA_C1LBAR// LPDMA channel 1 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x560250DCLPDMA_C1FCR// LPDMA channel 1 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x560250E0LPDMA_C1SR// LPDMA channel 1 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x560250E4LPDMA_C1CR// LPDMA channel 1 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x56025110LPDMA_C1TR1// LPDMA channel 1 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x56025114LPDMA_C1TR2// LPDMA channel 1 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x56025118LPDMA_C1BR1// LPDMA channel 1 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x5602511CLPDMA_C1SAR// LPDMA channel 1 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x56025120LPDMA_C1DAR// LPDMA channel 1 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x5602514CLPDMA_C1LLR// LPDMA channel 1 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x56025150LPDMA_C2LBAR// LPDMA channel 2 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x5602515CLPDMA_C2FCR// LPDMA channel 2 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x56025160LPDMA_C2SR// LPDMA channel 2 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x56025164LPDMA_C2CR// LPDMA channel 2 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x56025190LPDMA_C2TR1// LPDMA channel 2 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x56025194LPDMA_C2TR2// LPDMA channel 2 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x56025198LPDMA_C2BR1// LPDMA channel 2 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x5602519CLPDMA_C2SAR// LPDMA channel 2 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x560251A0LPDMA_C2DAR// LPDMA channel 2 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x560251CCLPDMA_C2LLR// LPDMA channel 2 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
  • 0x560251D0LPDMA_C3LBAR// LPDMA channel 3 linked-list base address register

    • [16:31]LBA (def=0x0) // linked-list base address of LPDMA channel x
  • 0x560251DCLPDMA_C3FCR// LPDMA channel 3 flag clear register

    • [8]TCF (def=0x0) // transfer complete flag clear
    • [9]HTF (def=0x0) // half transfer flag clear
    • [10]DTEF (def=0x0) // data transfer error flag clear
    • [11]ULEF (def=0x0) // update link transfer error flag clear
    • [12]USEF (def=0x0) // user setting error flag clear
    • [13]SUSPF (def=0x0) // completed suspension flag clear
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x560251E0LPDMA_C3SR// LPDMA channel 3 status register

    • [0]IDLEF (def=0x1) // idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 
    • [8]TCF (def=0x0) // transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer com
    • [9]HTF (def=0x0) // half transfer flag An half transfer event is an half block transfer that occurs when half of the by
    • [10]DTEF (def=0x0) // data transfer error flag
    • [11]ULEF (def=0x0) // update link transfer error flag
    • [12]USEF (def=0x0) // user setting error flag
    • [13]SUSPF (def=0x0) // completed suspension flag
    • [14]TOF (def=0x0) // trigger overrun flag clear
  • 0x560251E4LPDMA_C3CR// LPDMA channel 3 control register

    • [0]EN (def=0x0) // enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever i
    • [1]RESET (def=0x0) // reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following
    • [2]SUSP (def=0x0) // suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever
    • [8]TCIE (def=0x0) // transfer complete interrupt enable
    • [9]HTIE (def=0x0) // half transfer complete interrupt enable
    • [10]DTEIE (def=0x0) // data transfer error interrupt enable
    • [11]ULEIE (def=0x0) // update link transfer error interrupt enable
    • [12]USEIE (def=0x0) // user setting error interrupt enable
    • [13]SUSPIE (def=0x0) // completed suspension interrupt enable
    • [14]TOIE (def=0x0) // trigger overrun interrupt enable
    • [16]LSM (def=0x0) // Link step mode First the block transfer is executed as defined by the current internal register fil
    • [22:23]PRIO (def=0x0) // priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN
  • 0x56025210LPDMA_C3TR1// LPDMA channel 3 transfer register 1

    • [0:1]SDW_LOG2 (def=0x0) // binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width ca
    • [3]SINC (def=0x0) // source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a sin
    • [11]PAM (def=0x0) // padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination tr
    • [15]SSEC (def=0x0) // security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access
    • [16:17]DDW_LOG2 (def=0x0) // binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data wid
    • [19]DINC (def=0x0) // destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant a
    • [31]DSEC (def=0x0) // security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the acc
  • 0x56025214LPDMA_C3TR2// LPDMA channel 3 transfer register 2

    • [0:4]REQSEL (def=0x0) // DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asse
    • [9]SWREQ (def=0x0) // software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
    • [11]BREQ (def=0x0) // block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (softw
    • [14:15]TRIGM (def=0x0) // trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the
    • [16:20]TRIGSEL (def=0x0) // trigger event input selection These bits select the trigger event input of the LPDMA transfer (as p
    • [24:25]TRIGPOL (def=0x0) // trigger event polarity These bits define the polarity of the selected trigger event input defined b
    • [30:31]TCEM (def=0x0) // transfer complete event mode These bits define the transfer granularity for the transfer complete a
  • 0x56025218LPDMA_C3BR1// LPDMA channel 3 block register 1

    • [0:15]BNDT (def=0x0) // block number of data bytes to transfer from the source Block size transferred from the source. When
  • 0x5602521CLPDMA_C3SAR// LPDMA channel 3 source address register

    • [0:31]SA (def=0x0) // source address This field is the pointer to the address from which the next data is read. During th
  • 0x56025220LPDMA_C3DAR// LPDMA channel 3 destination address register

    • [0:31]DA (def=0x0) // destination address This field is the pointer to the address from which the next data is written. D
  • 0x5602524CLPDMA_C3LLR// LPDMA channel 3 linked-list address register

    • [2:15]LA (def=0x0) // pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = 
    • [16]ULL (def=0x0) // Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR r
    • [27]UDA (def=0x0) // Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR r
    • [28]USA (def=0x0) // update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the me
    • [29]UB1 (def=0x0) // Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the me
    • [30]UT2 (def=0x0) // Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the me
    • [31]UT1 (def=0x0) // Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the me
• 0x40013000SPI1// Serial peripheral interface

  • 0x40013000SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x40013004SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x40013008SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x4001300CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x40013010SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x40013014SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x40013018SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x4001301CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x40013020SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x40013030SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x40013040SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x40013044SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x40013048SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x4001304CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
  interrupts:
  • [5] SPI1 // SPI1 global interrupt
• 0x50013000SEC_SPI1//

  • 0x50013000SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x50013004SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x50013008SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x5001300CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x50013010SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x50013014SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x50013018SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x5001301CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x50013020SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x50013030SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x50013040SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x50013044SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x50013048SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x5001304CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
• 0x40003800SPI2//

  • 0x40003800SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x40003804SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x40003808SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x4000380CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x40003810SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x40003814SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x40003818SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x4000381CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x40003820SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x40003830SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x40003840SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x40003844SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x40003848SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x4000384CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
  interrupts:
  • [48] SPI2 // SPI2 global interrupt
• 0x50003800SEC_SPI2//

  • 0x50003800SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x50003804SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x50003808SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x5000380CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x50003810SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x50003814SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x50003818SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x5000381CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x50003820SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x50003830SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x50003840SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x50003844SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x50003848SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x5000384CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
• 0x46002000SPI3//

  • 0x46002000SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x46002004SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x46002008SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x4600200CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x46002010SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x46002014SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x46002018SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x4600201CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x46002020SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x46002030SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x46002040SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x46002044SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x46002048SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x4600204CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
  interrupts:
  • [0] SPI3 // SPI3 global interrupt
• 0x56002000SEC_SPI3//

  • 0x56002000SPI_CR1//

    • [0]SPE (def=0x0) // serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer
    • [8]MASRX (def=0x0) // master automatic suspension in Receive mode This bit is set and cleared by software to control cont
    • [9]CSTART (def=0x0) // master transfer start This bit can be set by software if SPI is enabled only to start an SPI commun
    • [10]CSUSP (def=0x0) // master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, th
    • [11]HDDIR (def=0x0) // Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/T
    • [12]SSI (def=0x0) // internal SS signal input level This bit has an effect only when the SSM bit is set. The value of th
    • [13]CRC33_17 (def=0x0) // 32-bit CRC polynomial configuration
    • [14]RCRCINI (def=0x0) // CRC calculation initialization pattern control for receiver
    • [15]TCRCINI (def=0x0) // CRC calculation initialization pattern control for transmitter
    • [16]IOLOCK (def=0x0) // locking the AF configuration of associated IOs This bit is set by software and cleared by hardware
  • 0x56002004SPI_CR2//

    • [0:15]TSIZE (def=0x0) // number of data at current transfer When these bits are changed by software, the SPI has to be disab
  • 0x56002008SPI_CFG1// SPI configuration register 1

    • [0:4]DSIZE (def=0x7) // number of bits in at single SPI data frame ..... Note: Maximum data size can be limited up to 16-bi
    • [5:8]FTHLV (def=0x0) // FIFO threshold level Defines number of data frames at single data packet. Size of the packet should
    • [9]UDRCFG (def=0x0) // behavior of slave transmitter at underrun condition For more details see underrun condition.
    • [14]RXDMAEN (def=0x0) // Rx DMA stream enable
    • [15]TXDMAEN (def=0x0) // Tx DMA stream enable
    • [16:20]CRCSIZE (def=0x7) // length of CRC frame to be transacted and compared Most significant bits are taken into account from
    • [22]CRCEN (def=0x0) // hardware CRC computation enable
    • [28:30]MBR (def=0x0) // master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too
    • [31]BPASS (def=0x0) // bypass of the prescaler at master baud rate clock generator
  • 0x5600200CSPI_CFG2// SPI configuration register 2

    • [0:3]MSSI (def=0x0) // Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, insert
    • [4:7]MIDI (def=0x0) // master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) ins
    • [13]RDIOM (def=0x0) // RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter
    • [14]RDIOP (def=0x0) // RDY signal input/output polarity
    • [15]IOSWP (def=0x0) // swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins a
    • [17:18]COMM (def=0x0) // SPI Communication Mode
    • [19:21]SP (def=0x0) // serial protocol others: reserved, must not be used
    • [22]MASTER (def=0x0) // SPI Master
    • [23]LSBFRST (def=0x0) // data frame format
    • [24]CPHA (def=0x0) // clock phase
    • [25]CPOL (def=0x0) // clock polarity
    • [26]SSM (def=0x0) // software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the S
    • [28]SSIOP (def=0x0) // SS input/output polarity
    • [29]SSOE (def=0x0) // SS output enable This bit is taken into account in Master mode only
    • [30]SSOM (def=0x0) // SS output management in Master mode This bit is taken into account in Master mode when SSOE is enab
    • [31]AFCNTR (def=0x0) // alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be
  • 0x56002010SPI_IER//

    • [0]RXPIE (def=0x0) // RXP interrupt enable
    • [1]TXPIE (def=0x0) // TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event.
    • [2]DXPIE (def=0x0) // DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event.
    • [3]EOTIE (def=0x0) // EOT, SUSP and TXC interrupt enable
    • [4]TXTFIE (def=0x0) // TXTFIE interrupt enable
    • [5]UDRIE (def=0x0) // UDR interrupt enable
    • [6]OVRIE (def=0x0) // OVR interrupt enable
    • [7]CRCEIE (def=0x0) // CRC error interrupt enable
    • [8]TIFREIE (def=0x0) // TIFRE interrupt enable
    • [9]MODFIE (def=0x0) // mode Fault interrupt enable
  • 0x56002014SPI_SR//

    • [0]RXP (def=0x0) // Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently a
    • [1]TXP (def=0x1) // Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently avai
    • [2]DXP (def=0x0) // duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.
    • [3]EOT (def=0x0) // end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE n
    • [4]TXTF (def=0x0) // transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transf
    • [5]UDR (def=0x0) // underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note:
    • [6]OVR (def=0x0) // overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR
    • [7]CRCE (def=0x0) // CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR
    • [8]TIFRE (def=0x0) // TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR
    • [9]MODF (def=0x0) // mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR
    • [11]SUSP (def=0x0) // suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is co
    • [12]TXC (def=0x1) // TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is ch
    • [13:14]RXPLVL (def=0x0) // RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of rema
    • [15]RXWNE (def=0x0) // RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with
    • [16:31]CTSIZE (def=0x0) // number of data frames remaining in current TSIZE session The value is not quite reliable when traff
  • 0x56002018SPI_IFCR//

    • [3]EOTC (def=0x0) // end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
    • [4]TXTFC (def=0x0) // transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR re
    • [5]UDRC (def=0x0) // underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
    • [6]OVRC (def=0x0) // overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
    • [7]CRCEC (def=0x0) // CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
    • [8]TIFREC (def=0x0) // TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
    • [9]MODFC (def=0x0) // mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
    • [11]SUSPC (def=0x0) // SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
  • 0x5600201CSPI_AUTOCR//

    • [16:19]TRIGSEL (def=0x0) // trigger selection (refer ). ... Note: these bits can be written only when SPE = 0.
    • [20]TRIGPOL (def=0x0) // trigger polarity Note: This bit can be written only when SPE = 0.
    • [21]TRIGEN (def=0x0) // trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN
  • 0x56002020SPI_TXDR//

    • [0:31]TXDR (def=0x0) // transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFI
  • 0x56002030SPI_RXDR//

    • [0:31]RXDR (def=0x0) // receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is a
  • 0x56002040SPI_CRCPOLY// SPI polynomial register

    • [0:31]CRCPOLY (def=0x107) // CRC polynomial register This register contains the polynomial for the CRC calculation. The default
  • 0x56002044SPI_TXCRC//

    • [0:31]TXCRC (def=0x0) // CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the comp
  • 0x56002048SPI_RXCRC//

    • [0:31]RXCRC (def=0x0) // CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the compute
  • 0x5600204CSPI_UDRDR// SPI underrun data register

    • [0:31]UDRDR (def=0x0) // data at slave underrun condition The register is taken into account in Slave mode and at underrun c
• 0x40012C00TIM1// Advanced-timers

  • 0x40012C00TIM1_CR1// TIM1 control register 1

    • [0]CEN (def=0x0) // Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has b
    • [1]UDIS (def=0x0) // Update disable This bit is set and cleared by software to enable/disable UEV event generation. Coun
    • [2]URS (def=0x0) // Update request source This bit is set and cleared by software to select the UEV event sources. Coun
    • [3]OPM (def=0x0) // One pulse mode
    • [4]DIR (def=0x0) // Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encode
    • [5:6]CMS (def=0x0) // Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-al
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [8:9]CKD (def=0x0) // Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) fre
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [12]DITHEN (def=0x0) // Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset.
  • 0x40012C04TIM1_CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection 2
    • [20:23]MMS2 (def=0x0) // Master mode selection 2
    • [18]OIS6 (def=0x0) // Output Idle state 6
    • [16]OIS5 (def=0x0) // Output Idle state 5
    • [15]OIS4N (def=0x0) // Output Idle state 4 (OC5 output)
    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS0_2 (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40012C08TIM1_SMCR// TIM1 slave mode control register

    • [0:2]SMS1 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [3]OCCS (def=0x0) // OCREF clear selection This bit is used to select the OCREF clear source.
    • [4:6]TS1 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [7]MSM (def=0x0) // Master/slave mode
    • [8:11]ETF (def=0x0) // External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal an
    • [12:13]ETPS (def=0x0) // External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCL
    • [14]ECE (def=0x0) // External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the sam
    • [15]ETP (def=0x0) // External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger ope
    • [16]SMS2 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [20:21]TS2 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [24]SMSPE (def=0x0) // SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded
    • [25]SMSPS (def=0x0) // SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer
  • 0x40012C0CTIM1_DIER// TIM1 DMA/interrupt enable register

    • [0]UIE (def=0x0) // Update interrupt enable
    • [1]CC1IE (def=0x0) // Capture/compare 1 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/compare 3 interrupt enable
    • [4]CC4IE (def=0x0) // Capture/compare 4 interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [9]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/compare 3 DMA request enable
    • [12]CC4DE (def=0x0) // Capture/compare 4 DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [23]TERRIE (def=0x0) // Transition error interrupt enable
  • 0x40012C10TIM1_SR// TIM1 status register

    • [0]UIF (def=0x0) // Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input cap
    • [2]CC2IF (def=0x0) // Capture/compare 2 interrupt flag Refer to CC1IF description
    • [3]CC3IF (def=0x0) // Capture/compare 3 interrupt flag Refer to CC1IF description
    • [4]CC4IF (def=0x0) // Capture/compare 4 interrupt flag Refer to CC1IF description
    • [5]COMIF (def=0x0) // COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - C
    • [6]TIF (def=0x0) // Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected
    • [7]BIF (def=0x0) // Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be
    • [8]B2IF (def=0x0) // Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It ca
    • [9]CC1OF (def=0x0) // Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag Refer to CC1OF description
    • [11]CC3OF (def=0x0) // Capture/compare 3 overcapture flag Refer to CC1OF description
    • [12]CC4OF (def=0x0) // Capture/compare 4 overcapture flag Refer to CC1OF description
    • [13]SBIF (def=0x0) // System break interrupt flag This flag is set by hardware as soon as the system break input goes act
    • [16]CC5IF (def=0x0) // Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as outpu
    • [17]CC6IF (def=0x0) // Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as outpu
    • [20]IDXF (def=0x0) // Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by
    • [21]DIRF (def=0x0) // Direction change interrupt flag This flag is set by hardware when the direction changes in encoder
    • [22]IERRF (def=0x0) // Index error interrupt flag This flag is set by hardware when an index error is detected. It is clea
    • [23]TERRF (def=0x0) // Transition error interrupt flag This flag is set by hardware when a transition error is detected in
  • 0x40012C14TIM1_EGR// TIM1 event generation register

    • [0]UG (def=0x0) // Update generation This bit can be set by software, it is automatically cleared by hardware.
    • [1]CC1G (def=0x0) // Capture/compare 1 generation This bit is set by software in order to generate an event, it is autom
    • [2]CC2G (def=0x0) // Capture/compare 2 generation Refer to CC1G description
    • [3]CC3G (def=0x0) // Capture/compare 3 generation Refer to CC1G description
    • [4]CC4G (def=0x0) // Capture/compare 4 generation Refer to CC1G description
    • [5]COMG (def=0x0) // Capture/compare control update generation This bit can be set by software, it is automatically clea
    • [6]TG (def=0x0) // Trigger generation This bit is set by software in order to generate an event, it is automatically c
    • [7]BG (def=0x0) // Break generation This bit is set by software in order to generate an event, it is automatically cle
    • [8]B2G (def=0x0) // Break 2 generation This bit is set by software in order to generate an event, it is automatically c
  • 0x40012C18TIM1_CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40012C18TIM1_CCMR1_Input// TIM1 capture/compare mode register 1 [alternate]

    • [0:1]CC1S (def=0x0) // Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (ti
    • [4:7]IC1F (def=0x0) // Input capture 1 filter This bit-field defines the frequency used to sample tim_ti1 input and the le
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [12:15]IC2F (def=0x0) // Input capture 2 filter
  • 0x40012C1CTIM1_CCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 4 mode - bit 3
    • [16]OC3M_3 (def=0x0) // Output compare 3 mode
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M_3_0 (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S_1_0 (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M_2_0 (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S_1_0 (def=0x0) // Capture/Compare 3 selection
  • 0x40012C1CTIM1_CCMR2_Input// TIM1 capture/compare mode register 2 [alternate]

    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [8:9]CC4S (def=0x0) // Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [12:15]IC4F (def=0x0) // Input capture 4 filter
  • 0x40012C20TIM1_CCER// TIM1 capture/compare enable register

    • [0]CC1E (def=0x0) // Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on
    • [1]CC1P (def=0x0) // Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits sel
    • [2]CC1NE (def=0x0) // Capture/compare 1 complementary output enable Note: On channels having a complementary output, this
    • [3]CC1NP (def=0x0) // Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel confi
    • [4]CC2E (def=0x0) // Capture/compare 2 output enable Refer to CC1E description
    • [5]CC2P (def=0x0) // Capture/compare 2 output polarity Refer to CC1P description
    • [6]CC2NE (def=0x0) // Capture/compare 2 complementary output enable Refer to CC1NE description
    • [7]CC2NP (def=0x0) // Capture/compare 2 complementary output polarity Refer to CC1NP description
    • [8]CC3E (def=0x0) // Capture/compare 3 output enable Refer to CC1E description
    • [9]CC3P (def=0x0) // Capture/compare 3 output polarity Refer to CC1P description
    • [10]CC3NE (def=0x0) // Capture/compare 3 complementary output enable Refer to CC1NE description
    • [11]CC3NP (def=0x0) // Capture/compare 3 complementary output polarity Refer to CC1NP description
    • [12]CC4E (def=0x0) // Capture/compare 4 output enable Refer to CC1E description
    • [13]CC4P (def=0x0) // Capture/compare 4 output polarity Refer to CC1P description
    • [14]CC4NE (def=0x0) // Capture/compare 4 complementary output enable Refer to CC1NE description
    • [15]CC4NP (def=0x0) // Capture/compare 4 complementary output polarity Refer to CC1NP description
    • [16]CC5E (def=0x0) // Capture/compare 5 output enable Refer to CC1E description
    • [17]CC5P (def=0x0) // Capture/compare 5 output polarity Refer to CC1P description
    • [20]CC6E (def=0x0) // Capture/compare 6 output enable Refer to CC1E description
    • [21]CC6P (def=0x0) // Capture/compare 6 output polarity Refer to CC1P description
  • 0x40012C24TIM1_CNT// TIM1 counter

    • [0:15]CNT (def=0x0) // Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode
    • [31]UIFCPY (def=0x0) // UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit
  • 0x40012C28TIM1_PSC// TIM1 prescaler

    • [0:15]PSC (def=0x0) // Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1)
  • 0x40012C2CTIM1_ARR// TIM1 auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the f
  • 0x40012C30TIM1_RCR// TIM1 repetition counter register

    • [0:15]REP (def=0x0) // Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e
  • 0x40012C34TIM1_CCR1// TIM1 capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in t
  • 0x40012C38TIM1_CCR2// TIM1 capture/compare register 2

    • [0:19]CCR2 (def=0x0) // Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in t
  • 0x40012C3CTIM1_CCR3// TIM1 capture/compare register 3

    • [0:19]CCR3 (def=0x0) // Capture/compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the
  • 0x40012C40TIM1_CCR4// TIM1 capture/compare register 4

    • [0:19]CCR4 (def=0x0) // Capture/compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the
  • 0x40012C44TIM1_BDTR// TIM1 break and dead-time register

    • [0:7]DTG (def=0x0) // Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the
    • [8:9]LOCK (def=0x0) // Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits
    • [10]OSSI (def=0x0) // Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software
    • [11]OSSR (def=0x0) // Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary out
    • [12]BKE (def=0x0) // Break enable This bit enables the complete break protection (including all sources connected to bk_
    • [13]BKP (def=0x0) // Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
    • [14]AOE (def=0x0) // Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been program
    • [15]MOE (def=0x0) // Main output enable This bit is cleared asynchronously by hardware as soon as one of the break input
    • [16:19]BKF (def=0x0) // Break filter This bit-field defines the frequency used to sample tim_brk input and the length of th
    • [20:23]BK2F (def=0x0) // Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of
    • [24]BK2E (def=0x0) // Break 2 enable This bit enables the complete break 2 protection (including all sources connected to
    • [25]BK2P (def=0x0) // Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOC
    • [26]BKDSRM (def=0x0) // Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be
    • [27]BK2DSRM (def=0x0) // Break2 disarm Refer to BKDSRM description
    • [28]BKBID (def=0x0) // Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured b
    • [29]BK2BID (def=0x0) // Break2 bidirectional Refer to BKBID description
  • 0x40012C48TIM1_CCR5// TIM1 capture/compare register 5

    • [0:19]CCR5 (def=0x0) // Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (pr
    • [29]GC5C1 (def=0x0) // Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate ef
    • [30]GC5C2 (def=0x0) // Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate ef
    • [31]GC5C3 (def=0x0) // Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate ef
  • 0x40012C4CTIM1_CCR6// TIM1 capture/compare register 6

    • [0:19]CCR6 (def=0x0) // Capture/compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (pr
  • 0x40012C50TIM1_CCMR3// TIM1 capture/compare mode register 3

    • [2]OC5FE (def=0x0) // Output compare 5 fast enable
    • [3]OC5PE (def=0x0) // Output compare 5 preload enable
    • [4:6]OC5M1 (def=0x0) // Output compare 5 mode
    • [7]OC5CE (def=0x0) // Output compare 5 clear enable
    • [10]OC6FE (def=0x0) // Output compare 6 fast enable
    • [11]OC6PE (def=0x0) // Output compare 6 preload enable
    • [12:14]OC6M1 (def=0x0) // Output compare 6 mode
    • [15]OC6CE (def=0x0) // Output compare 6 clear enable
    • [16]OC5M2 (def=0x0) // Output compare 5 mode
    • [24]OC6M2 (def=0x0) // Output compare 6 mode
  • 0x40012C54TIM1_DTR2// TIM1 timer deadtime register 2

    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserte
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has b
    • [17]DTPE (def=0x0) // Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
  • 0x40012C58TIM1_ECR// TIM1 timer encoder control register

    • [0]IE (def=0x0) // Index enable This bit indicates if the Index event resets the counter.
    • [1:2]IDIR (def=0x0) // Index direction This bit indicates in which direction the Index event resets the counter. Note: The
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [5]FIDX (def=0x0) // First index This bit indicates if the first index only is taken into account
    • [6:7]IPOS (def=0x0) // Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit in
    • [16:23]PW (def=0x0) // Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG
    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following:
  • 0x40012C5CTIM1_TISEL// TIM1 timer input selection register

    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input ... Refer to for interconnects list.
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input ... Refer to for interconnects list.
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input ... Refer to for interconnects list.
    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input ... Refer to for interconnects list.
  • 0x40012C60TIM1_AF1// TIM1 alternate function option register 1

    • [0]BKINE (def=0x1) // TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer’s
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer’s tim_brk input. tim_brk_c
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer’s tim_brk input. tim_brk_c
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer’s tim_brk input. tim_brk_c
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer’s tim_brk input. tim_brk_c
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer’s tim_brk input. tim_brk_c
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer’s tim_brk input. tim_brk_c
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer’s tim_brk input. tim_brk_c
    • [8]BKCMP8E (def=0x0) // tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer’s tim_brk input. tim_brk_c
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It mu
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be program
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be program
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be program
    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be program
    • [14:17]ETRSEL (def=0x0) // etr_in source selection These bits select the etr_in input source. ... Refer to for product specif
  • 0x40012C64TIM1_AF2// TIM1 alternate function register 2

    • [0]BK2INE (def=0x1) // TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerâ€�
    • [1]BK2CMP1E (def=0x0) // tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer’s tim_brk2 input. tim_br
    • [2]BK2CMP2E (def=0x0) // tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer’s tim_brk2 input. tim_br
    • [3]BK2CMP3E (def=0x0) // tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer’s tim_brk2 input. tim_br
    • [4]BK2CMP4E (def=0x0) // tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer’s tim_brk2 input. tim_br
    • [5]BK2CMP5E (def=0x0) // tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer’s tim_brk2 input. tim_br
    • [6]BK2CMP6E (def=0x0) // tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer’s tim_brk2 input. tim_br
    • [7]BK2CMP7E (def=0x0) // tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer’s tim_brk2 input. tim_br
    • [8]BK2CMP8E (def=0x0) // tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer’s tim_brk2 input. tim_br
    • [9]BK2INP (def=0x0) // TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It
    • [10]BK2CMP1P (def=0x0) // tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be progr
    • [11]BK2CMP2P (def=0x0) // tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be progr
    • [12]BK2CMP3P (def=0x0) // tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be progr
    • [13]BK2CMP4P (def=0x0) // tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be progr
    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product
  • 0x40012FDCTIM1_DCR// TIM1 DMA control register

    • [0:4]DBA (def=0x0) // DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write acc
    • [8:12]DBL (def=0x0) // DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burs
    • [16:19]DBSS (def=0x0) // DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst t
  • 0x40012FE0TIM1_DMAR// TIM1 DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses A read or write operation to the DMAR register accesses the registe
  interrupts:
  • [33] TIM1_BRK // TIM1 Break - transition error -index error
  • [34] TIM1_UP // TIM1 Update
  • [35] TIM1_TRG_COM // TIM1 Trigger and Commutation - direction change interrupt -index
  • [36] TIM1_CC // TIM1 Capture Compare interrupt
• 0x50012C00SEC_TIM1//

  • 0x50012C00TIM1_CR1// TIM1 control register 1

    • [0]CEN (def=0x0) // Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has b
    • [1]UDIS (def=0x0) // Update disable This bit is set and cleared by software to enable/disable UEV event generation. Coun
    • [2]URS (def=0x0) // Update request source This bit is set and cleared by software to select the UEV event sources. Coun
    • [3]OPM (def=0x0) // One pulse mode
    • [4]DIR (def=0x0) // Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encode
    • [5:6]CMS (def=0x0) // Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-al
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [8:9]CKD (def=0x0) // Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) fre
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [12]DITHEN (def=0x0) // Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset.
  • 0x50012C04TIM1_CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection 2
    • [20:23]MMS2 (def=0x0) // Master mode selection 2
    • [18]OIS6 (def=0x0) // Output Idle state 6
    • [16]OIS5 (def=0x0) // Output Idle state 5
    • [15]OIS4N (def=0x0) // Output Idle state 4 (OC5 output)
    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS0_2 (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x50012C08TIM1_SMCR// TIM1 slave mode control register

    • [0:2]SMS1 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [3]OCCS (def=0x0) // OCREF clear selection This bit is used to select the OCREF clear source.
    • [4:6]TS1 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [7]MSM (def=0x0) // Master/slave mode
    • [8:11]ETF (def=0x0) // External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal an
    • [12:13]ETPS (def=0x0) // External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCL
    • [14]ECE (def=0x0) // External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the sam
    • [15]ETP (def=0x0) // External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger ope
    • [16]SMS2 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [20:21]TS2 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [24]SMSPE (def=0x0) // SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded
    • [25]SMSPS (def=0x0) // SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer
  • 0x50012C0CTIM1_DIER// TIM1 DMA/interrupt enable register

    • [0]UIE (def=0x0) // Update interrupt enable
    • [1]CC1IE (def=0x0) // Capture/compare 1 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/compare 3 interrupt enable
    • [4]CC4IE (def=0x0) // Capture/compare 4 interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [9]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/compare 3 DMA request enable
    • [12]CC4DE (def=0x0) // Capture/compare 4 DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [23]TERRIE (def=0x0) // Transition error interrupt enable
  • 0x50012C10TIM1_SR// TIM1 status register

    • [0]UIF (def=0x0) // Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input cap
    • [2]CC2IF (def=0x0) // Capture/compare 2 interrupt flag Refer to CC1IF description
    • [3]CC3IF (def=0x0) // Capture/compare 3 interrupt flag Refer to CC1IF description
    • [4]CC4IF (def=0x0) // Capture/compare 4 interrupt flag Refer to CC1IF description
    • [5]COMIF (def=0x0) // COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - C
    • [6]TIF (def=0x0) // Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected
    • [7]BIF (def=0x0) // Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be
    • [8]B2IF (def=0x0) // Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It ca
    • [9]CC1OF (def=0x0) // Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag Refer to CC1OF description
    • [11]CC3OF (def=0x0) // Capture/compare 3 overcapture flag Refer to CC1OF description
    • [12]CC4OF (def=0x0) // Capture/compare 4 overcapture flag Refer to CC1OF description
    • [13]SBIF (def=0x0) // System break interrupt flag This flag is set by hardware as soon as the system break input goes act
    • [16]CC5IF (def=0x0) // Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as outpu
    • [17]CC6IF (def=0x0) // Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as outpu
    • [20]IDXF (def=0x0) // Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by
    • [21]DIRF (def=0x0) // Direction change interrupt flag This flag is set by hardware when the direction changes in encoder
    • [22]IERRF (def=0x0) // Index error interrupt flag This flag is set by hardware when an index error is detected. It is clea
    • [23]TERRF (def=0x0) // Transition error interrupt flag This flag is set by hardware when a transition error is detected in
  • 0x50012C14TIM1_EGR// TIM1 event generation register

    • [0]UG (def=0x0) // Update generation This bit can be set by software, it is automatically cleared by hardware.
    • [1]CC1G (def=0x0) // Capture/compare 1 generation This bit is set by software in order to generate an event, it is autom
    • [2]CC2G (def=0x0) // Capture/compare 2 generation Refer to CC1G description
    • [3]CC3G (def=0x0) // Capture/compare 3 generation Refer to CC1G description
    • [4]CC4G (def=0x0) // Capture/compare 4 generation Refer to CC1G description
    • [5]COMG (def=0x0) // Capture/compare control update generation This bit can be set by software, it is automatically clea
    • [6]TG (def=0x0) // Trigger generation This bit is set by software in order to generate an event, it is automatically c
    • [7]BG (def=0x0) // Break generation This bit is set by software in order to generate an event, it is automatically cle
    • [8]B2G (def=0x0) // Break 2 generation This bit is set by software in order to generate an event, it is automatically c
  • 0x50012C18TIM1_CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50012C18TIM1_CCMR1_Input// TIM1 capture/compare mode register 1 [alternate]

    • [0:1]CC1S (def=0x0) // Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (ti
    • [4:7]IC1F (def=0x0) // Input capture 1 filter This bit-field defines the frequency used to sample tim_ti1 input and the le
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [12:15]IC2F (def=0x0) // Input capture 2 filter
  • 0x50012C1CTIM1_CCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 4 mode - bit 3
    • [16]OC3M_3 (def=0x0) // Output compare 3 mode
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M_3_0 (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S_1_0 (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M_2_0 (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S_1_0 (def=0x0) // Capture/Compare 3 selection
  • 0x50012C1CTIM1_CCMR2_Input// TIM1 capture/compare mode register 2 [alternate]

    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [8:9]CC4S (def=0x0) // Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [12:15]IC4F (def=0x0) // Input capture 4 filter
  • 0x50012C20TIM1_CCER// TIM1 capture/compare enable register

    • [0]CC1E (def=0x0) // Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on
    • [1]CC1P (def=0x0) // Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits sel
    • [2]CC1NE (def=0x0) // Capture/compare 1 complementary output enable Note: On channels having a complementary output, this
    • [3]CC1NP (def=0x0) // Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel confi
    • [4]CC2E (def=0x0) // Capture/compare 2 output enable Refer to CC1E description
    • [5]CC2P (def=0x0) // Capture/compare 2 output polarity Refer to CC1P description
    • [6]CC2NE (def=0x0) // Capture/compare 2 complementary output enable Refer to CC1NE description
    • [7]CC2NP (def=0x0) // Capture/compare 2 complementary output polarity Refer to CC1NP description
    • [8]CC3E (def=0x0) // Capture/compare 3 output enable Refer to CC1E description
    • [9]CC3P (def=0x0) // Capture/compare 3 output polarity Refer to CC1P description
    • [10]CC3NE (def=0x0) // Capture/compare 3 complementary output enable Refer to CC1NE description
    • [11]CC3NP (def=0x0) // Capture/compare 3 complementary output polarity Refer to CC1NP description
    • [12]CC4E (def=0x0) // Capture/compare 4 output enable Refer to CC1E description
    • [13]CC4P (def=0x0) // Capture/compare 4 output polarity Refer to CC1P description
    • [14]CC4NE (def=0x0) // Capture/compare 4 complementary output enable Refer to CC1NE description
    • [15]CC4NP (def=0x0) // Capture/compare 4 complementary output polarity Refer to CC1NP description
    • [16]CC5E (def=0x0) // Capture/compare 5 output enable Refer to CC1E description
    • [17]CC5P (def=0x0) // Capture/compare 5 output polarity Refer to CC1P description
    • [20]CC6E (def=0x0) // Capture/compare 6 output enable Refer to CC1E description
    • [21]CC6P (def=0x0) // Capture/compare 6 output polarity Refer to CC1P description
  • 0x50012C24TIM1_CNT// TIM1 counter

    • [0:15]CNT (def=0x0) // Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode
    • [31]UIFCPY (def=0x0) // UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit
  • 0x50012C28TIM1_PSC// TIM1 prescaler

    • [0:15]PSC (def=0x0) // Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1)
  • 0x50012C2CTIM1_ARR// TIM1 auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the f
  • 0x50012C30TIM1_RCR// TIM1 repetition counter register

    • [0:15]REP (def=0x0) // Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e
  • 0x50012C34TIM1_CCR1// TIM1 capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in t
  • 0x50012C38TIM1_CCR2// TIM1 capture/compare register 2

    • [0:19]CCR2 (def=0x0) // Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in t
  • 0x50012C3CTIM1_CCR3// TIM1 capture/compare register 3

    • [0:19]CCR3 (def=0x0) // Capture/compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the
  • 0x50012C40TIM1_CCR4// TIM1 capture/compare register 4

    • [0:19]CCR4 (def=0x0) // Capture/compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the
  • 0x50012C44TIM1_BDTR// TIM1 break and dead-time register

    • [0:7]DTG (def=0x0) // Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the
    • [8:9]LOCK (def=0x0) // Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits
    • [10]OSSI (def=0x0) // Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software
    • [11]OSSR (def=0x0) // Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary out
    • [12]BKE (def=0x0) // Break enable This bit enables the complete break protection (including all sources connected to bk_
    • [13]BKP (def=0x0) // Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
    • [14]AOE (def=0x0) // Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been program
    • [15]MOE (def=0x0) // Main output enable This bit is cleared asynchronously by hardware as soon as one of the break input
    • [16:19]BKF (def=0x0) // Break filter This bit-field defines the frequency used to sample tim_brk input and the length of th
    • [20:23]BK2F (def=0x0) // Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of
    • [24]BK2E (def=0x0) // Break 2 enable This bit enables the complete break 2 protection (including all sources connected to
    • [25]BK2P (def=0x0) // Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOC
    • [26]BKDSRM (def=0x0) // Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be
    • [27]BK2DSRM (def=0x0) // Break2 disarm Refer to BKDSRM description
    • [28]BKBID (def=0x0) // Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured b
    • [29]BK2BID (def=0x0) // Break2 bidirectional Refer to BKBID description
  • 0x50012C48TIM1_CCR5// TIM1 capture/compare register 5

    • [0:19]CCR5 (def=0x0) // Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (pr
    • [29]GC5C1 (def=0x0) // Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate ef
    • [30]GC5C2 (def=0x0) // Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate ef
    • [31]GC5C3 (def=0x0) // Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate ef
  • 0x50012C4CTIM1_CCR6// TIM1 capture/compare register 6

    • [0:19]CCR6 (def=0x0) // Capture/compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (pr
  • 0x50012C50TIM1_CCMR3// TIM1 capture/compare mode register 3

    • [2]OC5FE (def=0x0) // Output compare 5 fast enable
    • [3]OC5PE (def=0x0) // Output compare 5 preload enable
    • [4:6]OC5M1 (def=0x0) // Output compare 5 mode
    • [7]OC5CE (def=0x0) // Output compare 5 clear enable
    • [10]OC6FE (def=0x0) // Output compare 6 fast enable
    • [11]OC6PE (def=0x0) // Output compare 6 preload enable
    • [12:14]OC6M1 (def=0x0) // Output compare 6 mode
    • [15]OC6CE (def=0x0) // Output compare 6 clear enable
    • [16]OC5M2 (def=0x0) // Output compare 5 mode
    • [24]OC6M2 (def=0x0) // Output compare 6 mode
  • 0x50012C54TIM1_DTR2// TIM1 timer deadtime register 2

    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserte
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has b
    • [17]DTPE (def=0x0) // Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
  • 0x50012C58TIM1_ECR// TIM1 timer encoder control register

    • [0]IE (def=0x0) // Index enable This bit indicates if the Index event resets the counter.
    • [1:2]IDIR (def=0x0) // Index direction This bit indicates in which direction the Index event resets the counter. Note: The
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [5]FIDX (def=0x0) // First index This bit indicates if the first index only is taken into account
    • [6:7]IPOS (def=0x0) // Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit in
    • [16:23]PW (def=0x0) // Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG
    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following:
  • 0x50012C5CTIM1_TISEL// TIM1 timer input selection register

    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input ... Refer to for interconnects list.
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input ... Refer to for interconnects list.
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input ... Refer to for interconnects list.
    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input ... Refer to for interconnects list.
  • 0x50012C60TIM1_AF1// TIM1 alternate function option register 1

    • [0]BKINE (def=0x1) // TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer’s
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer’s tim_brk input. tim_brk_c
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer’s tim_brk input. tim_brk_c
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer’s tim_brk input. tim_brk_c
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer’s tim_brk input. tim_brk_c
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer’s tim_brk input. tim_brk_c
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer’s tim_brk input. tim_brk_c
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer’s tim_brk input. tim_brk_c
    • [8]BKCMP8E (def=0x0) // tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer’s tim_brk input. tim_brk_c
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It mu
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be program
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be program
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be program
    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be program
    • [14:17]ETRSEL (def=0x0) // etr_in source selection These bits select the etr_in input source. ... Refer to for product specif
  • 0x50012C64TIM1_AF2// TIM1 alternate function register 2

    • [0]BK2INE (def=0x1) // TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerâ€�
    • [1]BK2CMP1E (def=0x0) // tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer’s tim_brk2 input. tim_br
    • [2]BK2CMP2E (def=0x0) // tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer’s tim_brk2 input. tim_br
    • [3]BK2CMP3E (def=0x0) // tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer’s tim_brk2 input. tim_br
    • [4]BK2CMP4E (def=0x0) // tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer’s tim_brk2 input. tim_br
    • [5]BK2CMP5E (def=0x0) // tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer’s tim_brk2 input. tim_br
    • [6]BK2CMP6E (def=0x0) // tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer’s tim_brk2 input. tim_br
    • [7]BK2CMP7E (def=0x0) // tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer’s tim_brk2 input. tim_br
    • [8]BK2CMP8E (def=0x0) // tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer’s tim_brk2 input. tim_br
    • [9]BK2INP (def=0x0) // TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It
    • [10]BK2CMP1P (def=0x0) // tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be progr
    • [11]BK2CMP2P (def=0x0) // tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be progr
    • [12]BK2CMP3P (def=0x0) // tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be progr
    • [13]BK2CMP4P (def=0x0) // tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be progr
    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product
  • 0x50012FDCTIM1_DCR// TIM1 DMA control register

    • [0:4]DBA (def=0x0) // DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write acc
    • [8:12]DBL (def=0x0) // DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burs
    • [16:19]DBSS (def=0x0) // DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst t
  • 0x50012FE0TIM1_DMAR// TIM1 DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses A read or write operation to the DMAR register accesses the registe
• 0x40013400TIM8//

  • 0x40013400TIM1_CR1// TIM1 control register 1

    • [0]CEN (def=0x0) // Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has b
    • [1]UDIS (def=0x0) // Update disable This bit is set and cleared by software to enable/disable UEV event generation. Coun
    • [2]URS (def=0x0) // Update request source This bit is set and cleared by software to select the UEV event sources. Coun
    • [3]OPM (def=0x0) // One pulse mode
    • [4]DIR (def=0x0) // Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encode
    • [5:6]CMS (def=0x0) // Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-al
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [8:9]CKD (def=0x0) // Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) fre
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [12]DITHEN (def=0x0) // Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset.
  • 0x40013404TIM1_CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection 2
    • [20:23]MMS2 (def=0x0) // Master mode selection 2
    • [18]OIS6 (def=0x0) // Output Idle state 6
    • [16]OIS5 (def=0x0) // Output Idle state 5
    • [15]OIS4N (def=0x0) // Output Idle state 4 (OC5 output)
    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS0_2 (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40013408TIM1_SMCR// TIM1 slave mode control register

    • [0:2]SMS1 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [3]OCCS (def=0x0) // OCREF clear selection This bit is used to select the OCREF clear source.
    • [4:6]TS1 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [7]MSM (def=0x0) // Master/slave mode
    • [8:11]ETF (def=0x0) // External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal an
    • [12:13]ETPS (def=0x0) // External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCL
    • [14]ECE (def=0x0) // External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the sam
    • [15]ETP (def=0x0) // External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger ope
    • [16]SMS2 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [20:21]TS2 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [24]SMSPE (def=0x0) // SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded
    • [25]SMSPS (def=0x0) // SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer
  • 0x4001340CTIM1_DIER// TIM1 DMA/interrupt enable register

    • [0]UIE (def=0x0) // Update interrupt enable
    • [1]CC1IE (def=0x0) // Capture/compare 1 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/compare 3 interrupt enable
    • [4]CC4IE (def=0x0) // Capture/compare 4 interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [9]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/compare 3 DMA request enable
    • [12]CC4DE (def=0x0) // Capture/compare 4 DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [23]TERRIE (def=0x0) // Transition error interrupt enable
  • 0x40013410TIM1_SR// TIM1 status register

    • [0]UIF (def=0x0) // Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input cap
    • [2]CC2IF (def=0x0) // Capture/compare 2 interrupt flag Refer to CC1IF description
    • [3]CC3IF (def=0x0) // Capture/compare 3 interrupt flag Refer to CC1IF description
    • [4]CC4IF (def=0x0) // Capture/compare 4 interrupt flag Refer to CC1IF description
    • [5]COMIF (def=0x0) // COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - C
    • [6]TIF (def=0x0) // Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected
    • [7]BIF (def=0x0) // Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be
    • [8]B2IF (def=0x0) // Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It ca
    • [9]CC1OF (def=0x0) // Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag Refer to CC1OF description
    • [11]CC3OF (def=0x0) // Capture/compare 3 overcapture flag Refer to CC1OF description
    • [12]CC4OF (def=0x0) // Capture/compare 4 overcapture flag Refer to CC1OF description
    • [13]SBIF (def=0x0) // System break interrupt flag This flag is set by hardware as soon as the system break input goes act
    • [16]CC5IF (def=0x0) // Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as outpu
    • [17]CC6IF (def=0x0) // Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as outpu
    • [20]IDXF (def=0x0) // Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by
    • [21]DIRF (def=0x0) // Direction change interrupt flag This flag is set by hardware when the direction changes in encoder
    • [22]IERRF (def=0x0) // Index error interrupt flag This flag is set by hardware when an index error is detected. It is clea
    • [23]TERRF (def=0x0) // Transition error interrupt flag This flag is set by hardware when a transition error is detected in
  • 0x40013414TIM1_EGR// TIM1 event generation register

    • [0]UG (def=0x0) // Update generation This bit can be set by software, it is automatically cleared by hardware.
    • [1]CC1G (def=0x0) // Capture/compare 1 generation This bit is set by software in order to generate an event, it is autom
    • [2]CC2G (def=0x0) // Capture/compare 2 generation Refer to CC1G description
    • [3]CC3G (def=0x0) // Capture/compare 3 generation Refer to CC1G description
    • [4]CC4G (def=0x0) // Capture/compare 4 generation Refer to CC1G description
    • [5]COMG (def=0x0) // Capture/compare control update generation This bit can be set by software, it is automatically clea
    • [6]TG (def=0x0) // Trigger generation This bit is set by software in order to generate an event, it is automatically c
    • [7]BG (def=0x0) // Break generation This bit is set by software in order to generate an event, it is automatically cle
    • [8]B2G (def=0x0) // Break 2 generation This bit is set by software in order to generate an event, it is automatically c
  • 0x40013418TIM1_CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40013418TIM1_CCMR1_Input// TIM1 capture/compare mode register 1 [alternate]

    • [0:1]CC1S (def=0x0) // Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (ti
    • [4:7]IC1F (def=0x0) // Input capture 1 filter This bit-field defines the frequency used to sample tim_ti1 input and the le
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [12:15]IC2F (def=0x0) // Input capture 2 filter
  • 0x4001341CTIM1_CCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 4 mode - bit 3
    • [16]OC3M_3 (def=0x0) // Output compare 3 mode
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M_3_0 (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S_1_0 (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M_2_0 (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S_1_0 (def=0x0) // Capture/Compare 3 selection
  • 0x4001341CTIM1_CCMR2_Input// TIM1 capture/compare mode register 2 [alternate]

    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [8:9]CC4S (def=0x0) // Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [12:15]IC4F (def=0x0) // Input capture 4 filter
  • 0x40013420TIM1_CCER// TIM1 capture/compare enable register

    • [0]CC1E (def=0x0) // Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on
    • [1]CC1P (def=0x0) // Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits sel
    • [2]CC1NE (def=0x0) // Capture/compare 1 complementary output enable Note: On channels having a complementary output, this
    • [3]CC1NP (def=0x0) // Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel confi
    • [4]CC2E (def=0x0) // Capture/compare 2 output enable Refer to CC1E description
    • [5]CC2P (def=0x0) // Capture/compare 2 output polarity Refer to CC1P description
    • [6]CC2NE (def=0x0) // Capture/compare 2 complementary output enable Refer to CC1NE description
    • [7]CC2NP (def=0x0) // Capture/compare 2 complementary output polarity Refer to CC1NP description
    • [8]CC3E (def=0x0) // Capture/compare 3 output enable Refer to CC1E description
    • [9]CC3P (def=0x0) // Capture/compare 3 output polarity Refer to CC1P description
    • [10]CC3NE (def=0x0) // Capture/compare 3 complementary output enable Refer to CC1NE description
    • [11]CC3NP (def=0x0) // Capture/compare 3 complementary output polarity Refer to CC1NP description
    • [12]CC4E (def=0x0) // Capture/compare 4 output enable Refer to CC1E description
    • [13]CC4P (def=0x0) // Capture/compare 4 output polarity Refer to CC1P description
    • [14]CC4NE (def=0x0) // Capture/compare 4 complementary output enable Refer to CC1NE description
    • [15]CC4NP (def=0x0) // Capture/compare 4 complementary output polarity Refer to CC1NP description
    • [16]CC5E (def=0x0) // Capture/compare 5 output enable Refer to CC1E description
    • [17]CC5P (def=0x0) // Capture/compare 5 output polarity Refer to CC1P description
    • [20]CC6E (def=0x0) // Capture/compare 6 output enable Refer to CC1E description
    • [21]CC6P (def=0x0) // Capture/compare 6 output polarity Refer to CC1P description
  • 0x40013424TIM1_CNT// TIM1 counter

    • [0:15]CNT (def=0x0) // Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode
    • [31]UIFCPY (def=0x0) // UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit
  • 0x40013428TIM1_PSC// TIM1 prescaler

    • [0:15]PSC (def=0x0) // Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1)
  • 0x4001342CTIM1_ARR// TIM1 auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the f
  • 0x40013430TIM1_RCR// TIM1 repetition counter register

    • [0:15]REP (def=0x0) // Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e
  • 0x40013434TIM1_CCR1// TIM1 capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in t
  • 0x40013438TIM1_CCR2// TIM1 capture/compare register 2

    • [0:19]CCR2 (def=0x0) // Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in t
  • 0x4001343CTIM1_CCR3// TIM1 capture/compare register 3

    • [0:19]CCR3 (def=0x0) // Capture/compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the
  • 0x40013440TIM1_CCR4// TIM1 capture/compare register 4

    • [0:19]CCR4 (def=0x0) // Capture/compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the
  • 0x40013444TIM1_BDTR// TIM1 break and dead-time register

    • [0:7]DTG (def=0x0) // Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the
    • [8:9]LOCK (def=0x0) // Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits
    • [10]OSSI (def=0x0) // Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software
    • [11]OSSR (def=0x0) // Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary out
    • [12]BKE (def=0x0) // Break enable This bit enables the complete break protection (including all sources connected to bk_
    • [13]BKP (def=0x0) // Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
    • [14]AOE (def=0x0) // Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been program
    • [15]MOE (def=0x0) // Main output enable This bit is cleared asynchronously by hardware as soon as one of the break input
    • [16:19]BKF (def=0x0) // Break filter This bit-field defines the frequency used to sample tim_brk input and the length of th
    • [20:23]BK2F (def=0x0) // Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of
    • [24]BK2E (def=0x0) // Break 2 enable This bit enables the complete break 2 protection (including all sources connected to
    • [25]BK2P (def=0x0) // Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOC
    • [26]BKDSRM (def=0x0) // Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be
    • [27]BK2DSRM (def=0x0) // Break2 disarm Refer to BKDSRM description
    • [28]BKBID (def=0x0) // Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured b
    • [29]BK2BID (def=0x0) // Break2 bidirectional Refer to BKBID description
  • 0x40013448TIM1_CCR5// TIM1 capture/compare register 5

    • [0:19]CCR5 (def=0x0) // Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (pr
    • [29]GC5C1 (def=0x0) // Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate ef
    • [30]GC5C2 (def=0x0) // Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate ef
    • [31]GC5C3 (def=0x0) // Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate ef
  • 0x4001344CTIM1_CCR6// TIM1 capture/compare register 6

    • [0:19]CCR6 (def=0x0) // Capture/compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (pr
  • 0x40013450TIM1_CCMR3// TIM1 capture/compare mode register 3

    • [2]OC5FE (def=0x0) // Output compare 5 fast enable
    • [3]OC5PE (def=0x0) // Output compare 5 preload enable
    • [4:6]OC5M1 (def=0x0) // Output compare 5 mode
    • [7]OC5CE (def=0x0) // Output compare 5 clear enable
    • [10]OC6FE (def=0x0) // Output compare 6 fast enable
    • [11]OC6PE (def=0x0) // Output compare 6 preload enable
    • [12:14]OC6M1 (def=0x0) // Output compare 6 mode
    • [15]OC6CE (def=0x0) // Output compare 6 clear enable
    • [16]OC5M2 (def=0x0) // Output compare 5 mode
    • [24]OC6M2 (def=0x0) // Output compare 6 mode
  • 0x40013454TIM1_DTR2// TIM1 timer deadtime register 2

    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserte
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has b
    • [17]DTPE (def=0x0) // Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
  • 0x40013458TIM1_ECR// TIM1 timer encoder control register

    • [0]IE (def=0x0) // Index enable This bit indicates if the Index event resets the counter.
    • [1:2]IDIR (def=0x0) // Index direction This bit indicates in which direction the Index event resets the counter. Note: The
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [5]FIDX (def=0x0) // First index This bit indicates if the first index only is taken into account
    • [6:7]IPOS (def=0x0) // Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit in
    • [16:23]PW (def=0x0) // Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG
    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following:
  • 0x4001345CTIM1_TISEL// TIM1 timer input selection register

    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input ... Refer to for interconnects list.
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input ... Refer to for interconnects list.
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input ... Refer to for interconnects list.
    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input ... Refer to for interconnects list.
  • 0x40013460TIM1_AF1// TIM1 alternate function option register 1

    • [0]BKINE (def=0x1) // TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer’s
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer’s tim_brk input. tim_brk_c
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer’s tim_brk input. tim_brk_c
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer’s tim_brk input. tim_brk_c
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer’s tim_brk input. tim_brk_c
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer’s tim_brk input. tim_brk_c
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer’s tim_brk input. tim_brk_c
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer’s tim_brk input. tim_brk_c
    • [8]BKCMP8E (def=0x0) // tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer’s tim_brk input. tim_brk_c
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It mu
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be program
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be program
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be program
    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be program
    • [14:17]ETRSEL (def=0x0) // etr_in source selection These bits select the etr_in input source. ... Refer to for product specif
  • 0x40013464TIM1_AF2// TIM1 alternate function register 2

    • [0]BK2INE (def=0x1) // TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerâ€�
    • [1]BK2CMP1E (def=0x0) // tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer’s tim_brk2 input. tim_br
    • [2]BK2CMP2E (def=0x0) // tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer’s tim_brk2 input. tim_br
    • [3]BK2CMP3E (def=0x0) // tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer’s tim_brk2 input. tim_br
    • [4]BK2CMP4E (def=0x0) // tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer’s tim_brk2 input. tim_br
    • [5]BK2CMP5E (def=0x0) // tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer’s tim_brk2 input. tim_br
    • [6]BK2CMP6E (def=0x0) // tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer’s tim_brk2 input. tim_br
    • [7]BK2CMP7E (def=0x0) // tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer’s tim_brk2 input. tim_br
    • [8]BK2CMP8E (def=0x0) // tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer’s tim_brk2 input. tim_br
    • [9]BK2INP (def=0x0) // TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It
    • [10]BK2CMP1P (def=0x0) // tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be progr
    • [11]BK2CMP2P (def=0x0) // tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be progr
    • [12]BK2CMP3P (def=0x0) // tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be progr
    • [13]BK2CMP4P (def=0x0) // tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be progr
    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product
  • 0x400137DCTIM1_DCR// TIM1 DMA control register

    • [0:4]DBA (def=0x0) // DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write acc
    • [8:12]DBL (def=0x0) // DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burs
    • [16:19]DBSS (def=0x0) // DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst t
  • 0x400137E0TIM1_DMAR// TIM1 DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses A read or write operation to the DMAR register accesses the registe
  interrupts:
  • [41] TIM8_BRK // TIM8 Break Interrupt
  • [42] TIM8_UP // TIM8 Update Interrupt
  • [43] TIM8_TRG_COM // TIM8 Trigger and Commutation Interrupt
  • [44] TIM8_CC // TIM8 Capture Compare Interrupt
• 0x50013400SEC_TIM8//

  • 0x50013400TIM1_CR1// TIM1 control register 1

    • [0]CEN (def=0x0) // Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has b
    • [1]UDIS (def=0x0) // Update disable This bit is set and cleared by software to enable/disable UEV event generation. Coun
    • [2]URS (def=0x0) // Update request source This bit is set and cleared by software to select the UEV event sources. Coun
    • [3]OPM (def=0x0) // One pulse mode
    • [4]DIR (def=0x0) // Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encode
    • [5:6]CMS (def=0x0) // Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-al
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [8:9]CKD (def=0x0) // Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) fre
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [12]DITHEN (def=0x0) // Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset.
  • 0x50013404TIM1_CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection 2
    • [20:23]MMS2 (def=0x0) // Master mode selection 2
    • [18]OIS6 (def=0x0) // Output Idle state 6
    • [16]OIS5 (def=0x0) // Output Idle state 5
    • [15]OIS4N (def=0x0) // Output Idle state 4 (OC5 output)
    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS0_2 (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x50013408TIM1_SMCR// TIM1 slave mode control register

    • [0:2]SMS1 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [3]OCCS (def=0x0) // OCREF clear selection This bit is used to select the OCREF clear source.
    • [4:6]TS1 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [7]MSM (def=0x0) // Master/slave mode
    • [8:11]ETF (def=0x0) // External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal an
    • [12:13]ETPS (def=0x0) // External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCL
    • [14]ECE (def=0x0) // External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the sam
    • [15]ETP (def=0x0) // External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger ope
    • [16]SMS2 (def=0x0) // Slave mode selection When external signals are selected the active edge of the trigger signal (tim_
    • [20:21]TS2 (def=0x0) // Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bit
    • [24]SMSPE (def=0x0) // SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded
    • [25]SMSPS (def=0x0) // SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer
  • 0x5001340CTIM1_DIER// TIM1 DMA/interrupt enable register

    • [0]UIE (def=0x0) // Update interrupt enable
    • [1]CC1IE (def=0x0) // Capture/compare 1 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/compare 2 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/compare 3 interrupt enable
    • [4]CC4IE (def=0x0) // Capture/compare 4 interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [9]CC1DE (def=0x0) // Capture/compare 1 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/compare 2 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/compare 3 DMA request enable
    • [12]CC4DE (def=0x0) // Capture/compare 4 DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [23]TERRIE (def=0x0) // Transition error interrupt enable
  • 0x50013410TIM1_SR// TIM1 status register

    • [0]UIF (def=0x0) // Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input cap
    • [2]CC2IF (def=0x0) // Capture/compare 2 interrupt flag Refer to CC1IF description
    • [3]CC3IF (def=0x0) // Capture/compare 3 interrupt flag Refer to CC1IF description
    • [4]CC4IF (def=0x0) // Capture/compare 4 interrupt flag Refer to CC1IF description
    • [5]COMIF (def=0x0) // COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - C
    • [6]TIF (def=0x0) // Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected
    • [7]BIF (def=0x0) // Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be
    • [8]B2IF (def=0x0) // Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It ca
    • [9]CC1OF (def=0x0) // Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag Refer to CC1OF description
    • [11]CC3OF (def=0x0) // Capture/compare 3 overcapture flag Refer to CC1OF description
    • [12]CC4OF (def=0x0) // Capture/compare 4 overcapture flag Refer to CC1OF description
    • [13]SBIF (def=0x0) // System break interrupt flag This flag is set by hardware as soon as the system break input goes act
    • [16]CC5IF (def=0x0) // Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as outpu
    • [17]CC6IF (def=0x0) // Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as outpu
    • [20]IDXF (def=0x0) // Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by
    • [21]DIRF (def=0x0) // Direction change interrupt flag This flag is set by hardware when the direction changes in encoder
    • [22]IERRF (def=0x0) // Index error interrupt flag This flag is set by hardware when an index error is detected. It is clea
    • [23]TERRF (def=0x0) // Transition error interrupt flag This flag is set by hardware when a transition error is detected in
  • 0x50013414TIM1_EGR// TIM1 event generation register

    • [0]UG (def=0x0) // Update generation This bit can be set by software, it is automatically cleared by hardware.
    • [1]CC1G (def=0x0) // Capture/compare 1 generation This bit is set by software in order to generate an event, it is autom
    • [2]CC2G (def=0x0) // Capture/compare 2 generation Refer to CC1G description
    • [3]CC3G (def=0x0) // Capture/compare 3 generation Refer to CC1G description
    • [4]CC4G (def=0x0) // Capture/compare 4 generation Refer to CC1G description
    • [5]COMG (def=0x0) // Capture/compare control update generation This bit can be set by software, it is automatically clea
    • [6]TG (def=0x0) // Trigger generation This bit is set by software in order to generate an event, it is automatically c
    • [7]BG (def=0x0) // Break generation This bit is set by software in order to generate an event, it is automatically cle
    • [8]B2G (def=0x0) // Break 2 generation This bit is set by software in order to generate an event, it is automatically c
  • 0x50013418TIM1_CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50013418TIM1_CCMR1_Input// TIM1 capture/compare mode register 1 [alternate]

    • [0:1]CC1S (def=0x0) // Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (ti
    • [4:7]IC1F (def=0x0) // Input capture 1 filter This bit-field defines the frequency used to sample tim_ti1 input and the le
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [12:15]IC2F (def=0x0) // Input capture 2 filter
  • 0x5001341CTIM1_CCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 4 mode - bit 3
    • [16]OC3M_3 (def=0x0) // Output compare 3 mode
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M_3_0 (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S_1_0 (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M_2_0 (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S_1_0 (def=0x0) // Capture/Compare 3 selection
  • 0x5001341CTIM1_CCMR2_Input// TIM1 capture/compare mode register 2 [alternate]

    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as w
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [8:9]CC4S (def=0x0) // Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as w
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [12:15]IC4F (def=0x0) // Input capture 4 filter
  • 0x50013420TIM1_CCER// TIM1 capture/compare enable register

    • [0]CC1E (def=0x0) // Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on
    • [1]CC1P (def=0x0) // Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits sel
    • [2]CC1NE (def=0x0) // Capture/compare 1 complementary output enable Note: On channels having a complementary output, this
    • [3]CC1NP (def=0x0) // Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel confi
    • [4]CC2E (def=0x0) // Capture/compare 2 output enable Refer to CC1E description
    • [5]CC2P (def=0x0) // Capture/compare 2 output polarity Refer to CC1P description
    • [6]CC2NE (def=0x0) // Capture/compare 2 complementary output enable Refer to CC1NE description
    • [7]CC2NP (def=0x0) // Capture/compare 2 complementary output polarity Refer to CC1NP description
    • [8]CC3E (def=0x0) // Capture/compare 3 output enable Refer to CC1E description
    • [9]CC3P (def=0x0) // Capture/compare 3 output polarity Refer to CC1P description
    • [10]CC3NE (def=0x0) // Capture/compare 3 complementary output enable Refer to CC1NE description
    • [11]CC3NP (def=0x0) // Capture/compare 3 complementary output polarity Refer to CC1NP description
    • [12]CC4E (def=0x0) // Capture/compare 4 output enable Refer to CC1E description
    • [13]CC4P (def=0x0) // Capture/compare 4 output polarity Refer to CC1P description
    • [14]CC4NE (def=0x0) // Capture/compare 4 complementary output enable Refer to CC1NE description
    • [15]CC4NP (def=0x0) // Capture/compare 4 complementary output polarity Refer to CC1NP description
    • [16]CC5E (def=0x0) // Capture/compare 5 output enable Refer to CC1E description
    • [17]CC5P (def=0x0) // Capture/compare 5 output polarity Refer to CC1P description
    • [20]CC6E (def=0x0) // Capture/compare 6 output enable Refer to CC1E description
    • [21]CC6P (def=0x0) // Capture/compare 6 output polarity Refer to CC1P description
  • 0x50013424TIM1_CNT// TIM1 counter

    • [0:15]CNT (def=0x0) // Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode
    • [31]UIFCPY (def=0x0) // UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit
  • 0x50013428TIM1_PSC// TIM1 prescaler

    • [0:15]PSC (def=0x0) // Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1)
  • 0x5001342CTIM1_ARR// TIM1 auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the f
  • 0x50013430TIM1_RCR// TIM1 repetition counter register

    • [0:15]REP (def=0x0) // Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e
  • 0x50013434TIM1_CCR1// TIM1 capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in t
  • 0x50013438TIM1_CCR2// TIM1 capture/compare register 2

    • [0:19]CCR2 (def=0x0) // Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in t
  • 0x5001343CTIM1_CCR3// TIM1 capture/compare register 3

    • [0:19]CCR3 (def=0x0) // Capture/compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the
  • 0x50013440TIM1_CCR4// TIM1 capture/compare register 4

    • [0:19]CCR4 (def=0x0) // Capture/compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the
  • 0x50013444TIM1_BDTR// TIM1 break and dead-time register

    • [0:7]DTG (def=0x0) // Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the
    • [8:9]LOCK (def=0x0) // Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits
    • [10]OSSI (def=0x0) // Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software
    • [11]OSSR (def=0x0) // Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary out
    • [12]BKE (def=0x0) // Break enable This bit enables the complete break protection (including all sources connected to bk_
    • [13]BKP (def=0x0) // Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
    • [14]AOE (def=0x0) // Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been program
    • [15]MOE (def=0x0) // Main output enable This bit is cleared asynchronously by hardware as soon as one of the break input
    • [16:19]BKF (def=0x0) // Break filter This bit-field defines the frequency used to sample tim_brk input and the length of th
    • [20:23]BK2F (def=0x0) // Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of
    • [24]BK2E (def=0x0) // Break 2 enable This bit enables the complete break 2 protection (including all sources connected to
    • [25]BK2P (def=0x0) // Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOC
    • [26]BKDSRM (def=0x0) // Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be
    • [27]BK2DSRM (def=0x0) // Break2 disarm Refer to BKDSRM description
    • [28]BKBID (def=0x0) // Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured b
    • [29]BK2BID (def=0x0) // Break2 bidirectional Refer to BKBID description
  • 0x50013448TIM1_CCR5// TIM1 capture/compare register 5

    • [0:19]CCR5 (def=0x0) // Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (pr
    • [29]GC5C1 (def=0x0) // Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate ef
    • [30]GC5C2 (def=0x0) // Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate ef
    • [31]GC5C3 (def=0x0) // Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate ef
  • 0x5001344CTIM1_CCR6// TIM1 capture/compare register 6

    • [0:19]CCR6 (def=0x0) // Capture/compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (pr
  • 0x50013450TIM1_CCMR3// TIM1 capture/compare mode register 3

    • [2]OC5FE (def=0x0) // Output compare 5 fast enable
    • [3]OC5PE (def=0x0) // Output compare 5 preload enable
    • [4:6]OC5M1 (def=0x0) // Output compare 5 mode
    • [7]OC5CE (def=0x0) // Output compare 5 clear enable
    • [10]OC6FE (def=0x0) // Output compare 6 fast enable
    • [11]OC6PE (def=0x0) // Output compare 6 preload enable
    • [12:14]OC6M1 (def=0x0) // Output compare 6 mode
    • [15]OC6CE (def=0x0) // Output compare 6 clear enable
    • [16]OC5M2 (def=0x0) // Output compare 5 mode
    • [24]OC6M2 (def=0x0) // Output compare 6 mode
  • 0x50013454TIM1_DTR2// TIM1 timer deadtime register 2

    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserte
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has b
    • [17]DTPE (def=0x0) // Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
  • 0x50013458TIM1_ECR// TIM1 timer encoder control register

    • [0]IE (def=0x0) // Index enable This bit indicates if the Index event resets the counter.
    • [1:2]IDIR (def=0x0) // Index direction This bit indicates in which direction the Index event resets the counter. Note: The
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [5]FIDX (def=0x0) // First index This bit indicates if the first index only is taken into account
    • [6:7]IPOS (def=0x0) // Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit in
    • [16:23]PW (def=0x0) // Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG
    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following:
  • 0x5001345CTIM1_TISEL// TIM1 timer input selection register

    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input ... Refer to for interconnects list.
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input ... Refer to for interconnects list.
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input ... Refer to for interconnects list.
    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input ... Refer to for interconnects list.
  • 0x50013460TIM1_AF1// TIM1 alternate function option register 1

    • [0]BKINE (def=0x1) // TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timer’s
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timer’s tim_brk input. tim_brk_c
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timer’s tim_brk input. tim_brk_c
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timer’s tim_brk input. tim_brk_c
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timer’s tim_brk input. tim_brk_c
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timer’s tim_brk input. tim_brk_c
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timer’s tim_brk input. tim_brk_c
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timer’s tim_brk input. tim_brk_c
    • [8]BKCMP8E (def=0x0) // tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timer’s tim_brk input. tim_brk_c
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It mu
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be program
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be program
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be program
    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be program
    • [14:17]ETRSEL (def=0x0) // etr_in source selection These bits select the etr_in input source. ... Refer to for product specif
  • 0x50013464TIM1_AF2// TIM1 alternate function register 2

    • [0]BK2INE (def=0x1) // TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerâ€�
    • [1]BK2CMP1E (def=0x0) // tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer’s tim_brk2 input. tim_br
    • [2]BK2CMP2E (def=0x0) // tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer’s tim_brk2 input. tim_br
    • [3]BK2CMP3E (def=0x0) // tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer’s tim_brk2 input. tim_br
    • [4]BK2CMP4E (def=0x0) // tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer’s tim_brk2 input. tim_br
    • [5]BK2CMP5E (def=0x0) // tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer’s tim_brk2 input. tim_br
    • [6]BK2CMP6E (def=0x0) // tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer’s tim_brk2 input. tim_br
    • [7]BK2CMP7E (def=0x0) // tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer’s tim_brk2 input. tim_br
    • [8]BK2CMP8E (def=0x0) // tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer’s tim_brk2 input. tim_br
    • [9]BK2INP (def=0x0) // TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It
    • [10]BK2CMP1P (def=0x0) // tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be progr
    • [11]BK2CMP2P (def=0x0) // tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be progr
    • [12]BK2CMP3P (def=0x0) // tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be progr
    • [13]BK2CMP4P (def=0x0) // tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be progr
    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product
  • 0x500137DCTIM1_DCR// TIM1 DMA control register

    • [0:4]DBA (def=0x0) // DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write acc
    • [8:12]DBL (def=0x0) // DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burs
    • [16:19]DBSS (def=0x0) // DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst t
  • 0x500137E0TIM1_DMAR// TIM1 DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses A read or write operation to the DMAR register accesses the registe
• 0x40000000TIM2// General-purpose-timers

  • 0x40000000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000004CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000008SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000000CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000010SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000014EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000018CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000018CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000001CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000001CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000020CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000024CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x40000028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000002CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x40000034CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x40000038CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x4000003CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x40000040CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x40000058ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x4000005CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x40000060AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x40000064AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x400003DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x400003E0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
  interrupts:
  • [37] TIM2 // TIM2 global interrupt
• 0x50000000SEC_TIM2//

  • 0x50000000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50000004CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x50000008SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x5000000CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50000010SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50000014EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50000018CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50000018CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x5000001CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x5000001CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x50000020CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50000024CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x50000028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5000002CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x50000034CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x50000038CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x5000003CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x50000040CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x50000058ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x5000005CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x50000060AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x50000064AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x500003DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x500003E0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
• 0x40000400TIM3//

  • 0x40000400CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000404CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000408SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000040CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000410SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000414EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000418CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000041CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000041CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000420CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000424CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x40000428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000042CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x40000434CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x40000438CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x4000043CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x40000440CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x40000458ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x4000045CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x40000460AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x40000464AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x400007DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x400007E0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
  interrupts:
  • [38] TIM3 // TIM3 global interrupt
• 0x50000400SEC_TIM3//

  • 0x50000400CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50000404CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x50000408SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x5000040CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50000410SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50000414EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50000418CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50000418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x5000041CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x5000041CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x50000420CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50000424CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x50000428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5000042CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x50000434CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x50000438CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x5000043CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x50000440CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x50000458ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x5000045CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x50000460AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x50000464AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x500007DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x500007E0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
• 0x40000800TIM4//

  • 0x40000800CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000804CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000808SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000080CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000810SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000814EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000818CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000081CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000081CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000820CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000824CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x40000828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000082CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x40000834CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x40000838CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x4000083CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x40000840CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x40000858ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x4000085CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x40000860AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x40000864AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x40000BDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40000BE0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
  interrupts:
  • [39] TIM4 // TIM4 global interrupt
• 0x50000800SEC_TIM4//

  • 0x50000800CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50000804CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x50000808SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x5000080CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50000810SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50000814EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50000818CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50000818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x5000081CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x5000081CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x50000820CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50000824CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x50000828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5000082CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x50000834CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x50000838CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x5000083CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x50000840CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x50000858ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x5000085CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x50000860AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x50000864AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x50000BDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x50000BE0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
• 0x40000C00TIM5//

  • 0x40000C00CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000C04CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000C08SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40000C0CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000C10SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000C14EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000C18CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C18CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C1CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C1CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C20CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000C24CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x40000C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40000C2CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x40000C34CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x40000C38CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x40000C3CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x40000C40CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x40000C58ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x40000C5CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x40000C60AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x40000C64AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x40000FDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40000FE0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
  interrupts:
  • [4] TIM5 // TIM5 global interrupt
• 0x50000C00SEC_TIM5//

  • 0x50000C00CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50000C04CR2// control register 2

    • [25]MMS_3 (def=0x0) // Master mode selection
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x50000C08SMCR// slave mode control register

    • [25]SMSPS (def=0x0) // SMS preload source
    • [24]SMSPE (def=0x0) // SMS preload enable
    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_bit3 (def=0x0) // Slave mode selection - bit 3
    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [3]OCCS (def=0x0) // OCREF clear selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x50000C0CDIER// DMA/Interrupt enable register

    • [23]TERRIE (def=0x0) // Transition error interrupt enable
    • [22]IERRIE (def=0x0) // Index error interrupt enable
    • [21]DIRIE (def=0x0) // Direction change interrupt enable
    • [20]IDXIE (def=0x0) // Index interrupt enable
    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50000C10SR// status register

    • [23]TERRF (def=0x0) // Transition error interrupt flag
    • [22]IERRF (def=0x0) // Index error interrupt flag
    • [21]DIRF (def=0x0) // Direction change interrupt flag
    • [20]IDXF (def=0x0) // Index interrupt flag
    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50000C14EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50000C18CCMR1_Output// capture/compare mode register 1 (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50000C18CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50000C1CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [24]OC4M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC3M_bit3 (def=0x0) // Output Compare 1 mode - bit 3
    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x50000C1CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x50000C20CCER// capture/compare enable register

    • [15]CC4NP (def=0x0) // Capture/Compare 4 output Polarity
    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50000C24CNT// counter

    • [16:30]CNT_H (def=0x0) // Most significant part counter value (on TIM2 and TIM5)
    • [0:15]CNT_L (def=0x0) // Least significant part of counter value
    • [31]CNT_bit31 (def=0x0) // Most significant bit of counter value (on TIM2 and TIM5)
  • 0x50000C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x50000C2CARR// auto-reload register

    • [16:31]ARR_H (def=0xFFFF) // High Auto-reload value (TIM2 only)
    • [0:15]ARR_L (def=0xFFFF) // Low Auto-reload value
  • 0x50000C34CCR1// capture/compare register 1

    • [16:31]CCR1_H (def=0x0) // High Capture/Compare 1 value (TIM2 only)
    • [0:15]CCR1_L (def=0x0) // Low Capture/Compare 1 value
  • 0x50000C38CCR2// capture/compare register 2

    • [16:31]CCR2_H (def=0x0) // High Capture/Compare 2 value (TIM2 only)
    • [0:15]CCR2_L (def=0x0) // Low Capture/Compare 2 value
  • 0x50000C3CCCR3// capture/compare register 3

    • [16:31]CCR3_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR3_L (def=0x0) // Low Capture/Compare value
  • 0x50000C40CCR4// capture/compare register 4

    • [16:31]CCR4_H (def=0x0) // High Capture/Compare value (TIM2 only)
    • [0:15]CCR4_L (def=0x0) // Low Capture/Compare value
  • 0x50000C58ECR// encoder control register

    • [24:26]PWPRSC (def=0x0) // Pulse width prescaler
    • [16:23]PW (def=0x0) // Pulse width
    • [6:7]IPOS (def=0x0) // Index positioning
    • [5]FIDX (def=0x0) // First index
    • [3:4]IBLK (def=0x0) // Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
    • [1:2]IDIR (def=0x0) // Index direction
    • [0]IE (def=0x0) // Index enable
  • 0x50000C5CTISEL// timer input selection register

    • [24:27]TI4SEL (def=0x0) // Selects tim_ti4[0..15] input
    • [16:19]TI3SEL (def=0x0) // Selects tim_ti3[0..15] input
    • [8:11]TI2SEL (def=0x0) // Selects tim_ti2[0..15] input
    • [0:3]TI1SEL (def=0x0) // Selects tim_ti1[0..15] input
  • 0x50000C60AF1// alternate function register 1

    • [14:17]ETRSEL (def=0x0) // etr_in source selection
  • 0x50000C64AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x50000FDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x50000FE0DMAR// DMA address for full transfer

    • [0:31]ETRSEL (def=0x0) // DMA register for burst accesses
• 0x40014000TIM15// General purpose timers

  • 0x40014000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40014004CR2// control register 2

    • [10]OIS2 (def=0x0) // Output idle state 2 (OC2 output)
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:5]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40014008SMCR// slave mode control register

    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_3 (def=0x0) // Slave mode selection
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [7]MSM (def=0x0) // Master/slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4001400CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40014010SR// status register

    • [10]CC2OF (def=0x0) // Capture/Compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40014014EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [2]CC2G (def=0x0) // Capture/Compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40014018CCMR1_Output// capture/compare mode register (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014018CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014020CCER// capture/compare enable register

    • [7]CC2NP (def=0x0) // Capture/Compare 2 complementary output polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40014024CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // counter value
  • 0x40014028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001402CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x40014030RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x40014034CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40014038CCR2// capture/compare register 2

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40014044BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [16:19]BKF (def=0x0) // Break filter
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x40014054DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup
  • 0x4001405CTISEL// input selection register

    • [8:11]TI2SEL (def=0x0) // selects tim_ti2_in[0..15] input
    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x40014060AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x0) // TIMx_BKIN input enable
  • 0x40014064AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x400143DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x400143E0DMAR// DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses
  interrupts:
  • [6] TIM15 // TIM15 global interrupt
• 0x50014000SEC_TIM15//

  • 0x50014000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50014004CR2// control register 2

    • [10]OIS2 (def=0x0) // Output idle state 2 (OC2 output)
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:5]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x50014008SMCR// slave mode control register

    • [20:21]TS_4_3 (def=0x0) // Trigger selection
    • [16]SMS_3 (def=0x0) // Slave mode selection
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [7]MSM (def=0x0) // Master/slave mode
    • [4:6]TS_2_0 (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x5001400CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50014010SR// status register

    • [10]CC2OF (def=0x0) // Capture/Compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50014014EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [2]CC2G (def=0x0) // Capture/Compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50014018CCMR1_Output// capture/compare mode register (output mode)

    • [24]OC2M_bit3 (def=0x0) // Output Compare 2 mode - bit 3
    • [16]OC1M_bit3 (def=0x0) // Output Compare 1 mode
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014018CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014020CCER// capture/compare enable register

    • [7]CC2NP (def=0x0) // Capture/Compare 2 complementary output polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50014024CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // counter value
  • 0x50014028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5001402CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x50014030RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x50014034CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x50014038CCR2// capture/compare register 2

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x50014044BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [16:19]BKF (def=0x0) // Break filter
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x50014054DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Dead-time falling edge generator setup
  • 0x5001405CTISEL// input selection register

    • [8:11]TI2SEL (def=0x0) // selects tim_ti2_in[0..15] input
    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x50014060AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x0) // TIMx_BKIN input enable
  • 0x50014064AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // ocref_clr source selection
  • 0x500143DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x500143E0DMAR// DMA address for full transfer

    • [0:31]DMAB (def=0x0) // DMA register for burst accesses
• 0x40014400TIM16// General purpose timers

  • 0x40014400CR1// control register 1

    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40014404CR2// control register 2

    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x4001440CDIER// DMA/interrupt enable register

    • [13]COMDE (def=0x0) // COM DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40014410SR// status register

    • [9]CC1OF (def=0x0) // CC1OF
    • [7]BIF (def=0x0) // Break interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [1]CC1IF (def=0x0) // Capture/Compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40014414EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40014418CCMR1_Output// capture/compare mode register (output mode)

    • [16]OC1M_2 (def=0x0) // Output Compare 1 mode
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014420CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40014424CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // CNT
  • 0x40014428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001442CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x40014430RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x40014434CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40014444BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x40014454DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Deadtime asymmetric enable
  • 0x4001445CTISEL// TIM17 option register 1

    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x40014460AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x1) // TIMx_BKIN input enable
  • 0x40014464AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // tim_ocref_clr source selection
  • 0x400147DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x1) // DMA base address
  • 0x400147E0DMAR// TIM17 option register 1

    • [0:31]DMAB (def=0x1) // DMA register for burst accesses
  interrupts:
  • [56] TIM16 // TIM16 global interrupt
• 0x50014400SEC_TIM16//

  • 0x50014400CR1// control register 1

    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50014404CR2// control register 2

    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x5001440CDIER// DMA/interrupt enable register

    • [13]COMDE (def=0x0) // COM DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50014410SR// status register

    • [9]CC1OF (def=0x0) // CC1OF
    • [7]BIF (def=0x0) // Break interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [1]CC1IF (def=0x0) // Capture/Compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50014414EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50014418CCMR1_Output// capture/compare mode register (output mode)

    • [16]OC1M_2 (def=0x0) // Output Compare 1 mode
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014420CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50014424CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // CNT
  • 0x50014428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5001442CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x50014430RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x50014434CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x50014444BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x50014454DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Deadtime asymmetric enable
  • 0x5001445CTISEL// TIM17 option register 1

    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x50014460AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x1) // TIMx_BKIN input enable
  • 0x50014464AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // tim_ocref_clr source selection
  • 0x500147DCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x1) // DMA base address
  • 0x500147E0DMAR// TIM17 option register 1

    • [0:31]DMAB (def=0x1) // DMA register for burst accesses
• 0x40014800TIM17//

  • 0x40014800CR1// control register 1

    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40014804CR2// control register 2

    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x4001480CDIER// DMA/interrupt enable register

    • [13]COMDE (def=0x0) // COM DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40014810SR// status register

    • [9]CC1OF (def=0x0) // CC1OF
    • [7]BIF (def=0x0) // Break interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [1]CC1IF (def=0x0) // Capture/Compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40014814EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40014818CCMR1_Output// capture/compare mode register (output mode)

    • [16]OC1M_2 (def=0x0) // Output Compare 1 mode
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014820CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40014824CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // CNT
  • 0x40014828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001482CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x40014830RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x40014834CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40014844BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x40014854DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Deadtime asymmetric enable
  • 0x4001485CTISEL// TIM17 option register 1

    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x40014860AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x1) // TIMx_BKIN input enable
  • 0x40014864AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // tim_ocref_clr source selection
  • 0x40014BDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x1) // DMA base address
  • 0x40014BE0DMAR// TIM17 option register 1

    • [0:31]DMAB (def=0x1) // DMA register for burst accesses
  interrupts:
  • [57] TIM17 // TIM17 global interrupt
• 0x50014800SEC_TIM17//

  • 0x50014800CR1// control register 1

    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50014804CR2// control register 2

    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x5001480CDIER// DMA/interrupt enable register

    • [13]COMDE (def=0x0) // COM DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x50014810SR// status register

    • [9]CC1OF (def=0x0) // CC1OF
    • [7]BIF (def=0x0) // Break interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [1]CC1IF (def=0x0) // Capture/Compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x50014814EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x50014818CCMR1_Output// capture/compare mode register (output mode)

    • [16]OC1M_2 (def=0x0) // Output Compare 1 mode
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x50014820CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x50014824CNT// counter

    • [31]UIFCPY (def=0x0) // UIF Copy
    • [0:15]CNT (def=0x0) // CNT
  • 0x50014828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x5001482CARR// auto-reload register

    • [0:19]ARR (def=0xFFFF) // Auto-reload value
  • 0x50014830RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x50014834CCR1// capture/compare register 1

    • [0:19]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x50014844BDTR// break and dead-time register

    • [28]BKBID (def=0x0) // Break Bidirectional
    • [26]BKDSRM (def=0x0) // Break Disarm
    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x50014854DTR2// timer deadtime register 2

    • [17]DTPE (def=0x0) // Deadtime preload enable
    • [16]DTAE (def=0x0) // Deadtime asymmetric enable
    • [0:7]DTGF (def=0x0) // Deadtime asymmetric enable
  • 0x5001485CTISEL// TIM17 option register 1

    • [0:3]TI1SEL (def=0x0) // selects tim_ti1_in[0..15] input
  • 0x50014860AF1// alternate function register 1

    • [13]BKCMP4P (def=0x0) // tim_brk_cmp4 input polarity
    • [12]BKCMP3P (def=0x0) // tim_brk_cmp3 input polarity
    • [11]BKCMP2P (def=0x0) // tim_brk_cmp2 input polarity
    • [10]BKCMP1P (def=0x0) // tim_brk_cmp1 input polarity
    • [9]BKINP (def=0x0) // TIMx_BKIN input polarity
    • [7]BKCMP7E (def=0x0) // tim_brk_cmp7 enable
    • [6]BKCMP6E (def=0x0) // tim_brk_cmp6 enable
    • [5]BKCMP5E (def=0x0) // tim_brk_cmp5 enable
    • [4]BKCMP4E (def=0x0) // tim_brk_cmp4 enable
    • [3]BKCMP3E (def=0x0) // tim_brk_cmp3 enable
    • [2]BKCMP2E (def=0x0) // tim_brk_cmp2 enable
    • [1]BKCMP1E (def=0x0) // tim_brk_cmp1 enable
    • [0]BKINE (def=0x1) // TIMx_BKIN input enable
  • 0x50014864AF2// alternate function register 2

    • [16:18]OCRSEL (def=0x0) // tim_ocref_clr source selection
  • 0x50014BDCDCR// DMA control register

    • [16:19]DBSS (def=0x0) // DMA burst source selection
    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x1) // DMA base address
  • 0x50014BE0DMAR// TIM17 option register 1

    • [0:31]DMAB (def=0x1) // DMA register for burst accesses
• 0x40001000TIM6// General-purpose-timers

  • 0x40001000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001004CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000100CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // UDE
    • [0]UIE (def=0x0) // UIE
  • 0x40001010SR// status register

    • [0]UIF (def=0x0) // UIF
  • 0x40001014EGR// event generation register

    • [0]UG (def=0x0) // UG
  • 0x40001024CNT// counter

    • [31]UIFCPY (def=0x0) // UIFCPY
    • [0:15]CNT (def=0x0) // CNT
  • 0x40001028PSC// prescaler

    • [0:15]PSC (def=0x0) // PSC
  • 0x4000102CARR// auto-reload register

    • [0:18]ARR (def=0xFFFF) // ARR
  interrupts:
  • [49] TIM6 // TIM6 global interrupt
• 0x50001000SEC_TIM6//

  • 0x50001000CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50001004CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x5000100CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // UDE
    • [0]UIE (def=0x0) // UIE
  • 0x50001010SR// status register

    • [0]UIF (def=0x0) // UIF
  • 0x50001014EGR// event generation register

    • [0]UG (def=0x0) // UG
  • 0x50001024CNT// counter

    • [31]UIFCPY (def=0x0) // UIFCPY
    • [0:15]CNT (def=0x0) // CNT
  • 0x50001028PSC// prescaler

    • [0:15]PSC (def=0x0) // PSC
  • 0x5000102CARR// auto-reload register

    • [0:18]ARR (def=0xFFFF) // ARR
• 0x40001400TIM7//

  • 0x40001400CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001404CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000140CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // UDE
    • [0]UIE (def=0x0) // UIE
  • 0x40001410SR// status register

    • [0]UIF (def=0x0) // UIF
  • 0x40001414EGR// event generation register

    • [0]UG (def=0x0) // UG
  • 0x40001424CNT// counter

    • [31]UIFCPY (def=0x0) // UIFCPY
    • [0:15]CNT (def=0x0) // CNT
  • 0x40001428PSC// prescaler

    • [0:15]PSC (def=0x0) // PSC
  • 0x4000142CARR// auto-reload register

    • [0:18]ARR (def=0xFFFF) // ARR
  interrupts:
  • [50] TIM7 // TIM7 global interrupt
• 0x50001400SEC_TIM7//

  • 0x50001400CR1// control register 1

    • [12]DITHEN (def=0x0) // Dithering Enable
    • [11]UIFREMAP (def=0x0) // UIF status bit remapping
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x50001404CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x5000140CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // UDE
    • [0]UIE (def=0x0) // UIE
  • 0x50001410SR// status register

    • [0]UIF (def=0x0) // UIF
  • 0x50001414EGR// event generation register

    • [0]UG (def=0x0) // UG
  • 0x50001424CNT// counter

    • [31]UIFCPY (def=0x0) // UIFCPY
    • [0:15]CNT (def=0x0) // CNT
  • 0x50001428PSC// prescaler

    • [0:15]PSC (def=0x0) // PSC
  • 0x5000142CARR// auto-reload register

    • [0:18]ARR (def=0xFFFF) // ARR
• 0x40002C00WWDG// System window watchdog

  • 0x40002C00CR// Control register

    • [7]WDGA (def=0x0) // Activation bit
    • [0:6]T (def=0x7F) // 7-bit counter (MSB to LSB)
  • 0x40002C04CFR// Configuration register

    • [11:13]WDGTB (def=0x0) // Timer base
    • [9]EWI (def=0x0) // Early wakeup interrupt
    • [0:6]W (def=0x7F) // 7-bit window value
  • 0x40002C08SR// Status register

    • [0]EWIF (def=0x0) // Early wakeup interrupt flag
  interrupts:
  • [0] WWDG // Window Watchdog interrupt
• 0x50002C00SEC_WWDG//

  • 0x50002C00CR// Control register

    • [7]WDGA (def=0x0) // Activation bit
    • [0:6]T (def=0x7F) // 7-bit counter (MSB to LSB)
  • 0x50002C04CFR// Configuration register

    • [11:13]WDGTB (def=0x0) // Timer base
    • [9]EWI (def=0x0) // Early wakeup interrupt
    • [0:6]W (def=0x7F) // 7-bit window value
  • 0x50002C08SR// Status register

    • [0]EWIF (def=0x0) // Early wakeup interrupt flag
• 0x46000400SYSCFG// System configuration controller

  • 0x46000400SECCFGR// SYSCFG secure configuration register

    • [0]SYSCFGSEC (def=0x0) // SYSCFG clock control security
    • [1]CLASSBSEC (def=0x0) // CLASSBSEC
    • [3]FPUSEC (def=0x0) // FPUSEC
  • 0x46000404CFGR1// configuration register 1

    • [19]PB9_FMP (def=0x0) // PB9_FMP
    • [18]PB8_FMP (def=0x0) // PB8_FMP
    • [17]PB7_FMP (def=0x0) // PB7_FMP
    • [16]PB6_FMP (def=0x0) // PB6_FMP
    • [9]ANASWVDD (def=0x0) // GPIO analog switch control voltage selection
    • [8]BOOSTEN (def=0x0) // I/O analog switch voltage booster enable
  • 0x46000408FPUIMR// FPU interrupt mask register

    • [0:5]FPU_IE (def=0x1F) // Floating point unit interrupts enable bits
  • 0x4600040CCNSLCKR// SYSCFG CPU non-secure lock register

    • [0]LOCKNSVTOR (def=0x0) // VTOR_NS register lock
    • [1]LOCKNSMPU (def=0x0) // Non-secure MPU registers lock
  • 0x46000410CSLOCKR// SYSCFG CPU secure lock register

    • [0]LOCKSVTAIRCR (def=0x0) // LOCKSVTAIRCR
    • [1]LOCKSMPU (def=0x0) // LOCKSMPU
    • [2]LOCKSAU (def=0x0) // LOCKSAU
  • 0x46000414CFGR2// configuration register 2

    • [3]ECCL (def=0x0) // ECC Lock
    • [2]PVDL (def=0x0) // PVD lock enable bit
    • [1]SPL (def=0x0) // SRAM ECC lock bit
    • [0]CLL (def=0x0) // LOCKUP (hardfault) output enable bit
  • 0x46000418MESR// memory erase status register

    • [16]IPMEE (def=0x0) // IPMEE
    • [0]MCLR (def=0x0) // MCLR
  • 0x4600041CCCCSR// compensation cell control/status register

    • [0]EN1 (def=0x0) // EN1
    • [1]CS1 (def=0x1) // CS1
    • [2]EN2 (def=0x0) // EN2
    • [3]CS2 (def=0x1) // CS2
    • [8]RDY1 (def=0x0) // RDY1
    • [9]RDY2 (def=0x0) // RDY2
  • 0x46000420CCVR// compensation cell value register

    • [0:3]NCV1 (def=0x0) // NCV1
    • [4:7]PCV1 (def=0x0) // PCV1
    • [8:11]NCV2 (def=0x0) // NCV2
    • [12:15]PCV2 (def=0x0) // PCV2
  • 0x46000424CCCR// compensation cell code register

    • [0:3]NCC1 (def=0x8) // NCC1
    • [4:7]PCC1 (def=0x7) // PCC1
    • [8:11]NCC2 (def=0x8) // NCC2
    • [12:15]PCC2 (def=0x7) // PCC2
  • 0x4600042CRSSCMDR// RSS command register

    • [0:15]RSSCMD (def=0x0) // RSS commands
  • 0x46000470UCPDR// USB Type C and Power Delivery register

    • [0]CC1ENRXFILTER (def=0x0) // CC1ENRXFILTER
    • [1]CC2ENRXFILTER (def=0x0) // CC2ENRXFILTER
• 0x56000400SEC_SYSCFG//

  • 0x56000400SECCFGR// SYSCFG secure configuration register

    • [0]SYSCFGSEC (def=0x0) // SYSCFG clock control security
    • [1]CLASSBSEC (def=0x0) // CLASSBSEC
    • [3]FPUSEC (def=0x0) // FPUSEC
  • 0x56000404CFGR1// configuration register 1

    • [19]PB9_FMP (def=0x0) // PB9_FMP
    • [18]PB8_FMP (def=0x0) // PB8_FMP
    • [17]PB7_FMP (def=0x0) // PB7_FMP
    • [16]PB6_FMP (def=0x0) // PB6_FMP
    • [9]ANASWVDD (def=0x0) // GPIO analog switch control voltage selection
    • [8]BOOSTEN (def=0x0) // I/O analog switch voltage booster enable
  • 0x56000408FPUIMR// FPU interrupt mask register

    • [0:5]FPU_IE (def=0x1F) // Floating point unit interrupts enable bits
  • 0x5600040CCNSLCKR// SYSCFG CPU non-secure lock register

    • [0]LOCKNSVTOR (def=0x0) // VTOR_NS register lock
    • [1]LOCKNSMPU (def=0x0) // Non-secure MPU registers lock
  • 0x56000410CSLOCKR// SYSCFG CPU secure lock register

    • [0]LOCKSVTAIRCR (def=0x0) // LOCKSVTAIRCR
    • [1]LOCKSMPU (def=0x0) // LOCKSMPU
    • [2]LOCKSAU (def=0x0) // LOCKSAU
  • 0x56000414CFGR2// configuration register 2

    • [3]ECCL (def=0x0) // ECC Lock
    • [2]PVDL (def=0x0) // PVD lock enable bit
    • [1]SPL (def=0x0) // SRAM ECC lock bit
    • [0]CLL (def=0x0) // LOCKUP (hardfault) output enable bit
  • 0x56000418MESR// memory erase status register

    • [16]IPMEE (def=0x0) // IPMEE
    • [0]MCLR (def=0x0) // MCLR
  • 0x5600041CCCCSR// compensation cell control/status register

    • [0]EN1 (def=0x0) // EN1
    • [1]CS1 (def=0x1) // CS1
    • [2]EN2 (def=0x0) // EN2
    • [3]CS2 (def=0x1) // CS2
    • [8]RDY1 (def=0x0) // RDY1
    • [9]RDY2 (def=0x0) // RDY2
  • 0x56000420CCVR// compensation cell value register

    • [0:3]NCV1 (def=0x0) // NCV1
    • [4:7]PCV1 (def=0x0) // PCV1
    • [8:11]NCV2 (def=0x0) // NCV2
    • [12:15]PCV2 (def=0x0) // PCV2
  • 0x56000424CCCR// compensation cell code register

    • [0:3]NCC1 (def=0x8) // NCC1
    • [4:7]PCC1 (def=0x7) // PCC1
    • [8:11]NCC2 (def=0x8) // NCC2
    • [12:15]PCC2 (def=0x7) // PCC2
  • 0x5600042CRSSCMDR// RSS command register

    • [0:15]RSSCMD (def=0x0) // RSS commands
  • 0x56000470UCPDR// USB Type C and Power Delivery register

    • [0]CC1ENRXFILTER (def=0x0) // CC1ENRXFILTER
    • [1]CC2ENRXFILTER (def=0x0) // CC2ENRXFILTER
• 0x420C2000PKA// Private key accelerator

  • 0x420C2000CR// Control register

    • [21]OPERRIE (def=0x0) // Operation error interrupt enable
    • [20]ADDRERRIE (def=0x0) // Address error interrupt enable
    • [19]RAMERRIE (def=0x0) // RAM error interrupt enable
    • [17]PROCENDIE (def=0x0) // End of operation interrupt enable
    • [8:13]MODE (def=0x0) // PKA Operation Mode
    • [1]START (def=0x0) // Start the operation
    • [0]EN (def=0x0) // Peripheral Enable
  • 0x420C2004SR// PKA status register

    • [0]INITOK (def=0x0) // INITOK
    • [16]BUSY (def=0x0) // PKA operation is in progress
    • [17]PROCENDF (def=0x0) // PKA End of Operation flag
    • [19]RAMERRF (def=0x0) // RAMERRF
    • [20]ADDRERRF (def=0x0) // ADDRERRF
    • [21]OPERRF (def=0x0) // OPERRF
  • 0x420C2008CLRFR// PKA clear flag register

    • [17]PROCENDFC (def=0x0) // Clear PKA End of Operation flag
    • [19]RAMERRFC (def=0x0) // RAMERRFC
    • [20]ADDRERRFC (def=0x0) // ADDRERRFC
    • [21]OPERRFC (def=0x0) // OPERRFC
  interrupts:
  • [0] PKA // PKA global interrupt
• 0x520C2000SEC_PKA//

  • 0x520C2000CR// Control register

    • [21]OPERRIE (def=0x0) // Operation error interrupt enable
    • [20]ADDRERRIE (def=0x0) // Address error interrupt enable
    • [19]RAMERRIE (def=0x0) // RAM error interrupt enable
    • [17]PROCENDIE (def=0x0) // End of operation interrupt enable
    • [8:13]MODE (def=0x0) // PKA Operation Mode
    • [1]START (def=0x0) // Start the operation
    • [0]EN (def=0x0) // Peripheral Enable
  • 0x520C2004SR// PKA status register

    • [0]INITOK (def=0x0) // INITOK
    • [16]BUSY (def=0x0) // PKA operation is in progress
    • [17]PROCENDF (def=0x0) // PKA End of Operation flag
    • [19]RAMERRF (def=0x0) // RAMERRF
    • [20]ADDRERRF (def=0x0) // ADDRERRF
    • [21]OPERRF (def=0x0) // OPERRF
  • 0x520C2008CLRFR// PKA clear flag register

    • [17]PROCENDFC (def=0x0) // Clear PKA End of Operation flag
    • [19]RAMERRFC (def=0x0) // RAMERRFC
    • [20]ADDRERRFC (def=0x0) // ADDRERRFC
    • [21]OPERRFC (def=0x0) // OPERRFC
• 0xE0044000DBGMCU// MCU debug component

  • 0xE0044000IDCODE// DBGMCU_IDCODE

    • [0:11]DEV_ID (def=0x482) // Device dentification
    • [16:31]REV_ID (def=0x3001) // Revision
  • 0xE0044004CR// Debug MCU configuration register

    • [1]DBG_STOP (def=0x0) // Debug Stop mode
    • [2]DBG_STANDBY (def=0x0) // Debug Standby mode
    • [4]TRACE_IOEN (def=0x0) // Trace pin assignment control
    • [5]TRACE_EN (def=0x0) // trace port and clock enable
    • [6:7]TRACE_MODE (def=0x0) // Trace pin assignment control
  • 0xE0044008APB1LFZR// Debug MCU APB1L peripheral freeze register

    • [0]DBG_TIM2_STOP (def=0x0) // TIM2 stop in debug
    • [1]DBG_TIM3_STOP (def=0x0) // TIM3 stop in debug
    • [2]DBG_TIM4_STOP (def=0x0) // TIM4 stop in debug
    • [3]DBG_TIM5_STOP (def=0x0) // TIM5 stop in debug
    • [4]DBG_TIM6_STOP (def=0x0) // TIM6 stop in debug
    • [5]DBG_TIM7_STOP (def=0x0) // TIM7 stop in debug
    • [11]DBG_WWDG_STOP (def=0x0) // Window watchdog counter stop in debug
    • [12]DBG_IWDG_STOP (def=0x0) // Independent watchdog counter stop in debug
    • [21]DBG_I2C1_STOP (def=0x0) // I2C1 SMBUS timeout stop in debug
    • [22]DBG_I2C2_STOP (def=0x0) // I2C2 SMBUS timeout stop in debug
  • 0xE004400CAPB1HFZR// Debug MCU APB1H peripheral freeze register

    • [1]DBG_I2C4_STOP (def=0x0) // I2C4 stop in debug
    • [5]DBG_LPTIM2_STOP (def=0x0) // LPTIM2 stop in debug
  • 0xE0044010APB2FZR// Debug MCU APB2 peripheral freeze register

    • [11]DBG_TIM1_STOP (def=0x0) // TIM1 counter stopped when core is halted
    • [13]DBG_TIM8_STOP (def=0x0) // TIM8 stop in debug
    • [16]DBG_TIM15_STOP (def=0x0) // TIM15 counter stopped when core is halted
    • [17]DBG_TIM16_STOP (def=0x0) // TIM16 counter stopped when core is halted
    • [18]DBG_TIM17_STOP (def=0x0) // DBG_TIM17_STOP
  • 0xE0044014APB3FZR// Debug MCU APB3 peripheral freeze register

    • [10]DBG_I2C3_STOP (def=0x0) // I2C3 stop in debug
    • [17]DBG_LPTIM1_STOP (def=0x0) // LPTIM1 stop in debug
    • [18]DBG_LPTIM3_STOP (def=0x0) // LPTIM3 stop in debug
    • [19]DBG_LPTIM4_STOP (def=0x0) // LPTIM4 stop in debug
    • [30]DBG_RTC_STOP (def=0x0) // RTC stop in debug
  • 0xE0044020AHB1FZR// Debug MCU AHB1 peripheral freeze register

    • [0]DBG_GPDMA0_STOP (def=0x0) // GPDMA channel 0 stop in debug
    • [1]DBG_GPDMA1_STOP (def=0x0) // GPDMA channel 1 stop in debug
    • [2]DBG_GPDMA2_STOP (def=0x0) // GPDMA channel 2 stop in debug
    • [3]DBG_GPDMA3_STOP (def=0x0) // GPDMA channel 3 stop in debug
    • [4]DBG_GPDMA4_STOP (def=0x0) // GPDMA channel 4 stop in debug
    • [5]DBG_GPDMA5_STOP (def=0x0) // GPDMA channel 5 stop in debug
    • [6]DBG_GPDMA6_STOP (def=0x0) // GPDMA channel 6 stop in debug
    • [7]DBG_GPDMA7_STOP (def=0x0) // GPDMA channel 7 stop in debug
    • [8]DBG_GPDMA8_STOP (def=0x0) // GPDMA channel 8 stop in debug
    • [9]DBG_GPDMA9_STOP (def=0x0) // GPDMA channel 9 stop in debug
    • [10]DBG_GPDMA10_STOP (def=0x0) // GPDMA channel 10 stop in debug
    • [11]DBG_GPDMA11_STOP (def=0x0) // GPDMA channel 11 stop in debug
    • [12]DBG_GPDMA12_STOP (def=0x0) // GPDMA channel 12 stop in debug
    • [13]DBG_GPDMA13_STOP (def=0x0) // GPDMA channel 13 stop in debug
    • [14]DBG_GPDMA14_STOP (def=0x0) // GPDMA channel 14 stop in debug
    • [15]DBG_GPDMA15_STOP (def=0x0) // GPDMA channel 15 stop in debug
  • 0xE0044028AHB3FZR// Debug MCU AHB3 peripheral freeze register

    • [0]DBG_LPDMA0_STOP (def=0x0) // LPDMA channel 0 stop in debug
    • [1]DBG_LPDMA1_STOP (def=0x0) // LPDMA channel 1 stop in debug
    • [2]DBG_LPDMA2_STOP (def=0x0) // LPDMA channel 2 stop in debug
    • [3]DBG_LPDMA3_STOP (def=0x0) // LPDMA channel 3 stop in debug
  • 0xE00440FCDBGMCU_SR// DBGMCU status register

    • [0:7]AP_PRESENT (def=0x1) // Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 
    • [8:15]AP_LOCKED (def=0x0) // DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (ca
  • 0xE0044100DBGMCU_DBG_AUTH_HOST// DBGMCU debug host authentication register

    • [0:31]AUTH_KEY (def=0x0) // Device authentication key The device specific 64-bit authentication key (OEM key) must be written
  • 0xE0044104DBGMCU_DBG_AUTH_DEVICE// DBGMCU debug device authentication register

    • [0:31]AUTH_ID (def=0x0) // Device specific ID Device specific ID used for RDP regression.
  • 0xE0044FD0PIDR4// Debug MCU CoreSight peripheral identity register 4

    • [0:3]JEP106CON (def=0x0) // JEP106 continuation code
    • [4:7]KCOUNT_4 (def=0x0) // register file size
  • 0xE0044FE0PIDR0// Debug MCU CoreSight peripheral identity register 0

    • [0:7]PARTNUM (def=0x0) // part number bits [7:0]
  • 0xE0044FE4PIDR1// Debug MCU CoreSight peripheral identity register 1

    • [0:3]PARTNUM (def=0x0) // part number bits [11:8]
    • [4:7]JEP106ID (def=0x0) // JEP106 identity code bits [3:0]
  • 0xE0044FE8PIDR2// Debug MCU CoreSight peripheral identity register 2

    • [0:2]JEP106ID (def=0x2) // JEP106 identity code bits [6:4]
    • [3]JEDEC (def=0x1) // JEDEC assigned value
    • [4:7]REVISION (def=0x0) // component revision number
  • 0xE0044FECPIDR3// Debug MCU CoreSight peripheral identity register 3

    • [0:3]CMOD (def=0x0) // customer modified
    • [4:7]REVAND (def=0x0) // metal fix version
  • 0xE0044FF0CIDR0// Debug MCU CoreSight component identity register 0

    • [0:7]PREAMBLE (def=0xD) // component identification bits [7:0]
  • 0xE0044FF4CIDR1// Debug MCU CoreSight component identity register 1

    • [0:3]PREAMBLE (def=0x0) // component identification bits [11:8]
    • [4:7]CLASS (def=0xF) // component identification bits [15:12] - component class
  • 0xE0044FF8CIDR2// Debug MCU CoreSight component identity register 2

    • [0:7]PREAMBLE (def=0x5) // component identification bits [23:16]
  • 0xE0044FFCCIDR3// Debug MCU CoreSight component identity register 3

    • [0:7]PREAMBLE (def=0xB1) // component identification bits [31:24]
• 0x420D1400OCTOSPI1// OctoSPI

  • 0x420D1400CR// control register

    • [28:29]FMODE (def=0x0) // Functional mode
    • [23]PMM (def=0x0) // Polling match mode
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [20]TOIE (def=0x0) // TimeOut interrupt enable
    • [19]SMIE (def=0x0) // Status match interrupt enable
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable
    • [8:12]FTHRES (def=0x0) // IFO threshold level
    • [7]FSEL (def=0x0) // FLASH memory selection
    • [6]DQM (def=0x0) // Dual-quad mode
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [2]DMAEN (def=0x0) // DMA enable
    • [1]ABORT (def=0x0) // Abort request
    • [0]EN (def=0x0) // Enable
  • 0x420D1408DCR1// device configuration register 1

    • [0]CKMODE (def=0x0) // Mode 0 / mode 3
    • [1]FRCK (def=0x0) // Free running clock
    • [3]DLYBYP (def=0x0) // Delay block bypass
    • [8:13]CSHT (def=0x0) // Chip-select high time
    • [16:20]DEVSIZE (def=0x0) // Device size
    • [24:26]MTYP (def=0x0) // Memory type
  • 0x420D140CDCR2// device configuration register 2

    • [0:7]PRESCALER (def=0x0) // Clock prescaler
    • [16:18]WRAPSIZE (def=0x0) // Wrap size
  • 0x420D1410DCR3// device configuration register 3

    • [0:7]MAXTRAN (def=0x0) // Maximum transfer
    • [16:20]CSBOUND (def=0x0) // CS boundary
  • 0x420D1414DCR4// DCR4

    • [0:31]REFRESH (def=0x0) // Refresh rate
  • 0x420D1420SR// status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // status match flag
    • [4]TOF (def=0x0) // timeout flag
    • [5]BUSY (def=0x0) // BUSY
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x420D1424FCR// flag clear register

    • [0]CTEF (def=0x0) // Clear Transfer error flag
    • [1]CTCF (def=0x0) // Clear transfer complete flag
    • [3]CSMF (def=0x0) // Clear status match flag
    • [4]CTOF (def=0x0) // Clear timeout flag
  • 0x420D1440DLR// data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x420D1448AR// address register

    • [0:31]ADDRESS (def=0x0) // ADDRESS
  • 0x420D1450DR// data register

    • [0:31]DATA (def=0x0) // DATA
  • 0x420D1480PSMKR// polling status mask register

    • [0:31]MASK (def=0x0) // Status MASK
  • 0x420D1488PSMAR// polling status match register

    • [0:31]MATCH (def=0x0) // Status match
  • 0x420D1490PIR// polling interval register

    • [0:15]INTERVAL (def=0x0) // polling interval
  • 0x420D1500CCR// communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // Alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
    • [31]SIOO (def=0x0) // Send instruction only once mode
  • 0x420D1508TCR// timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x420D1510IR// instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D1520ABR// alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x420D1530LPTR// low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout period
  • 0x420D1540WPCCR// wrap communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x420D1548WPTCR// wrap timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x420D1550WPIR// wrap instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D1560WPABR// wrap alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x420D1580WCCR// write communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x420D1588WTCR// write timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
  • 0x420D1590WIR// write instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D15A0WABR// write alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // ALTERNATE
  • 0x420D1600HLCR// HyperBus latency configuration register

    • [0]LM (def=0x0) // Latency mode
    • [1]WZL (def=0x0) // Write zero latency
    • [8:15]TACC (def=0x0) // Access time
    • [16:23]TRWR (def=0x0) // Read write recovery time
  interrupts:
  • [62] OCTOSPI1 // OCTOSPI1 global interrupt
• 0x520D1400SEC_OCTOSPI1//

  • 0x520D1400CR// control register

    • [28:29]FMODE (def=0x0) // Functional mode
    • [23]PMM (def=0x0) // Polling match mode
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [20]TOIE (def=0x0) // TimeOut interrupt enable
    • [19]SMIE (def=0x0) // Status match interrupt enable
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable
    • [8:12]FTHRES (def=0x0) // IFO threshold level
    • [7]FSEL (def=0x0) // FLASH memory selection
    • [6]DQM (def=0x0) // Dual-quad mode
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [2]DMAEN (def=0x0) // DMA enable
    • [1]ABORT (def=0x0) // Abort request
    • [0]EN (def=0x0) // Enable
  • 0x520D1408DCR1// device configuration register 1

    • [0]CKMODE (def=0x0) // Mode 0 / mode 3
    • [1]FRCK (def=0x0) // Free running clock
    • [3]DLYBYP (def=0x0) // Delay block bypass
    • [8:13]CSHT (def=0x0) // Chip-select high time
    • [16:20]DEVSIZE (def=0x0) // Device size
    • [24:26]MTYP (def=0x0) // Memory type
  • 0x520D140CDCR2// device configuration register 2

    • [0:7]PRESCALER (def=0x0) // Clock prescaler
    • [16:18]WRAPSIZE (def=0x0) // Wrap size
  • 0x520D1410DCR3// device configuration register 3

    • [0:7]MAXTRAN (def=0x0) // Maximum transfer
    • [16:20]CSBOUND (def=0x0) // CS boundary
  • 0x520D1414DCR4// DCR4

    • [0:31]REFRESH (def=0x0) // Refresh rate
  • 0x520D1420SR// status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // status match flag
    • [4]TOF (def=0x0) // timeout flag
    • [5]BUSY (def=0x0) // BUSY
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x520D1424FCR// flag clear register

    • [0]CTEF (def=0x0) // Clear Transfer error flag
    • [1]CTCF (def=0x0) // Clear transfer complete flag
    • [3]CSMF (def=0x0) // Clear status match flag
    • [4]CTOF (def=0x0) // Clear timeout flag
  • 0x520D1440DLR// data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x520D1448AR// address register

    • [0:31]ADDRESS (def=0x0) // ADDRESS
  • 0x520D1450DR// data register

    • [0:31]DATA (def=0x0) // DATA
  • 0x520D1480PSMKR// polling status mask register

    • [0:31]MASK (def=0x0) // Status MASK
  • 0x520D1488PSMAR// polling status match register

    • [0:31]MATCH (def=0x0) // Status match
  • 0x520D1490PIR// polling interval register

    • [0:15]INTERVAL (def=0x0) // polling interval
  • 0x520D1500CCR// communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // Alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
    • [31]SIOO (def=0x0) // Send instruction only once mode
  • 0x520D1508TCR// timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x520D1510IR// instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D1520ABR// alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x520D1530LPTR// low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout period
  • 0x520D1540WPCCR// wrap communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x520D1548WPTCR// wrap timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x520D1550WPIR// wrap instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D1560WPABR// wrap alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x520D1580WCCR// write communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x520D1588WTCR// write timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
  • 0x520D1590WIR// write instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D15A0WABR// write alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // ALTERNATE
  • 0x520D1600HLCR// HyperBus latency configuration register

    • [0]LM (def=0x0) // Latency mode
    • [1]WZL (def=0x0) // Write zero latency
    • [8:15]TACC (def=0x0) // Access time
    • [16:23]TRWR (def=0x0) // Read write recovery time
• 0x420D2400OCTOSPI2//

  • 0x420D2400CR// control register

    • [28:29]FMODE (def=0x0) // Functional mode
    • [23]PMM (def=0x0) // Polling match mode
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [20]TOIE (def=0x0) // TimeOut interrupt enable
    • [19]SMIE (def=0x0) // Status match interrupt enable
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable
    • [8:12]FTHRES (def=0x0) // IFO threshold level
    • [7]FSEL (def=0x0) // FLASH memory selection
    • [6]DQM (def=0x0) // Dual-quad mode
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [2]DMAEN (def=0x0) // DMA enable
    • [1]ABORT (def=0x0) // Abort request
    • [0]EN (def=0x0) // Enable
  • 0x420D2408DCR1// device configuration register 1

    • [0]CKMODE (def=0x0) // Mode 0 / mode 3
    • [1]FRCK (def=0x0) // Free running clock
    • [3]DLYBYP (def=0x0) // Delay block bypass
    • [8:13]CSHT (def=0x0) // Chip-select high time
    • [16:20]DEVSIZE (def=0x0) // Device size
    • [24:26]MTYP (def=0x0) // Memory type
  • 0x420D240CDCR2// device configuration register 2

    • [0:7]PRESCALER (def=0x0) // Clock prescaler
    • [16:18]WRAPSIZE (def=0x0) // Wrap size
  • 0x420D2410DCR3// device configuration register 3

    • [0:7]MAXTRAN (def=0x0) // Maximum transfer
    • [16:20]CSBOUND (def=0x0) // CS boundary
  • 0x420D2414DCR4// DCR4

    • [0:31]REFRESH (def=0x0) // Refresh rate
  • 0x420D2420SR// status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // status match flag
    • [4]TOF (def=0x0) // timeout flag
    • [5]BUSY (def=0x0) // BUSY
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x420D2424FCR// flag clear register

    • [0]CTEF (def=0x0) // Clear Transfer error flag
    • [1]CTCF (def=0x0) // Clear transfer complete flag
    • [3]CSMF (def=0x0) // Clear status match flag
    • [4]CTOF (def=0x0) // Clear timeout flag
  • 0x420D2440DLR// data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x420D2448AR// address register

    • [0:31]ADDRESS (def=0x0) // ADDRESS
  • 0x420D2450DR// data register

    • [0:31]DATA (def=0x0) // DATA
  • 0x420D2480PSMKR// polling status mask register

    • [0:31]MASK (def=0x0) // Status MASK
  • 0x420D2488PSMAR// polling status match register

    • [0:31]MATCH (def=0x0) // Status match
  • 0x420D2490PIR// polling interval register

    • [0:15]INTERVAL (def=0x0) // polling interval
  • 0x420D2500CCR// communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // Alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
    • [31]SIOO (def=0x0) // Send instruction only once mode
  • 0x420D2508TCR// timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x420D2510IR// instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D2520ABR// alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x420D2530LPTR// low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout period
  • 0x420D2540WPCCR// wrap communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x420D2548WPTCR// wrap timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x420D2550WPIR// wrap instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D2560WPABR// wrap alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x420D2580WCCR// write communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x420D2588WTCR// write timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
  • 0x420D2590WIR// write instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x420D25A0WABR// write alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // ALTERNATE
  • 0x420D2600HLCR// HyperBus latency configuration register

    • [0]LM (def=0x0) // Latency mode
    • [1]WZL (def=0x0) // Write zero latency
    • [8:15]TACC (def=0x0) // Access time
    • [16:23]TRWR (def=0x0) // Read write recovery time
  interrupts:
  • [120] OCTOSPI2 // OCTOSPI2 global interrupt
• 0x520D2400SEC_OCTOSPI2//

  • 0x520D2400CR// control register

    • [28:29]FMODE (def=0x0) // Functional mode
    • [23]PMM (def=0x0) // Polling match mode
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [20]TOIE (def=0x0) // TimeOut interrupt enable
    • [19]SMIE (def=0x0) // Status match interrupt enable
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable
    • [8:12]FTHRES (def=0x0) // IFO threshold level
    • [7]FSEL (def=0x0) // FLASH memory selection
    • [6]DQM (def=0x0) // Dual-quad mode
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [2]DMAEN (def=0x0) // DMA enable
    • [1]ABORT (def=0x0) // Abort request
    • [0]EN (def=0x0) // Enable
  • 0x520D2408DCR1// device configuration register 1

    • [0]CKMODE (def=0x0) // Mode 0 / mode 3
    • [1]FRCK (def=0x0) // Free running clock
    • [3]DLYBYP (def=0x0) // Delay block bypass
    • [8:13]CSHT (def=0x0) // Chip-select high time
    • [16:20]DEVSIZE (def=0x0) // Device size
    • [24:26]MTYP (def=0x0) // Memory type
  • 0x520D240CDCR2// device configuration register 2

    • [0:7]PRESCALER (def=0x0) // Clock prescaler
    • [16:18]WRAPSIZE (def=0x0) // Wrap size
  • 0x520D2410DCR3// device configuration register 3

    • [0:7]MAXTRAN (def=0x0) // Maximum transfer
    • [16:20]CSBOUND (def=0x0) // CS boundary
  • 0x520D2414DCR4// DCR4

    • [0:31]REFRESH (def=0x0) // Refresh rate
  • 0x520D2420SR// status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // status match flag
    • [4]TOF (def=0x0) // timeout flag
    • [5]BUSY (def=0x0) // BUSY
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x520D2424FCR// flag clear register

    • [0]CTEF (def=0x0) // Clear Transfer error flag
    • [1]CTCF (def=0x0) // Clear transfer complete flag
    • [3]CSMF (def=0x0) // Clear status match flag
    • [4]CTOF (def=0x0) // Clear timeout flag
  • 0x520D2440DLR// data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x520D2448AR// address register

    • [0:31]ADDRESS (def=0x0) // ADDRESS
  • 0x520D2450DR// data register

    • [0:31]DATA (def=0x0) // DATA
  • 0x520D2480PSMKR// polling status mask register

    • [0:31]MASK (def=0x0) // Status MASK
  • 0x520D2488PSMAR// polling status match register

    • [0:31]MATCH (def=0x0) // Status match
  • 0x520D2490PIR// polling interval register

    • [0:15]INTERVAL (def=0x0) // polling interval
  • 0x520D2500CCR// communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // Alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
    • [31]SIOO (def=0x0) // Send instruction only once mode
  • 0x520D2508TCR// timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x520D2510IR// instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D2520ABR// alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x520D2530LPTR// low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout period
  • 0x520D2540WPCCR// wrap communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x520D2548WPTCR// wrap timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
    • [28]DHQC (def=0x0) // Delay hold quarter cycle
    • [30]SSHIFT (def=0x0) // Sample shift
  • 0x520D2550WPIR// wrap instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D2560WPABR// wrap alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // Alternate bytes
  • 0x520D2580WCCR// write communication configuration register

    • [0:2]IMODE (def=0x0) // Instruction mode
    • [3]IDTR (def=0x0) // Instruction double transfer rate
    • [4:5]ISIZE (def=0x0) // Instruction size
    • [8:10]ADMODE (def=0x0) // Address mode
    • [11]ADDTR (def=0x0) // Address double transfer rate
    • [12:13]ADSIZE (def=0x0) // Address size
    • [16:18]ABMODE (def=0x0) // Alternate byte mode
    • [19]ABDTR (def=0x0) // Alternate bytes double transfer rate
    • [20:21]ABSIZE (def=0x0) // Alternate bytes size
    • [24:26]DMODE (def=0x0) // Data mode
    • [27]DDTR (def=0x0) // alternate bytes double transfer rate
    • [29]DQSE (def=0x0) // DQS enable
  • 0x520D2588WTCR// write timing configuration register

    • [0:4]DCYC (def=0x0) // Number of dummy cycles
  • 0x520D2590WIR// write instruction register

    • [0:31]INSTRUCTION (def=0x0) // INSTRUCTION
  • 0x520D25A0WABR// write alternate bytes register

    • [0:31]ALTERNATE (def=0x0) // ALTERNATE
  • 0x520D2600HLCR// HyperBus latency configuration register

    • [0]LM (def=0x0) // Latency mode
    • [1]WZL (def=0x0) // Write zero latency
    • [8:15]TACC (def=0x0) // Access time
    • [16:23]TRWR (def=0x0) // Read write recovery time
• 0x46002400LPUART1// Universal synchronous asynchronous receiver transmitter

  • 0x46002400CR1// Control register 1

    • [31]RXFFIE (def=0x0) // RXFFIE
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [28]M1 (def=0x0) // Word length
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFNEIE
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
  • 0x46002404CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the LPUART node
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [12:13]STOP (def=0x0) // STOP bits
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
  • 0x46002408CR3// Control register 3

    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x4600240CBRR// Baud rate register

    • [0:19]BRR (def=0x0) // BRR
  • 0x46002418RQR// Request register

    • [4]TXFRQ (def=0x0) // TXFRQ
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
  • 0x4600241CISR// Interrupt and status register

    • [27]TXFT (def=0x0) // TXFT
    • [26]RXFT (def=0x0) // RXFT
    • [24]RXFF (def=0x0) // RXFF
    • [23]TXFE (def=0x1) // TXFE
    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
  • 0x46002420ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
  • 0x46002424RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x46002428TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x4600242CPRESC// prescaler register

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x46002430AUTOCR// Autonomous mode control register

    • [0:15]TDN (def=0x0) // TDN
    • [16]TRIGPOL (def=0x0) // TRIGPOL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [31]TECLREN (def=0x1) // TECLREN
  interrupts:
  • [54] LPUART1 // LPUART1 global interrupt
• 0x56002400SEC_LPUART1//

  • 0x56002400CR1// Control register 1

    • [31]RXFFIE (def=0x0) // RXFFIE
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [28]M1 (def=0x0) // Word length
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFNEIE
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
  • 0x56002404CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the LPUART node
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [12:13]STOP (def=0x0) // STOP bits
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
  • 0x56002408CR3// Control register 3

    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x5600240CBRR// Baud rate register

    • [0:19]BRR (def=0x0) // BRR
  • 0x56002418RQR// Request register

    • [4]TXFRQ (def=0x0) // TXFRQ
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
  • 0x5600241CISR// Interrupt and status register

    • [27]TXFT (def=0x0) // TXFT
    • [26]RXFT (def=0x0) // RXFT
    • [24]RXFF (def=0x0) // RXFF
    • [23]TXFE (def=0x1) // TXFE
    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
  • 0x56002420ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
  • 0x56002424RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x56002428TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x5600242CPRESC// prescaler register

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x56002430AUTOCR// Autonomous mode control register

    • [0:15]TDN (def=0x0) // TDN
    • [16]TRIGPOL (def=0x0) // TRIGPOL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [31]TECLREN (def=0x1) // TECLREN
• 0x46005400COMP// Comparator

  • 0x46005400COMP1_CSR// Comparator 1 control and status register

    • [0]COMP1_EN (def=0x0) // Comparator 1 enable bit
    • [4:7]COMP1_INMSEL (def=0x0) // Comparator 1 Input Minus connection configuration bit
    • [8:9]COMP1_INPSEL (def=0x0) // Comparator1 input plus selection bit
    • [11]COMP1_WINMODE (def=0x0) // COMP1_WINMODE
    • [14]COMP1_WINOUT (def=0x0) // COMP1_WINOUT
    • [15]COMP1_POLARITY (def=0x0) // Comparator 1 polarity selection bit
    • [16:17]COMP1_HYST (def=0x0) // Comparator 1 hysteresis selection bits
    • [18:19]COMP1_PWRMODE (def=0x0) // COMP1_PWRMODE
    • [20:24]COMP1_BLANKSEL (def=0x0) // COMP1_BLANKSEL
    • [30]COMP1_VALUE (def=0x0) // Comparator 1 output status bit
    • [31]COMP1_LOCK (def=0x0) // COMP1_CSR register lock bit
  • 0x46005404COMP2_CSR// Comparator 2 control and status register

    • [0]COM2_EN (def=0x0) // Comparator 2 enable bit
    • [4:7]COM2_INMSEL (def=0x0) // Comparator 2 Input Minus connection configuration bit
    • [8:9]COM2_INPSEL (def=0x0) // Comparator 2 input plus selection bit
    • [11]COM2_WINMODE (def=0x0) // COM2_WINMODE
    • [14]COM2_WINOUT (def=0x0) // COM2_WINOUT
    • [15]COM2_POLARITY (def=0x0) // Comparator 2 polarity selection bit
    • [16:17]COM2_HYST (def=0x0) // Comparator 2 hysteresis selection bits
    • [18:19]COM2_PWRMODE (def=0x0) // COM2_PWRMODE
    • [20:24]COM2_BLANKSEL (def=0x0) // COM2_BLANKSEL
    • [30]COM2_VALUE (def=0x0) // Comparator 2 output status bit
    • [31]COM2_LOCK (def=0x0) // COMP2_CSR register lock bit
  interrupts:
  • [58] COMP // COMP1 and COMP2 interrupts
• 0x56005400SEC_COMP//

  • 0x56005400COMP1_CSR// Comparator 1 control and status register

    • [0]COMP1_EN (def=0x0) // Comparator 1 enable bit
    • [4:7]COMP1_INMSEL (def=0x0) // Comparator 1 Input Minus connection configuration bit
    • [8:9]COMP1_INPSEL (def=0x0) // Comparator1 input plus selection bit
    • [11]COMP1_WINMODE (def=0x0) // COMP1_WINMODE
    • [14]COMP1_WINOUT (def=0x0) // COMP1_WINOUT
    • [15]COMP1_POLARITY (def=0x0) // Comparator 1 polarity selection bit
    • [16:17]COMP1_HYST (def=0x0) // Comparator 1 hysteresis selection bits
    • [18:19]COMP1_PWRMODE (def=0x0) // COMP1_PWRMODE
    • [20:24]COMP1_BLANKSEL (def=0x0) // COMP1_BLANKSEL
    • [30]COMP1_VALUE (def=0x0) // Comparator 1 output status bit
    • [31]COMP1_LOCK (def=0x0) // COMP1_CSR register lock bit
  • 0x56005404COMP2_CSR// Comparator 2 control and status register

    • [0]COM2_EN (def=0x0) // Comparator 2 enable bit
    • [4:7]COM2_INMSEL (def=0x0) // Comparator 2 Input Minus connection configuration bit
    • [8:9]COM2_INPSEL (def=0x0) // Comparator 2 input plus selection bit
    • [11]COM2_WINMODE (def=0x0) // COM2_WINMODE
    • [14]COM2_WINOUT (def=0x0) // COM2_WINOUT
    • [15]COM2_POLARITY (def=0x0) // Comparator 2 polarity selection bit
    • [16:17]COM2_HYST (def=0x0) // Comparator 2 hysteresis selection bits
    • [18:19]COM2_PWRMODE (def=0x0) // COM2_PWRMODE
    • [20:24]COM2_BLANKSEL (def=0x0) // COM2_BLANKSEL
    • [30]COM2_VALUE (def=0x0) // Comparator 2 output status bit
    • [31]COM2_LOCK (def=0x0) // COMP2_CSR register lock bit
• 0x46007400VREFBUF// Voltage reference buffer

  • 0x46007400VREFBUF_CSR// VREFBUF control and status register

    • [0]ENVR (def=0x0) // ENVR
    • [1]HIZ (def=0x1) // HIZ
    • [3]VRR (def=0x0) // VRR
    • [4:6]VRS (def=0x0) // VRS
  • 0x46007404VREFBUF_CCR// VREFBUF calibration control register

    • [0:5]TRIM (def=0x0) // TRIM
• 0x56007400SEC_VREFBUF//

  • 0x56007400VREFBUF_CSR// VREFBUF control and status register

    • [0]ENVR (def=0x0) // ENVR
    • [1]HIZ (def=0x1) // HIZ
    • [3]VRR (def=0x0) // VRR
    • [4:6]VRS (def=0x0) // VRS
  • 0x56007404VREFBUF_CCR// VREFBUF calibration control register

    • [0:5]TRIM (def=0x0) // TRIM
• 0x40024000TSC// Touch sensing controller

  • 0x40024000CR// control register

    • [28:31]CTPH (def=0x0) // Charge transfer pulse high
    • [24:27]CTPL (def=0x0) // Charge transfer pulse low
    • [17:23]SSD (def=0x0) // Spread spectrum deviation
    • [16]SSE (def=0x0) // Spread spectrum enable
    • [15]SSPSC (def=0x0) // Spread spectrum prescaler
    • [12:14]PGPSC (def=0x0) // pulse generator prescaler
    • [5:7]MCV (def=0x0) // Max count value
    • [4]IODEF (def=0x0) // I/O Default mode
    • [3]SYNCPOL (def=0x0) // Synchronization pin polarity
    • [2]AM (def=0x0) // Acquisition mode
    • [1]START (def=0x0) // Start a new acquisition
    • [0]TSCE (def=0x0) // Touch sensing controller enable
  • 0x40024004IER// interrupt enable register

    • [1]MCEIE (def=0x0) // Max count error interrupt enable
    • [0]EOAIE (def=0x0) // End of acquisition interrupt enable
  • 0x40024008ICR// interrupt clear register

    • [1]MCEIC (def=0x0) // Max count error interrupt clear
    • [0]EOAIC (def=0x0) // End of acquisition interrupt clear
  • 0x4002400CISR// interrupt status register

    • [1]MCEF (def=0x0) // Max count error flag
    • [0]EOAF (def=0x0) // End of acquisition flag
  • 0x40024010IOHCR// I/O hysteresis control register

    • [31]G8_IO4 (def=0x1) // G8_IO4
    • [30]G8_IO3 (def=0x1) // G8_IO3
    • [29]G8_IO2 (def=0x1) // G8_IO2
    • [28]G8_IO1 (def=0x1) // G8_IO1
    • [27]G7_IO4 (def=0x1) // G7_IO4
    • [26]G7_IO3 (def=0x1) // G7_IO3
    • [25]G7_IO2 (def=0x1) // G7_IO2
    • [24]G7_IO1 (def=0x1) // G7_IO1
    • [23]G6_IO4 (def=0x1) // G6_IO4
    • [22]G6_IO3 (def=0x1) // G6_IO3
    • [21]G6_IO2 (def=0x1) // G6_IO2
    • [20]G6_IO1 (def=0x1) // G6_IO1
    • [19]G5_IO4 (def=0x1) // G5_IO4
    • [18]G5_IO3 (def=0x1) // G5_IO3
    • [17]G5_IO2 (def=0x1) // G5_IO2
    • [16]G5_IO1 (def=0x1) // G5_IO1
    • [15]G4_IO4 (def=0x1) // G4_IO4
    • [14]G4_IO3 (def=0x1) // G4_IO3
    • [13]G4_IO2 (def=0x1) // G4_IO2
    • [12]G4_IO1 (def=0x1) // G4_IO1
    • [11]G3_IO4 (def=0x1) // G3_IO4
    • [10]G3_IO3 (def=0x1) // G3_IO3
    • [9]G3_IO2 (def=0x1) // G3_IO2
    • [8]G3_IO1 (def=0x1) // G3_IO1
    • [7]G2_IO4 (def=0x1) // G2_IO4
    • [6]G2_IO3 (def=0x1) // G2_IO3
    • [5]G2_IO2 (def=0x1) // G2_IO2
    • [4]G2_IO1 (def=0x1) // G2_IO1
    • [3]G1_IO4 (def=0x1) // G1_IO4
    • [2]G1_IO3 (def=0x1) // G1_IO3
    • [1]G1_IO2 (def=0x1) // G1_IO2
    • [0]G1_IO1 (def=0x1) // G1_IO1
  • 0x40024018IOASCR// I/O analog switch control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x40024020IOSCR// I/O sampling control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x40024028IOCCR// I/O channel control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x40024030IOGCSR// I/O group control status register

    • [23]G8S (def=0x0) // Analog I/O group x status
    • [22]G7S (def=0x0) // Analog I/O group x status
    • [21]G6S (def=0x0) // Analog I/O group x status
    • [20]G5S (def=0x0) // Analog I/O group x status
    • [19]G4S (def=0x0) // Analog I/O group x status
    • [18]G3S (def=0x0) // Analog I/O group x status
    • [17]G2S (def=0x0) // Analog I/O group x status
    • [16]G1S (def=0x0) // Analog I/O group x status
    • [7]G8E (def=0x0) // Analog I/O group x enable
    • [6]G7E (def=0x0) // Analog I/O group x enable
    • [5]G6E (def=0x0) // Analog I/O group x enable
    • [4]G5E (def=0x0) // Analog I/O group x enable
    • [3]G4E (def=0x0) // Analog I/O group x enable
    • [2]G3E (def=0x0) // Analog I/O group x enable
    • [1]G2E (def=0x0) // Analog I/O group x enable
    • [0]G1E (def=0x0) // Analog I/O group x enable
  • 0x40024034IOG1CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x40024038IOG2CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x4002403CIOG3CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x40024040IOG4CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x40024044IOG5CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x40024048IOG6CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x4002404CIOG7CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x40024050IOG8CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  interrupts:
  • [0] TSC // TSC global interrupt
• 0x50024000SEC_TSC//

  • 0x50024000CR// control register

    • [28:31]CTPH (def=0x0) // Charge transfer pulse high
    • [24:27]CTPL (def=0x0) // Charge transfer pulse low
    • [17:23]SSD (def=0x0) // Spread spectrum deviation
    • [16]SSE (def=0x0) // Spread spectrum enable
    • [15]SSPSC (def=0x0) // Spread spectrum prescaler
    • [12:14]PGPSC (def=0x0) // pulse generator prescaler
    • [5:7]MCV (def=0x0) // Max count value
    • [4]IODEF (def=0x0) // I/O Default mode
    • [3]SYNCPOL (def=0x0) // Synchronization pin polarity
    • [2]AM (def=0x0) // Acquisition mode
    • [1]START (def=0x0) // Start a new acquisition
    • [0]TSCE (def=0x0) // Touch sensing controller enable
  • 0x50024004IER// interrupt enable register

    • [1]MCEIE (def=0x0) // Max count error interrupt enable
    • [0]EOAIE (def=0x0) // End of acquisition interrupt enable
  • 0x50024008ICR// interrupt clear register

    • [1]MCEIC (def=0x0) // Max count error interrupt clear
    • [0]EOAIC (def=0x0) // End of acquisition interrupt clear
  • 0x5002400CISR// interrupt status register

    • [1]MCEF (def=0x0) // Max count error flag
    • [0]EOAF (def=0x0) // End of acquisition flag
  • 0x50024010IOHCR// I/O hysteresis control register

    • [31]G8_IO4 (def=0x1) // G8_IO4
    • [30]G8_IO3 (def=0x1) // G8_IO3
    • [29]G8_IO2 (def=0x1) // G8_IO2
    • [28]G8_IO1 (def=0x1) // G8_IO1
    • [27]G7_IO4 (def=0x1) // G7_IO4
    • [26]G7_IO3 (def=0x1) // G7_IO3
    • [25]G7_IO2 (def=0x1) // G7_IO2
    • [24]G7_IO1 (def=0x1) // G7_IO1
    • [23]G6_IO4 (def=0x1) // G6_IO4
    • [22]G6_IO3 (def=0x1) // G6_IO3
    • [21]G6_IO2 (def=0x1) // G6_IO2
    • [20]G6_IO1 (def=0x1) // G6_IO1
    • [19]G5_IO4 (def=0x1) // G5_IO4
    • [18]G5_IO3 (def=0x1) // G5_IO3
    • [17]G5_IO2 (def=0x1) // G5_IO2
    • [16]G5_IO1 (def=0x1) // G5_IO1
    • [15]G4_IO4 (def=0x1) // G4_IO4
    • [14]G4_IO3 (def=0x1) // G4_IO3
    • [13]G4_IO2 (def=0x1) // G4_IO2
    • [12]G4_IO1 (def=0x1) // G4_IO1
    • [11]G3_IO4 (def=0x1) // G3_IO4
    • [10]G3_IO3 (def=0x1) // G3_IO3
    • [9]G3_IO2 (def=0x1) // G3_IO2
    • [8]G3_IO1 (def=0x1) // G3_IO1
    • [7]G2_IO4 (def=0x1) // G2_IO4
    • [6]G2_IO3 (def=0x1) // G2_IO3
    • [5]G2_IO2 (def=0x1) // G2_IO2
    • [4]G2_IO1 (def=0x1) // G2_IO1
    • [3]G1_IO4 (def=0x1) // G1_IO4
    • [2]G1_IO3 (def=0x1) // G1_IO3
    • [1]G1_IO2 (def=0x1) // G1_IO2
    • [0]G1_IO1 (def=0x1) // G1_IO1
  • 0x50024018IOASCR// I/O analog switch control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x50024020IOSCR// I/O sampling control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x50024028IOCCR// I/O channel control register

    • [31]G8_IO4 (def=0x0) // G8_IO4
    • [30]G8_IO3 (def=0x0) // G8_IO3
    • [29]G8_IO2 (def=0x0) // G8_IO2
    • [28]G8_IO1 (def=0x0) // G8_IO1
    • [27]G7_IO4 (def=0x0) // G7_IO4
    • [26]G7_IO3 (def=0x0) // G7_IO3
    • [25]G7_IO2 (def=0x0) // G7_IO2
    • [24]G7_IO1 (def=0x0) // G7_IO1
    • [23]G6_IO4 (def=0x0) // G6_IO4
    • [22]G6_IO3 (def=0x0) // G6_IO3
    • [21]G6_IO2 (def=0x0) // G6_IO2
    • [20]G6_IO1 (def=0x0) // G6_IO1
    • [19]G5_IO4 (def=0x0) // G5_IO4
    • [18]G5_IO3 (def=0x0) // G5_IO3
    • [17]G5_IO2 (def=0x0) // G5_IO2
    • [16]G5_IO1 (def=0x0) // G5_IO1
    • [15]G4_IO4 (def=0x0) // G4_IO4
    • [14]G4_IO3 (def=0x0) // G4_IO3
    • [13]G4_IO2 (def=0x0) // G4_IO2
    • [12]G4_IO1 (def=0x0) // G4_IO1
    • [11]G3_IO4 (def=0x0) // G3_IO4
    • [10]G3_IO3 (def=0x0) // G3_IO3
    • [9]G3_IO2 (def=0x0) // G3_IO2
    • [8]G3_IO1 (def=0x0) // G3_IO1
    • [7]G2_IO4 (def=0x0) // G2_IO4
    • [6]G2_IO3 (def=0x0) // G2_IO3
    • [5]G2_IO2 (def=0x0) // G2_IO2
    • [4]G2_IO1 (def=0x0) // G2_IO1
    • [3]G1_IO4 (def=0x0) // G1_IO4
    • [2]G1_IO3 (def=0x0) // G1_IO3
    • [1]G1_IO2 (def=0x0) // G1_IO2
    • [0]G1_IO1 (def=0x0) // G1_IO1
  • 0x50024030IOGCSR// I/O group control status register

    • [23]G8S (def=0x0) // Analog I/O group x status
    • [22]G7S (def=0x0) // Analog I/O group x status
    • [21]G6S (def=0x0) // Analog I/O group x status
    • [20]G5S (def=0x0) // Analog I/O group x status
    • [19]G4S (def=0x0) // Analog I/O group x status
    • [18]G3S (def=0x0) // Analog I/O group x status
    • [17]G2S (def=0x0) // Analog I/O group x status
    • [16]G1S (def=0x0) // Analog I/O group x status
    • [7]G8E (def=0x0) // Analog I/O group x enable
    • [6]G7E (def=0x0) // Analog I/O group x enable
    • [5]G6E (def=0x0) // Analog I/O group x enable
    • [4]G5E (def=0x0) // Analog I/O group x enable
    • [3]G4E (def=0x0) // Analog I/O group x enable
    • [2]G3E (def=0x0) // Analog I/O group x enable
    • [1]G2E (def=0x0) // Analog I/O group x enable
    • [0]G1E (def=0x0) // Analog I/O group x enable
  • 0x50024034IOG1CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x50024038IOG2CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x5002403CIOG3CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x50024040IOG4CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x50024044IOG5CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x50024048IOG6CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x5002404CIOG7CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
  • 0x50024050IOG8CR// I/O group x counter register

    • [0:13]CNT (def=0x0) // Counter value
• 0x4000DC00UCPD1// USB Power Delivery interface

  • 0x4000DC00UCPD_CFGR1// UCPD configuration register 1

    • [0:5]HBITCLKDIV (def=0x0) // Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfiel
    • [6:10]IFRGAP (def=0x0) // Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio
    • [11:15]TRANSWIN (def=0x0) // Transition window duration The bitfield determines the division ratio (the bitfield value minus one
    • [17:19]PSC_USBPDCLK (def=0x0) // Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a k
    • [20:28]RXORDSETEN (def=0x0) // Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver mus
    • [29]TXDMAEN (def=0x0) // Transmission DMA mode enable When set, the bit enables DMA mode for transmission.
    • [30]RXDMAEN (def=0x0) // Reception DMA mode enable When set, the bit enables DMA mode for reception.
    • [31]UCPDEN (def=0x0) // UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instan
  • 0x4000DC04UCPD_CFGR2// UCPD configuration register 2

    • [0]RXFILTDIS (def=0x0) // BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-sca
    • [1]RXFILT2N3 (def=0x0) // BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirmin
    • [2]FORCECLK (def=0x0) // Force ClkReq clock request
    • [3]WUPEN (def=0x0) // Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
  • 0x4000DC08UCPD_CFGR3// UCPD configuration register 3

    • [0:3]TRIM1_NG_CCRPD (def=0x0) // SW trim value for RPD resistors on the CC1 line
    • [9:12]TRIM1_NG_CC3A0 (def=0x0) // SW trim value for Iref on the CC1 line
    • [16:19]TRIM2_NG_CCRPD (def=0x0) // SW trim value for RPD resistors on the CC2 line
    • [25:28]TRIM2_NG_CC3A0 (def=0x0) // SW trim value for Iref on the CC2 line
  • 0x4000DC0CUCPD_CR// UCPD control register

    • [0:1]TXMODE (def=0x0) // Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Othe
    • [2]TXSEND (def=0x0) // Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begin
    • [3]TXHRST (def=0x0) // Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission
    • [4]RXMODE (def=0x0) // Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally,
    • [5]PHYRXEN (def=0x0) // USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared.
    • [6]PHYCCSEL (def=0x0) // CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientati
    • [7:8]ANASUBMODE (def=0x0) // Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.
    • [9]ANAMODE (def=0x0) // Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE
    • [10:11]CCENABLE (def=0x0) // CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) accordi
    • [13]CC1VCONNEN (def=0x0) // VCONN switch enable for CC1
    • [14]CC2VCONNEN (def=0x0) // VCONN switch enable for CC2
    • [16]FRSRXEN (def=0x0) // FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line s
    • [17]FRSTX (def=0x0) // FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware a
    • [18]RDCH (def=0x0) // Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit
    • [20]CC1TCDIS (def=0x0) // CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the
    • [21]CC2TCDIS (def=0x0) // CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the
  • 0x4000DC10UCPD_IMR// UCPD interrupt mask register

    • [0]TXISIE (def=0x0) // TXIS interrupt enable
    • [1]TXMSGDISCIE (def=0x0) // TXMSGDISC interrupt enable
    • [2]TXMSGSENTIE (def=0x0) // TXMSGSENT interrupt enable
    • [3]TXMSGABTIE (def=0x0) // TXMSGABT interrupt enable
    • [4]HRSTDISCIE (def=0x0) // HRSTDISC interrupt enable
    • [5]HRSTSENTIE (def=0x0) // HRSTSENT interrupt enable
    • [6]TXUNDIE (def=0x0) // TXUND interrupt enable
    • [8]RXNEIE (def=0x0) // RXNE interrupt enable
    • [9]RXORDDETIE (def=0x0) // RXORDDET interrupt enable
    • [10]RXHRSTDETIE (def=0x0) // RXHRSTDET interrupt enable
    • [11]RXOVRIE (def=0x0) // RXOVR interrupt enable
    • [12]RXMSGENDIE (def=0x0) // RXMSGEND interrupt enable
    • [14]TYPECEVT1IE (def=0x0) // TYPECEVT1 interrupt enable
    • [15]TYPECEVT2IE (def=0x0) // TYPECEVT2 interrupt enable
    • [20]FRSEVTIE (def=0x0) // FRSEVT interrupt enable
  • 0x4000DC14UCPD_SR// UCPD status register

    • [0]TXIS (def=0x0) // Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data writ
    • [1]TXMSGDISC (def=0x0) // Message transmission discarded The flag indicates that a message transmission was dropped. The flag
    • [2]TXMSGSENT (def=0x0) // Message transmission completed The flag indicates the completion of packet transmission. It is clea
    • [3]TXMSGABT (def=0x0) // Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Res
    • [4]HRSTDISC (def=0x0) // Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is clear
    • [5]HRSTSENT (def=0x0) // Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared
    • [6]TXUND (def=0x0) // Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written
    • [8]RXNE (def=0x0) // Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not emp
    • [9]RXORDDET (def=0x0) // Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The releva
    • [10]RXHRSTDET (def=0x0) // Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is c
    • [11]RXOVR (def=0x0) // Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the
    • [12]RXMSGEND (def=0x0) // Rx message received The flag indicates whether a message (except Hard Reset message) has been recei
    • [13]RXERR (def=0x0) // Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), suc
    • [14]TYPECEVT1 (def=0x0) // Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bit
    • [15]TYPECEVT2 (def=0x0) // Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bit
    • [16:17]TYPEC_VSTATE_CC1 (def=0x0) // The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage va
    • [18:19]TYPEC_VSTATE_CC2 (def=0x0) // CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its stead
    • [20]FRSEVT (def=0x0) // FRS detection event The flag is cleared by setting the FRSEVTCF bit.
  • 0x4000DC18UCPD_ICR// UCPD interrupt clear register

    • [1]TXMSGDISCCF (def=0x0) // Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the UCPD_SR
    • [2]TXMSGSENTCF (def=0x0) // Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the UCPD_SR reg
    • [3]TXMSGABTCF (def=0x0) // Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the UCPD_SR regi
    • [4]HRSTDISCCF (def=0x0) // Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the UCPD_SR re
    • [5]HRSTSENTCF (def=0x0) // Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the UCPD_SR regis
    • [6]TXUNDCF (def=0x0) // Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the UCPD_SR register.
    • [9]RXORDDETCF (def=0x0) // Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the UCPD_SR
    • [10]RXHRSTDETCF (def=0x0) // Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the UCPD_S
    • [11]RXOVRCF (def=0x0) // Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the UCPD_SR register.
    • [12]RXMSGENDCF (def=0x0) // Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the UCPD_SR r
    • [14]TYPECEVT1CF (def=0x0) // Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the UCPD_SR re
    • [15]TYPECEVT2CF (def=0x0) // Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the UCPD_
    • [20]FRSEVTCF (def=0x0) // FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the UCPD_SR register.
  • 0x4000DC1CUCPD_TX_ORDSETR// UCPD Tx ordered set type register

    • [0:19]TXORDSET (def=0x0) // Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of f
  • 0x4000DC20UCPD_TX_PAYSZR// UCPD Tx payload size register

    • [0:9]TXPAYSZ (def=0x0) // Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the
  • 0x4000DC24UCPD_TXDR// UCPD Tx data register

    • [0:7]TXDATA (def=0x0) // Data byte to transmit
  • 0x4000DC28UCPD_RX_ORDSETR//

    • [0:2]RXORDSET (def=0x0) // Rx ordered set code detected
    • [3]RXSOP3OF4 (def=0x0) // The bit indicates the number of correct K‑codes. For debug purposes only.
    • [4:6]RXSOPKINVALID (def=0x0) // The bitfield is for debug purposes only. Others: Invalid
  • 0x4000DC2CUCPD_RX_PAYSZR//

    • [0:9]RXPAYSZ (def=0x0) // Rx payload size received This bitfield contains the number of bytes of a payload (including header
  • 0x4000DC30UCPD_RXDR//

    • [0:7]RXDATA (def=0x0) // Data byte received
  • 0x4000DC34UCPD_RX_ORDEXTR1// UCPD Rx ordered set extension register 1

    • [0:19]RXSOPX1 (def=0x0) // Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K�
  • 0x4000DC38UCPD_RX_ORDEXTR2// UCPD Rx ordered set extension register 2

    • [0:19]RXSOPX2 (def=0x0) // Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K�
  interrupts:
  • [106] UCPD1 // UCPD1 global interrupt
• 0x5000DC00SEC_UCPD1//

  • 0x5000DC00UCPD_CFGR1// UCPD configuration register 1

    • [0:5]HBITCLKDIV (def=0x0) // Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfiel
    • [6:10]IFRGAP (def=0x0) // Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio
    • [11:15]TRANSWIN (def=0x0) // Transition window duration The bitfield determines the division ratio (the bitfield value minus one
    • [17:19]PSC_USBPDCLK (def=0x0) // Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a k
    • [20:28]RXORDSETEN (def=0x0) // Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver mus
    • [29]TXDMAEN (def=0x0) // Transmission DMA mode enable When set, the bit enables DMA mode for transmission.
    • [30]RXDMAEN (def=0x0) // Reception DMA mode enable When set, the bit enables DMA mode for reception.
    • [31]UCPDEN (def=0x0) // UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instan
  • 0x5000DC04UCPD_CFGR2// UCPD configuration register 2

    • [0]RXFILTDIS (def=0x0) // BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-sca
    • [1]RXFILT2N3 (def=0x0) // BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirmin
    • [2]FORCECLK (def=0x0) // Force ClkReq clock request
    • [3]WUPEN (def=0x0) // Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
  • 0x5000DC08UCPD_CFGR3// UCPD configuration register 3

    • [0:3]TRIM1_NG_CCRPD (def=0x0) // SW trim value for RPD resistors on the CC1 line
    • [9:12]TRIM1_NG_CC3A0 (def=0x0) // SW trim value for Iref on the CC1 line
    • [16:19]TRIM2_NG_CCRPD (def=0x0) // SW trim value for RPD resistors on the CC2 line
    • [25:28]TRIM2_NG_CC3A0 (def=0x0) // SW trim value for Iref on the CC2 line
  • 0x5000DC0CUCPD_CR// UCPD control register

    • [0:1]TXMODE (def=0x0) // Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Othe
    • [2]TXSEND (def=0x0) // Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begin
    • [3]TXHRST (def=0x0) // Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission
    • [4]RXMODE (def=0x0) // Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally,
    • [5]PHYRXEN (def=0x0) // USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared.
    • [6]PHYCCSEL (def=0x0) // CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientati
    • [7:8]ANASUBMODE (def=0x0) // Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.
    • [9]ANAMODE (def=0x0) // Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE
    • [10:11]CCENABLE (def=0x0) // CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) accordi
    • [13]CC1VCONNEN (def=0x0) // VCONN switch enable for CC1
    • [14]CC2VCONNEN (def=0x0) // VCONN switch enable for CC2
    • [16]FRSRXEN (def=0x0) // FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line s
    • [17]FRSTX (def=0x0) // FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware a
    • [18]RDCH (def=0x0) // Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit
    • [20]CC1TCDIS (def=0x0) // CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the
    • [21]CC2TCDIS (def=0x0) // CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the
  • 0x5000DC10UCPD_IMR// UCPD interrupt mask register

    • [0]TXISIE (def=0x0) // TXIS interrupt enable
    • [1]TXMSGDISCIE (def=0x0) // TXMSGDISC interrupt enable
    • [2]TXMSGSENTIE (def=0x0) // TXMSGSENT interrupt enable
    • [3]TXMSGABTIE (def=0x0) // TXMSGABT interrupt enable
    • [4]HRSTDISCIE (def=0x0) // HRSTDISC interrupt enable
    • [5]HRSTSENTIE (def=0x0) // HRSTSENT interrupt enable
    • [6]TXUNDIE (def=0x0) // TXUND interrupt enable
    • [8]RXNEIE (def=0x0) // RXNE interrupt enable
    • [9]RXORDDETIE (def=0x0) // RXORDDET interrupt enable
    • [10]RXHRSTDETIE (def=0x0) // RXHRSTDET interrupt enable
    • [11]RXOVRIE (def=0x0) // RXOVR interrupt enable
    • [12]RXMSGENDIE (def=0x0) // RXMSGEND interrupt enable
    • [14]TYPECEVT1IE (def=0x0) // TYPECEVT1 interrupt enable
    • [15]TYPECEVT2IE (def=0x0) // TYPECEVT2 interrupt enable
    • [20]FRSEVTIE (def=0x0) // FRSEVT interrupt enable
  • 0x5000DC14UCPD_SR// UCPD status register

    • [0]TXIS (def=0x0) // Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data writ
    • [1]TXMSGDISC (def=0x0) // Message transmission discarded The flag indicates that a message transmission was dropped. The flag
    • [2]TXMSGSENT (def=0x0) // Message transmission completed The flag indicates the completion of packet transmission. It is clea
    • [3]TXMSGABT (def=0x0) // Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Res
    • [4]HRSTDISC (def=0x0) // Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is clear
    • [5]HRSTSENT (def=0x0) // Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared
    • [6]TXUND (def=0x0) // Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written
    • [8]RXNE (def=0x0) // Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not emp
    • [9]RXORDDET (def=0x0) // Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The releva
    • [10]RXHRSTDET (def=0x0) // Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is c
    • [11]RXOVR (def=0x0) // Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the
    • [12]RXMSGEND (def=0x0) // Rx message received The flag indicates whether a message (except Hard Reset message) has been recei
    • [13]RXERR (def=0x0) // Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), suc
    • [14]TYPECEVT1 (def=0x0) // Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bit
    • [15]TYPECEVT2 (def=0x0) // Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bit
    • [16:17]TYPEC_VSTATE_CC1 (def=0x0) // The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage va
    • [18:19]TYPEC_VSTATE_CC2 (def=0x0) // CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its stead
    • [20]FRSEVT (def=0x0) // FRS detection event The flag is cleared by setting the FRSEVTCF bit.
  • 0x5000DC18UCPD_ICR// UCPD interrupt clear register

    • [1]TXMSGDISCCF (def=0x0) // Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the UCPD_SR
    • [2]TXMSGSENTCF (def=0x0) // Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the UCPD_SR reg
    • [3]TXMSGABTCF (def=0x0) // Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the UCPD_SR regi
    • [4]HRSTDISCCF (def=0x0) // Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the UCPD_SR re
    • [5]HRSTSENTCF (def=0x0) // Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the UCPD_SR regis
    • [6]TXUNDCF (def=0x0) // Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the UCPD_SR register.
    • [9]RXORDDETCF (def=0x0) // Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the UCPD_SR
    • [10]RXHRSTDETCF (def=0x0) // Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the UCPD_S
    • [11]RXOVRCF (def=0x0) // Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the UCPD_SR register.
    • [12]RXMSGENDCF (def=0x0) // Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the UCPD_SR r
    • [14]TYPECEVT1CF (def=0x0) // Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the UCPD_SR re
    • [15]TYPECEVT2CF (def=0x0) // Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the UCPD_
    • [20]FRSEVTCF (def=0x0) // FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the UCPD_SR register.
  • 0x5000DC1CUCPD_TX_ORDSETR// UCPD Tx ordered set type register

    • [0:19]TXORDSET (def=0x0) // Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of f
  • 0x5000DC20UCPD_TX_PAYSZR// UCPD Tx payload size register

    • [0:9]TXPAYSZ (def=0x0) // Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the
  • 0x5000DC24UCPD_TXDR// UCPD Tx data register

    • [0:7]TXDATA (def=0x0) // Data byte to transmit
  • 0x5000DC28UCPD_RX_ORDSETR//

    • [0:2]RXORDSET (def=0x0) // Rx ordered set code detected
    • [3]RXSOP3OF4 (def=0x0) // The bit indicates the number of correct K‑codes. For debug purposes only.
    • [4:6]RXSOPKINVALID (def=0x0) // The bitfield is for debug purposes only. Others: Invalid
  • 0x5000DC2CUCPD_RX_PAYSZR//

    • [0:9]RXPAYSZ (def=0x0) // Rx payload size received This bitfield contains the number of bytes of a payload (including header
  • 0x5000DC30UCPD_RXDR//

    • [0:7]RXDATA (def=0x0) // Data byte received
  • 0x5000DC34UCPD_RX_ORDEXTR1// UCPD Rx ordered set extension register 1

    • [0:19]RXSOPX1 (def=0x0) // Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K�
  • 0x5000DC38UCPD_RX_ORDEXTR2// UCPD Rx ordered set extension register 2

    • [0:19]RXSOPX2 (def=0x0) // Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K�
• 0x4000AC00FDCAN1_RAM// FDCAN1_RAM

  • 0x4000AC00FDCAN_CREL// FDCAN Core Release Register

    • [28:31]REL (def=0x3) // Core release
    • [24:27]STEP (def=0x2) // Step of Core release
    • [20:23]SUBSTEP (def=0x1) // Sub-step of Core release
    • [16:19]YEAR (def=0x4) // Timestamp Year
    • [8:15]MON (def=0x12) // Timestamp Month
    • [0:7]DAY (def=0x18) // Timestamp Day
  • 0x4000AC04FDCAN_ENDN// FDCAN endian register

    • [0:31]ETV (def=0x87654321) // Endiannes Test Value
  • 0x4000AC0CFDCAN_DBTP// FDCAN Data Bit Timing and Prescaler Register

    • [0:3]DSJW (def=0x3) // Synchronization Jump Width
    • [4:7]DTSEG2 (def=0x3) // Data time segment after sample point
    • [8:12]DTSEG1 (def=0xA) // Data time segment after sample point
    • [16:20]DBRP (def=0x0) // Data BIt Rate Prescaler
    • [23]TDC (def=0x0) // Transceiver Delay Compensation
  • 0x4000AC10FDCAN_TEST// FDCAN Test Register

    • [4]LBCK (def=0x0) // Loop Back mode
    • [5:6]TX (def=0x0) // Loop Back mode
    • [7]RX (def=0x0) // Control of Transmit Pin
  • 0x4000AC14FDCAN_RWD// FDCAN RAM Watchdog Register

    • [8:15]WDV (def=0x0) // Watchdog value
    • [0:7]WDC (def=0x0) // Watchdog configuration
  • 0x4000AC18FDCAN_CCCR// FDCAN CC Control Register

    • [0]INIT (def=0x1) // Initialization
    • [1]CCE (def=0x0) // Configuration Change Enable
    • [2]ASM (def=0x0) // ASM Restricted Operation Mode
    • [3]CSA (def=0x0) // Clock Stop Acknowledge
    • [4]CSR (def=0x0) // Clock Stop Request
    • [5]MON (def=0x0) // Bus Monitoring Mode
    • [6]DAR (def=0x0) // Disable Automatic Retransmission
    • [7]TEST (def=0x0) // Test Mode Enable
    • [8]FDOE (def=0x0) // FD Operation Enable
    • [9]BRSE (def=0x0) // FDCAN Bit Rate Switching
    • [12]PXHD (def=0x0) // Protocol Exception Handling Disable
    • [13]EFBI (def=0x0) // Edge Filtering during Bus Integration
    • [14]TXP (def=0x0) // TXP
    • [15]NISO (def=0x0) // Non ISO Operation
  • 0x4000AC1CFDCAN_NBTP// FDCAN Nominal Bit Timing and Prescaler Register

    • [25:31]NSJW (def=0x3) // Nominal (Re)Synchronization Jump Width
    • [16:24]NBRP (def=0x0) // Bit Rate Prescaler
    • [8:15]NTSEG1 (def=0xA) // Nominal Time segment before sample point
    • [0:6]NTSEG2 (def=0x3) // Nominal Time segment after sample point
  • 0x4000AC20FDCAN_TSCC// FDCAN Timestamp Counter Configuration Register

    • [16:19]TCP (def=0x0) // Timestamp Counter Prescaler
    • [0:1]TSS (def=0x0) // Timestamp Select
  • 0x4000AC24FDCAN_TSCV// FDCAN Timestamp Counter Value Register

    • [0:15]TSC (def=0x0) // Timestamp Counter
  • 0x4000AC28FDCAN_TOCC// FDCAN Timeout Counter Configuration Register

    • [0]ETOC (def=0x0) // Enable Timeout Counter
    • [1:2]TOS (def=0x0) // Timeout Select
    • [16:31]TOP (def=0xFFFF) // Timeout Period
  • 0x4000AC2CFDCAN_TOCV// FDCAN Timeout Counter Value Register

    • [0:15]TOC (def=0xFFFF) // Timeout Counter
  • 0x4000AC40FDCAN_ECR// FDCAN Error Counter Register

    • [16:23]CEL (def=0x0) // AN Error Logging
    • [15]RP (def=0x0) // Receive Error Passive
    • [8:14]REC (def=0x0) // Receive Error Counter
    • [0:7]TEC (def=0x0) // Transmit Error Counter
  • 0x4000AC44FDCAN_PSR// FDCAN Protocol Status Register

    • [0:2]LEC (def=0x7) // Last Error Code
    • [3:4]ACT (def=0x0) // Activity
    • [5]EP (def=0x0) // Error Passive
    • [6]EW (def=0x0) // Warning Status
    • [7]BO (def=0x0) // Bus_Off Status
    • [8:10]DLEC (def=0x7) // Data Last Error Code
    • [11]RESI (def=0x0) // ESI flag of last received FDCAN Message
    • [12]RBRS (def=0x0) // BRS flag of last received FDCAN Message
    • [13]REDL (def=0x0) // Received FDCAN Message
    • [14]PXE (def=0x0) // Protocol Exception Event
    • [16:22]TDCV (def=0x0) // Transmitter Delay Compensation Value
  • 0x4000AC48FDCAN_TDCR// FDCAN Transmitter Delay Compensation Register

    • [0:6]TDCF (def=0x0) // Transmitter Delay Compensation Filter Window Length
    • [8:14]TDCO (def=0x0) // Transmitter Delay Compensation Offset
  • 0x4000AC50FDCAN_IR// FDCAN Interrupt Register

    • [0]RF0N (def=0x0) // RF0N
    • [1]RF0F (def=0x0) // RF0F
    • [2]RF0L (def=0x0) // RF0L
    • [3]RF1N (def=0x0) // RF1N
    • [4]RF1F (def=0x0) // RF1F
    • [5]RF1L (def=0x0) // RF1L
    • [6]HPM (def=0x0) // HPM
    • [7]TC (def=0x0) // TC
    • [8]TCF (def=0x0) // TCF
    • [9]TFE (def=0x0) // TFE
    • [10]TEFN (def=0x0) // TEFN
    • [11]TEFF (def=0x0) // TEFF
    • [12]TEFL (def=0x0) // TEFL
    • [13]TSW (def=0x0) // TSW
    • [14]MRAF (def=0x0) // MRAF
    • [15]TOO (def=0x0) // TOO
    • [16]ELO (def=0x0) // ELO
    • [17]EP (def=0x0) // EP
    • [18]EW (def=0x0) // EW
    • [19]BO (def=0x0) // BO
    • [20]WDI (def=0x0) // WDI
    • [21]PEA (def=0x0) // PEA
    • [22]PED (def=0x0) // PED
    • [23]ARA (def=0x0) // ARA
  • 0x4000AC54FDCAN_IE// FDCAN Interrupt Enable Register

    • [0]RF0NE (def=0x0) // Rx FIFO 0 New Message Enable
    • [1]RF0FE (def=0x0) // Rx FIFO 0 Full Enable
    • [2]RF0LE (def=0x0) // Rx FIFO 0 Message Lost Enable
    • [3]RF1NE (def=0x0) // Rx FIFO 1 New Message Enable
    • [4]RF1FE (def=0x0) // Rx FIFO 1 Watermark Reached Enable
    • [5]RF1LE (def=0x0) // Rx FIFO 1 Message Lost Enable
    • [6]HPME (def=0x0) // High Priority Message Enable
    • [7]TCE (def=0x0) // Transmission Completed Enable
    • [8]TCFE (def=0x0) // Transmission Cancellation Finished Enable
    • [9]TEFE (def=0x0) // Tx FIFO Empty Enable
    • [10]TEFNE (def=0x0) // Tx Event FIFO New Entry Enable
    • [11]TEFFE (def=0x0) // Tx Event FIFO Full Enable
    • [12]TEFLE (def=0x0) // Tx Event FIFO Element Lost Enable
    • [13]TSWE (def=0x0) // TSWE
    • [14]MRAFE (def=0x0) // Message RAM Access Failure Enable
    • [15]TOOE (def=0x0) // Timeout Occurred Enable
    • [16]ELOE (def=0x0) // Error Logging Overflow Enable
    • [17]EPE (def=0x0) // Error Passive Enable
    • [18]EWE (def=0x0) // Warning Status Enable
    • [19]BOE (def=0x0) // Bus_Off Status Enable
    • [20]WDIE (def=0x0) // Watchdog Interrupt Enable
    • [21]PEAE (def=0x0) // Protocol Error in Arbitration Phase Enable
    • [22]PEDE (def=0x0) // Protocol Error in Data Phase Enable
    • [23]ARAE (def=0x0) // Access to Reserved Address Enable
  • 0x4000AC58FDCAN_ILS// FDCAN Interrupt Line Select Register

    • [0]RxFIFO0 (def=0x0) // RxFIFO0
    • [1]RxFIFO1 (def=0x0) // RxFIFO1
    • [2]SMSG (def=0x0) // SMSG
    • [3]TFERR (def=0x0) // TFERR
    • [4]MISC (def=0x0) // MISC
    • [5]BERR (def=0x0) // BERR
    • [6]PERR (def=0x0) // PERR
  • 0x4000AC5CFDCAN_ILE// FDCAN Interrupt Line Enable Register

    • [0]EINT0 (def=0x0) // Enable Interrupt Line 0
    • [1]EINT1 (def=0x0) // Enable Interrupt Line 1
  • 0x4000AC80FDCAN_RXGFC// FDCAN Global Filter Configuration Register

    • [0]RRFE (def=0x0) // Reject Remote Frames Extended
    • [1]RRFS (def=0x0) // Reject Remote Frames Standard
    • [2:3]ANFE (def=0x0) // Accept Non-matching Frames Extended
    • [4:5]ANFS (def=0x0) // Accept Non-matching Frames Standard
    • [8]F1OM (def=0x0) // F1OM
    • [9]F0OM (def=0x0) // F0OM
    • [16:20]LSS (def=0x0) // LSS
    • [24:27]LSE (def=0x0) // LSE
  • 0x4000AC84FDCAN_XIDAM// FDCAN Extended ID and Mask Register

    • [0:28]EIDM (def=0x1FFFFFFF) // Extended ID Mask
  • 0x4000AC88FDCAN_HPMS// FDCAN High Priority Message Status Register

    • [0:2]BIDX (def=0x0) // Buffer Index
    • [6:7]MSI (def=0x0) // Message Storage Indicator
    • [8:12]FIDX (def=0x0) // Filter Index
    • [15]FLST (def=0x0) // Filter List
  • 0x4000AC90FDCAN_RXF0S// FDCAN Rx FIFO 0 Status Register

    • [0:3]F0FL (def=0x0) // Rx FIFO 0 Fill Level
    • [8:9]F0GI (def=0x0) // Rx FIFO 0 Get Index
    • [16:17]F0PI (def=0x0) // Rx FIFO 0 Put Index
    • [24]F0F (def=0x0) // Rx FIFO 0 Full
    • [25]RF0L (def=0x0) // Rx FIFO 0 Message Lost
  • 0x4000AC94FDCAN_RXF0A// CAN Rx FIFO 0 Acknowledge Register

    • [0:2]F0AI (def=0x0) // Rx FIFO 0 Acknowledge Index
  • 0x4000AC98FDCAN_RXF1S// FDCAN Rx FIFO 1 Status Register

    • [0:3]F1FL (def=0x0) // Rx FIFO 1 Fill Level
    • [8:9]F1GI (def=0x0) // Rx FIFO 1 Get Index
    • [16:17]F1PI (def=0x0) // Rx FIFO 1 Put Index
    • [24]F1F (def=0x0) // Rx FIFO 1 Full
    • [25]RF1L (def=0x0) // Rx FIFO 1 Message Lost
  • 0x4000AC9CFDCAN_RXF1A// FDCAN Rx FIFO 1 Acknowledge Register

    • [0:2]F1AI (def=0x0) // Rx FIFO 1 Acknowledge Index
  • 0x4000ACC0FDCAN_TXBC// FDCAN Tx buffer configuration register

    • [24]TFQM (def=0x0) // Tx FIFO/Queue Mode
  • 0x4000ACC4FDCAN_TXFQS// FDCAN Tx FIFO/Queue Status Register

    • [0:2]TFFL (def=0x3) // Tx FIFO Free Level
    • [8:9]TFGI (def=0x0) // TFGI
    • [16:17]TFQPI (def=0x0) // Tx FIFO/Queue Put Index
    • [21]TFQF (def=0x0) // Tx FIFO/Queue Full
  • 0x4000ACC8FDCAN_TXBRP// FDCAN Tx Buffer Request Pending Register

    • [0:2]TRP (def=0x0) // Transmission Request Pending
  • 0x4000ACCCFDCAN_TXBAR// FDCAN Tx Buffer Add Request Register

    • [0:2]AR (def=0x0) // Add Request
  • 0x4000ACD0FDCAN_TXBCR// FDCAN Tx Buffer Cancellation Request Register

    • [0:2]CR (def=0x0) // Cancellation Request
  • 0x4000ACD4FDCAN_TXBTO// FDCAN Tx Buffer Transmission Occurred Register

    • [0:2]TO (def=0x0) // Transmission Occurred.
  • 0x4000ACD8FDCAN_TXBCF// FDCAN Tx Buffer Cancellation Finished Register

    • [0:2]CF (def=0x0) // Cancellation Finished
  • 0x4000ACDCFDCAN_TXBTIE// FDCAN Tx Buffer Transmission Interrupt Enable Register

    • [0:2]TIE (def=0x0) // Transmission Interrupt Enable
  • 0x4000ACE0FDCAN_TXBCIE// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

    • [0:2]CFIE (def=0x0) // Cancellation Finished Interrupt Enable
  • 0x4000ACE4FDCAN_TXEFS// FDCAN Tx Event FIFO Status Register

    • [0:2]EFFL (def=0x0) // Event FIFO Fill Level
    • [8:9]EFGI (def=0x0) // Event FIFO Get Index.
    • [16:17]EFPI (def=0x0) // Event FIFO Put Index
    • [24]EFF (def=0x0) // Event FIFO Full.
    • [25]TEFL (def=0x0) // Tx Event FIFO Element Lost.
  • 0x4000ACE8FDCAN_TXEFA// FDCAN Tx Event FIFO Acknowledge Register

    • [0:1]EFAI (def=0x0) // Event FIFO Acknowledge Index
  • 0x4000AD00FDCAN_CKDIV// FDCAN CFG clock divider register

    • [0:3]PDIV (def=0x0) // PDIV
  interrupts:
  • [3] FDCAN1_IT0 // FDCAN1 Interrupt 0
  • [32] FDCAN1_IT1 // FDCAN1 Interrupt 1
• 0x5000AC00SEC_FDCAN1_RAM//

  • 0x5000AC00FDCAN_CREL// FDCAN Core Release Register

    • [28:31]REL (def=0x3) // Core release
    • [24:27]STEP (def=0x2) // Step of Core release
    • [20:23]SUBSTEP (def=0x1) // Sub-step of Core release
    • [16:19]YEAR (def=0x4) // Timestamp Year
    • [8:15]MON (def=0x12) // Timestamp Month
    • [0:7]DAY (def=0x18) // Timestamp Day
  • 0x5000AC04FDCAN_ENDN// FDCAN endian register

    • [0:31]ETV (def=0x87654321) // Endiannes Test Value
  • 0x5000AC0CFDCAN_DBTP// FDCAN Data Bit Timing and Prescaler Register

    • [0:3]DSJW (def=0x3) // Synchronization Jump Width
    • [4:7]DTSEG2 (def=0x3) // Data time segment after sample point
    • [8:12]DTSEG1 (def=0xA) // Data time segment after sample point
    • [16:20]DBRP (def=0x0) // Data BIt Rate Prescaler
    • [23]TDC (def=0x0) // Transceiver Delay Compensation
  • 0x5000AC10FDCAN_TEST// FDCAN Test Register

    • [4]LBCK (def=0x0) // Loop Back mode
    • [5:6]TX (def=0x0) // Loop Back mode
    • [7]RX (def=0x0) // Control of Transmit Pin
  • 0x5000AC14FDCAN_RWD// FDCAN RAM Watchdog Register

    • [8:15]WDV (def=0x0) // Watchdog value
    • [0:7]WDC (def=0x0) // Watchdog configuration
  • 0x5000AC18FDCAN_CCCR// FDCAN CC Control Register

    • [0]INIT (def=0x1) // Initialization
    • [1]CCE (def=0x0) // Configuration Change Enable
    • [2]ASM (def=0x0) // ASM Restricted Operation Mode
    • [3]CSA (def=0x0) // Clock Stop Acknowledge
    • [4]CSR (def=0x0) // Clock Stop Request
    • [5]MON (def=0x0) // Bus Monitoring Mode
    • [6]DAR (def=0x0) // Disable Automatic Retransmission
    • [7]TEST (def=0x0) // Test Mode Enable
    • [8]FDOE (def=0x0) // FD Operation Enable
    • [9]BRSE (def=0x0) // FDCAN Bit Rate Switching
    • [12]PXHD (def=0x0) // Protocol Exception Handling Disable
    • [13]EFBI (def=0x0) // Edge Filtering during Bus Integration
    • [14]TXP (def=0x0) // TXP
    • [15]NISO (def=0x0) // Non ISO Operation
  • 0x5000AC1CFDCAN_NBTP// FDCAN Nominal Bit Timing and Prescaler Register

    • [25:31]NSJW (def=0x3) // Nominal (Re)Synchronization Jump Width
    • [16:24]NBRP (def=0x0) // Bit Rate Prescaler
    • [8:15]NTSEG1 (def=0xA) // Nominal Time segment before sample point
    • [0:6]NTSEG2 (def=0x3) // Nominal Time segment after sample point
  • 0x5000AC20FDCAN_TSCC// FDCAN Timestamp Counter Configuration Register

    • [16:19]TCP (def=0x0) // Timestamp Counter Prescaler
    • [0:1]TSS (def=0x0) // Timestamp Select
  • 0x5000AC24FDCAN_TSCV// FDCAN Timestamp Counter Value Register

    • [0:15]TSC (def=0x0) // Timestamp Counter
  • 0x5000AC28FDCAN_TOCC// FDCAN Timeout Counter Configuration Register

    • [0]ETOC (def=0x0) // Enable Timeout Counter
    • [1:2]TOS (def=0x0) // Timeout Select
    • [16:31]TOP (def=0xFFFF) // Timeout Period
  • 0x5000AC2CFDCAN_TOCV// FDCAN Timeout Counter Value Register

    • [0:15]TOC (def=0xFFFF) // Timeout Counter
  • 0x5000AC40FDCAN_ECR// FDCAN Error Counter Register

    • [16:23]CEL (def=0x0) // AN Error Logging
    • [15]RP (def=0x0) // Receive Error Passive
    • [8:14]REC (def=0x0) // Receive Error Counter
    • [0:7]TEC (def=0x0) // Transmit Error Counter
  • 0x5000AC44FDCAN_PSR// FDCAN Protocol Status Register

    • [0:2]LEC (def=0x7) // Last Error Code
    • [3:4]ACT (def=0x0) // Activity
    • [5]EP (def=0x0) // Error Passive
    • [6]EW (def=0x0) // Warning Status
    • [7]BO (def=0x0) // Bus_Off Status
    • [8:10]DLEC (def=0x7) // Data Last Error Code
    • [11]RESI (def=0x0) // ESI flag of last received FDCAN Message
    • [12]RBRS (def=0x0) // BRS flag of last received FDCAN Message
    • [13]REDL (def=0x0) // Received FDCAN Message
    • [14]PXE (def=0x0) // Protocol Exception Event
    • [16:22]TDCV (def=0x0) // Transmitter Delay Compensation Value
  • 0x5000AC48FDCAN_TDCR// FDCAN Transmitter Delay Compensation Register

    • [0:6]TDCF (def=0x0) // Transmitter Delay Compensation Filter Window Length
    • [8:14]TDCO (def=0x0) // Transmitter Delay Compensation Offset
  • 0x5000AC50FDCAN_IR// FDCAN Interrupt Register

    • [0]RF0N (def=0x0) // RF0N
    • [1]RF0F (def=0x0) // RF0F
    • [2]RF0L (def=0x0) // RF0L
    • [3]RF1N (def=0x0) // RF1N
    • [4]RF1F (def=0x0) // RF1F
    • [5]RF1L (def=0x0) // RF1L
    • [6]HPM (def=0x0) // HPM
    • [7]TC (def=0x0) // TC
    • [8]TCF (def=0x0) // TCF
    • [9]TFE (def=0x0) // TFE
    • [10]TEFN (def=0x0) // TEFN
    • [11]TEFF (def=0x0) // TEFF
    • [12]TEFL (def=0x0) // TEFL
    • [13]TSW (def=0x0) // TSW
    • [14]MRAF (def=0x0) // MRAF
    • [15]TOO (def=0x0) // TOO
    • [16]ELO (def=0x0) // ELO
    • [17]EP (def=0x0) // EP
    • [18]EW (def=0x0) // EW
    • [19]BO (def=0x0) // BO
    • [20]WDI (def=0x0) // WDI
    • [21]PEA (def=0x0) // PEA
    • [22]PED (def=0x0) // PED
    • [23]ARA (def=0x0) // ARA
  • 0x5000AC54FDCAN_IE// FDCAN Interrupt Enable Register

    • [0]RF0NE (def=0x0) // Rx FIFO 0 New Message Enable
    • [1]RF0FE (def=0x0) // Rx FIFO 0 Full Enable
    • [2]RF0LE (def=0x0) // Rx FIFO 0 Message Lost Enable
    • [3]RF1NE (def=0x0) // Rx FIFO 1 New Message Enable
    • [4]RF1FE (def=0x0) // Rx FIFO 1 Watermark Reached Enable
    • [5]RF1LE (def=0x0) // Rx FIFO 1 Message Lost Enable
    • [6]HPME (def=0x0) // High Priority Message Enable
    • [7]TCE (def=0x0) // Transmission Completed Enable
    • [8]TCFE (def=0x0) // Transmission Cancellation Finished Enable
    • [9]TEFE (def=0x0) // Tx FIFO Empty Enable
    • [10]TEFNE (def=0x0) // Tx Event FIFO New Entry Enable
    • [11]TEFFE (def=0x0) // Tx Event FIFO Full Enable
    • [12]TEFLE (def=0x0) // Tx Event FIFO Element Lost Enable
    • [13]TSWE (def=0x0) // TSWE
    • [14]MRAFE (def=0x0) // Message RAM Access Failure Enable
    • [15]TOOE (def=0x0) // Timeout Occurred Enable
    • [16]ELOE (def=0x0) // Error Logging Overflow Enable
    • [17]EPE (def=0x0) // Error Passive Enable
    • [18]EWE (def=0x0) // Warning Status Enable
    • [19]BOE (def=0x0) // Bus_Off Status Enable
    • [20]WDIE (def=0x0) // Watchdog Interrupt Enable
    • [21]PEAE (def=0x0) // Protocol Error in Arbitration Phase Enable
    • [22]PEDE (def=0x0) // Protocol Error in Data Phase Enable
    • [23]ARAE (def=0x0) // Access to Reserved Address Enable
  • 0x5000AC58FDCAN_ILS// FDCAN Interrupt Line Select Register

    • [0]RxFIFO0 (def=0x0) // RxFIFO0
    • [1]RxFIFO1 (def=0x0) // RxFIFO1
    • [2]SMSG (def=0x0) // SMSG
    • [3]TFERR (def=0x0) // TFERR
    • [4]MISC (def=0x0) // MISC
    • [5]BERR (def=0x0) // BERR
    • [6]PERR (def=0x0) // PERR
  • 0x5000AC5CFDCAN_ILE// FDCAN Interrupt Line Enable Register

    • [0]EINT0 (def=0x0) // Enable Interrupt Line 0
    • [1]EINT1 (def=0x0) // Enable Interrupt Line 1
  • 0x5000AC80FDCAN_RXGFC// FDCAN Global Filter Configuration Register

    • [0]RRFE (def=0x0) // Reject Remote Frames Extended
    • [1]RRFS (def=0x0) // Reject Remote Frames Standard
    • [2:3]ANFE (def=0x0) // Accept Non-matching Frames Extended
    • [4:5]ANFS (def=0x0) // Accept Non-matching Frames Standard
    • [8]F1OM (def=0x0) // F1OM
    • [9]F0OM (def=0x0) // F0OM
    • [16:20]LSS (def=0x0) // LSS
    • [24:27]LSE (def=0x0) // LSE
  • 0x5000AC84FDCAN_XIDAM// FDCAN Extended ID and Mask Register

    • [0:28]EIDM (def=0x1FFFFFFF) // Extended ID Mask
  • 0x5000AC88FDCAN_HPMS// FDCAN High Priority Message Status Register

    • [0:2]BIDX (def=0x0) // Buffer Index
    • [6:7]MSI (def=0x0) // Message Storage Indicator
    • [8:12]FIDX (def=0x0) // Filter Index
    • [15]FLST (def=0x0) // Filter List
  • 0x5000AC90FDCAN_RXF0S// FDCAN Rx FIFO 0 Status Register

    • [0:3]F0FL (def=0x0) // Rx FIFO 0 Fill Level
    • [8:9]F0GI (def=0x0) // Rx FIFO 0 Get Index
    • [16:17]F0PI (def=0x0) // Rx FIFO 0 Put Index
    • [24]F0F (def=0x0) // Rx FIFO 0 Full
    • [25]RF0L (def=0x0) // Rx FIFO 0 Message Lost
  • 0x5000AC94FDCAN_RXF0A// CAN Rx FIFO 0 Acknowledge Register

    • [0:2]F0AI (def=0x0) // Rx FIFO 0 Acknowledge Index
  • 0x5000AC98FDCAN_RXF1S// FDCAN Rx FIFO 1 Status Register

    • [0:3]F1FL (def=0x0) // Rx FIFO 1 Fill Level
    • [8:9]F1GI (def=0x0) // Rx FIFO 1 Get Index
    • [16:17]F1PI (def=0x0) // Rx FIFO 1 Put Index
    • [24]F1F (def=0x0) // Rx FIFO 1 Full
    • [25]RF1L (def=0x0) // Rx FIFO 1 Message Lost
  • 0x5000AC9CFDCAN_RXF1A// FDCAN Rx FIFO 1 Acknowledge Register

    • [0:2]F1AI (def=0x0) // Rx FIFO 1 Acknowledge Index
  • 0x5000ACC0FDCAN_TXBC// FDCAN Tx buffer configuration register

    • [24]TFQM (def=0x0) // Tx FIFO/Queue Mode
  • 0x5000ACC4FDCAN_TXFQS// FDCAN Tx FIFO/Queue Status Register

    • [0:2]TFFL (def=0x3) // Tx FIFO Free Level
    • [8:9]TFGI (def=0x0) // TFGI
    • [16:17]TFQPI (def=0x0) // Tx FIFO/Queue Put Index
    • [21]TFQF (def=0x0) // Tx FIFO/Queue Full
  • 0x5000ACC8FDCAN_TXBRP// FDCAN Tx Buffer Request Pending Register

    • [0:2]TRP (def=0x0) // Transmission Request Pending
  • 0x5000ACCCFDCAN_TXBAR// FDCAN Tx Buffer Add Request Register

    • [0:2]AR (def=0x0) // Add Request
  • 0x5000ACD0FDCAN_TXBCR// FDCAN Tx Buffer Cancellation Request Register

    • [0:2]CR (def=0x0) // Cancellation Request
  • 0x5000ACD4FDCAN_TXBTO// FDCAN Tx Buffer Transmission Occurred Register

    • [0:2]TO (def=0x0) // Transmission Occurred.
  • 0x5000ACD8FDCAN_TXBCF// FDCAN Tx Buffer Cancellation Finished Register

    • [0:2]CF (def=0x0) // Cancellation Finished
  • 0x5000ACDCFDCAN_TXBTIE// FDCAN Tx Buffer Transmission Interrupt Enable Register

    • [0:2]TIE (def=0x0) // Transmission Interrupt Enable
  • 0x5000ACE0FDCAN_TXBCIE// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

    • [0:2]CFIE (def=0x0) // Cancellation Finished Interrupt Enable
  • 0x5000ACE4FDCAN_TXEFS// FDCAN Tx Event FIFO Status Register

    • [0:2]EFFL (def=0x0) // Event FIFO Fill Level
    • [8:9]EFGI (def=0x0) // Event FIFO Get Index.
    • [16:17]EFPI (def=0x0) // Event FIFO Put Index
    • [24]EFF (def=0x0) // Event FIFO Full.
    • [25]TEFL (def=0x0) // Tx Event FIFO Element Lost.
  • 0x5000ACE8FDCAN_TXEFA// FDCAN Tx Event FIFO Acknowledge Register

    • [0:1]EFAI (def=0x0) // Event FIFO Acknowledge Index
  • 0x5000AD00FDCAN_CKDIV// FDCAN CFG clock divider register

    • [0:3]PDIV (def=0x0) // PDIV
• 0x4000A400FDCAN1//

  • 0x4000A400FDCAN_CREL// FDCAN Core Release Register

    • [28:31]REL (def=0x3) // Core release
    • [24:27]STEP (def=0x2) // Step of Core release
    • [20:23]SUBSTEP (def=0x1) // Sub-step of Core release
    • [16:19]YEAR (def=0x4) // Timestamp Year
    • [8:15]MON (def=0x12) // Timestamp Month
    • [0:7]DAY (def=0x18) // Timestamp Day
  • 0x4000A404FDCAN_ENDN// FDCAN endian register

    • [0:31]ETV (def=0x87654321) // Endiannes Test Value
  • 0x4000A40CFDCAN_DBTP// FDCAN Data Bit Timing and Prescaler Register

    • [0:3]DSJW (def=0x3) // Synchronization Jump Width
    • [4:7]DTSEG2 (def=0x3) // Data time segment after sample point
    • [8:12]DTSEG1 (def=0xA) // Data time segment after sample point
    • [16:20]DBRP (def=0x0) // Data BIt Rate Prescaler
    • [23]TDC (def=0x0) // Transceiver Delay Compensation
  • 0x4000A410FDCAN_TEST// FDCAN Test Register

    • [4]LBCK (def=0x0) // Loop Back mode
    • [5:6]TX (def=0x0) // Loop Back mode
    • [7]RX (def=0x0) // Control of Transmit Pin
  • 0x4000A414FDCAN_RWD// FDCAN RAM Watchdog Register

    • [8:15]WDV (def=0x0) // Watchdog value
    • [0:7]WDC (def=0x0) // Watchdog configuration
  • 0x4000A418FDCAN_CCCR// FDCAN CC Control Register

    • [0]INIT (def=0x1) // Initialization
    • [1]CCE (def=0x0) // Configuration Change Enable
    • [2]ASM (def=0x0) // ASM Restricted Operation Mode
    • [3]CSA (def=0x0) // Clock Stop Acknowledge
    • [4]CSR (def=0x0) // Clock Stop Request
    • [5]MON (def=0x0) // Bus Monitoring Mode
    • [6]DAR (def=0x0) // Disable Automatic Retransmission
    • [7]TEST (def=0x0) // Test Mode Enable
    • [8]FDOE (def=0x0) // FD Operation Enable
    • [9]BRSE (def=0x0) // FDCAN Bit Rate Switching
    • [12]PXHD (def=0x0) // Protocol Exception Handling Disable
    • [13]EFBI (def=0x0) // Edge Filtering during Bus Integration
    • [14]TXP (def=0x0) // TXP
    • [15]NISO (def=0x0) // Non ISO Operation
  • 0x4000A41CFDCAN_NBTP// FDCAN Nominal Bit Timing and Prescaler Register

    • [25:31]NSJW (def=0x3) // Nominal (Re)Synchronization Jump Width
    • [16:24]NBRP (def=0x0) // Bit Rate Prescaler
    • [8:15]NTSEG1 (def=0xA) // Nominal Time segment before sample point
    • [0:6]NTSEG2 (def=0x3) // Nominal Time segment after sample point
  • 0x4000A420FDCAN_TSCC// FDCAN Timestamp Counter Configuration Register

    • [16:19]TCP (def=0x0) // Timestamp Counter Prescaler
    • [0:1]TSS (def=0x0) // Timestamp Select
  • 0x4000A424FDCAN_TSCV// FDCAN Timestamp Counter Value Register

    • [0:15]TSC (def=0x0) // Timestamp Counter
  • 0x4000A428FDCAN_TOCC// FDCAN Timeout Counter Configuration Register

    • [0]ETOC (def=0x0) // Enable Timeout Counter
    • [1:2]TOS (def=0x0) // Timeout Select
    • [16:31]TOP (def=0xFFFF) // Timeout Period
  • 0x4000A42CFDCAN_TOCV// FDCAN Timeout Counter Value Register

    • [0:15]TOC (def=0xFFFF) // Timeout Counter
  • 0x4000A440FDCAN_ECR// FDCAN Error Counter Register

    • [16:23]CEL (def=0x0) // AN Error Logging
    • [15]RP (def=0x0) // Receive Error Passive
    • [8:14]REC (def=0x0) // Receive Error Counter
    • [0:7]TEC (def=0x0) // Transmit Error Counter
  • 0x4000A444FDCAN_PSR// FDCAN Protocol Status Register

    • [0:2]LEC (def=0x7) // Last Error Code
    • [3:4]ACT (def=0x0) // Activity
    • [5]EP (def=0x0) // Error Passive
    • [6]EW (def=0x0) // Warning Status
    • [7]BO (def=0x0) // Bus_Off Status
    • [8:10]DLEC (def=0x7) // Data Last Error Code
    • [11]RESI (def=0x0) // ESI flag of last received FDCAN Message
    • [12]RBRS (def=0x0) // BRS flag of last received FDCAN Message
    • [13]REDL (def=0x0) // Received FDCAN Message
    • [14]PXE (def=0x0) // Protocol Exception Event
    • [16:22]TDCV (def=0x0) // Transmitter Delay Compensation Value
  • 0x4000A448FDCAN_TDCR// FDCAN Transmitter Delay Compensation Register

    • [0:6]TDCF (def=0x0) // Transmitter Delay Compensation Filter Window Length
    • [8:14]TDCO (def=0x0) // Transmitter Delay Compensation Offset
  • 0x4000A450FDCAN_IR// FDCAN Interrupt Register

    • [0]RF0N (def=0x0) // RF0N
    • [1]RF0F (def=0x0) // RF0F
    • [2]RF0L (def=0x0) // RF0L
    • [3]RF1N (def=0x0) // RF1N
    • [4]RF1F (def=0x0) // RF1F
    • [5]RF1L (def=0x0) // RF1L
    • [6]HPM (def=0x0) // HPM
    • [7]TC (def=0x0) // TC
    • [8]TCF (def=0x0) // TCF
    • [9]TFE (def=0x0) // TFE
    • [10]TEFN (def=0x0) // TEFN
    • [11]TEFF (def=0x0) // TEFF
    • [12]TEFL (def=0x0) // TEFL
    • [13]TSW (def=0x0) // TSW
    • [14]MRAF (def=0x0) // MRAF
    • [15]TOO (def=0x0) // TOO
    • [16]ELO (def=0x0) // ELO
    • [17]EP (def=0x0) // EP
    • [18]EW (def=0x0) // EW
    • [19]BO (def=0x0) // BO
    • [20]WDI (def=0x0) // WDI
    • [21]PEA (def=0x0) // PEA
    • [22]PED (def=0x0) // PED
    • [23]ARA (def=0x0) // ARA
  • 0x4000A454FDCAN_IE// FDCAN Interrupt Enable Register

    • [0]RF0NE (def=0x0) // Rx FIFO 0 New Message Enable
    • [1]RF0FE (def=0x0) // Rx FIFO 0 Full Enable
    • [2]RF0LE (def=0x0) // Rx FIFO 0 Message Lost Enable
    • [3]RF1NE (def=0x0) // Rx FIFO 1 New Message Enable
    • [4]RF1FE (def=0x0) // Rx FIFO 1 Watermark Reached Enable
    • [5]RF1LE (def=0x0) // Rx FIFO 1 Message Lost Enable
    • [6]HPME (def=0x0) // High Priority Message Enable
    • [7]TCE (def=0x0) // Transmission Completed Enable
    • [8]TCFE (def=0x0) // Transmission Cancellation Finished Enable
    • [9]TEFE (def=0x0) // Tx FIFO Empty Enable
    • [10]TEFNE (def=0x0) // Tx Event FIFO New Entry Enable
    • [11]TEFFE (def=0x0) // Tx Event FIFO Full Enable
    • [12]TEFLE (def=0x0) // Tx Event FIFO Element Lost Enable
    • [13]TSWE (def=0x0) // TSWE
    • [14]MRAFE (def=0x0) // Message RAM Access Failure Enable
    • [15]TOOE (def=0x0) // Timeout Occurred Enable
    • [16]ELOE (def=0x0) // Error Logging Overflow Enable
    • [17]EPE (def=0x0) // Error Passive Enable
    • [18]EWE (def=0x0) // Warning Status Enable
    • [19]BOE (def=0x0) // Bus_Off Status Enable
    • [20]WDIE (def=0x0) // Watchdog Interrupt Enable
    • [21]PEAE (def=0x0) // Protocol Error in Arbitration Phase Enable
    • [22]PEDE (def=0x0) // Protocol Error in Data Phase Enable
    • [23]ARAE (def=0x0) // Access to Reserved Address Enable
  • 0x4000A458FDCAN_ILS// FDCAN Interrupt Line Select Register

    • [0]RxFIFO0 (def=0x0) // RxFIFO0
    • [1]RxFIFO1 (def=0x0) // RxFIFO1
    • [2]SMSG (def=0x0) // SMSG
    • [3]TFERR (def=0x0) // TFERR
    • [4]MISC (def=0x0) // MISC
    • [5]BERR (def=0x0) // BERR
    • [6]PERR (def=0x0) // PERR
  • 0x4000A45CFDCAN_ILE// FDCAN Interrupt Line Enable Register

    • [0]EINT0 (def=0x0) // Enable Interrupt Line 0
    • [1]EINT1 (def=0x0) // Enable Interrupt Line 1
  • 0x4000A480FDCAN_RXGFC// FDCAN Global Filter Configuration Register

    • [0]RRFE (def=0x0) // Reject Remote Frames Extended
    • [1]RRFS (def=0x0) // Reject Remote Frames Standard
    • [2:3]ANFE (def=0x0) // Accept Non-matching Frames Extended
    • [4:5]ANFS (def=0x0) // Accept Non-matching Frames Standard
    • [8]F1OM (def=0x0) // F1OM
    • [9]F0OM (def=0x0) // F0OM
    • [16:20]LSS (def=0x0) // LSS
    • [24:27]LSE (def=0x0) // LSE
  • 0x4000A484FDCAN_XIDAM// FDCAN Extended ID and Mask Register

    • [0:28]EIDM (def=0x1FFFFFFF) // Extended ID Mask
  • 0x4000A488FDCAN_HPMS// FDCAN High Priority Message Status Register

    • [0:2]BIDX (def=0x0) // Buffer Index
    • [6:7]MSI (def=0x0) // Message Storage Indicator
    • [8:12]FIDX (def=0x0) // Filter Index
    • [15]FLST (def=0x0) // Filter List
  • 0x4000A490FDCAN_RXF0S// FDCAN Rx FIFO 0 Status Register

    • [0:3]F0FL (def=0x0) // Rx FIFO 0 Fill Level
    • [8:9]F0GI (def=0x0) // Rx FIFO 0 Get Index
    • [16:17]F0PI (def=0x0) // Rx FIFO 0 Put Index
    • [24]F0F (def=0x0) // Rx FIFO 0 Full
    • [25]RF0L (def=0x0) // Rx FIFO 0 Message Lost
  • 0x4000A494FDCAN_RXF0A// CAN Rx FIFO 0 Acknowledge Register

    • [0:2]F0AI (def=0x0) // Rx FIFO 0 Acknowledge Index
  • 0x4000A498FDCAN_RXF1S// FDCAN Rx FIFO 1 Status Register

    • [0:3]F1FL (def=0x0) // Rx FIFO 1 Fill Level
    • [8:9]F1GI (def=0x0) // Rx FIFO 1 Get Index
    • [16:17]F1PI (def=0x0) // Rx FIFO 1 Put Index
    • [24]F1F (def=0x0) // Rx FIFO 1 Full
    • [25]RF1L (def=0x0) // Rx FIFO 1 Message Lost
  • 0x4000A49CFDCAN_RXF1A// FDCAN Rx FIFO 1 Acknowledge Register

    • [0:2]F1AI (def=0x0) // Rx FIFO 1 Acknowledge Index
  • 0x4000A4C0FDCAN_TXBC// FDCAN Tx buffer configuration register

    • [24]TFQM (def=0x0) // Tx FIFO/Queue Mode
  • 0x4000A4C4FDCAN_TXFQS// FDCAN Tx FIFO/Queue Status Register

    • [0:2]TFFL (def=0x3) // Tx FIFO Free Level
    • [8:9]TFGI (def=0x0) // TFGI
    • [16:17]TFQPI (def=0x0) // Tx FIFO/Queue Put Index
    • [21]TFQF (def=0x0) // Tx FIFO/Queue Full
  • 0x4000A4C8FDCAN_TXBRP// FDCAN Tx Buffer Request Pending Register

    • [0:2]TRP (def=0x0) // Transmission Request Pending
  • 0x4000A4CCFDCAN_TXBAR// FDCAN Tx Buffer Add Request Register

    • [0:2]AR (def=0x0) // Add Request
  • 0x4000A4D0FDCAN_TXBCR// FDCAN Tx Buffer Cancellation Request Register

    • [0:2]CR (def=0x0) // Cancellation Request
  • 0x4000A4D4FDCAN_TXBTO// FDCAN Tx Buffer Transmission Occurred Register

    • [0:2]TO (def=0x0) // Transmission Occurred.
  • 0x4000A4D8FDCAN_TXBCF// FDCAN Tx Buffer Cancellation Finished Register

    • [0:2]CF (def=0x0) // Cancellation Finished
  • 0x4000A4DCFDCAN_TXBTIE// FDCAN Tx Buffer Transmission Interrupt Enable Register

    • [0:2]TIE (def=0x0) // Transmission Interrupt Enable
  • 0x4000A4E0FDCAN_TXBCIE// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

    • [0:2]CFIE (def=0x0) // Cancellation Finished Interrupt Enable
  • 0x4000A4E4FDCAN_TXEFS// FDCAN Tx Event FIFO Status Register

    • [0:2]EFFL (def=0x0) // Event FIFO Fill Level
    • [8:9]EFGI (def=0x0) // Event FIFO Get Index.
    • [16:17]EFPI (def=0x0) // Event FIFO Put Index
    • [24]EFF (def=0x0) // Event FIFO Full.
    • [25]TEFL (def=0x0) // Tx Event FIFO Element Lost.
  • 0x4000A4E8FDCAN_TXEFA// FDCAN Tx Event FIFO Acknowledge Register

    • [0:1]EFAI (def=0x0) // Event FIFO Acknowledge Index
  • 0x4000A500FDCAN_CKDIV// FDCAN CFG clock divider register

    • [0:3]PDIV (def=0x0) // PDIV
  interrupts:
  • [57] TIM17 // TIM17 global interrupt
• 0x5000A400SEC_FDCAN1//

  • 0x5000A400FDCAN_CREL// FDCAN Core Release Register

    • [28:31]REL (def=0x3) // Core release
    • [24:27]STEP (def=0x2) // Step of Core release
    • [20:23]SUBSTEP (def=0x1) // Sub-step of Core release
    • [16:19]YEAR (def=0x4) // Timestamp Year
    • [8:15]MON (def=0x12) // Timestamp Month
    • [0:7]DAY (def=0x18) // Timestamp Day
  • 0x5000A404FDCAN_ENDN// FDCAN endian register

    • [0:31]ETV (def=0x87654321) // Endiannes Test Value
  • 0x5000A40CFDCAN_DBTP// FDCAN Data Bit Timing and Prescaler Register

    • [0:3]DSJW (def=0x3) // Synchronization Jump Width
    • [4:7]DTSEG2 (def=0x3) // Data time segment after sample point
    • [8:12]DTSEG1 (def=0xA) // Data time segment after sample point
    • [16:20]DBRP (def=0x0) // Data BIt Rate Prescaler
    • [23]TDC (def=0x0) // Transceiver Delay Compensation
  • 0x5000A410FDCAN_TEST// FDCAN Test Register

    • [4]LBCK (def=0x0) // Loop Back mode
    • [5:6]TX (def=0x0) // Loop Back mode
    • [7]RX (def=0x0) // Control of Transmit Pin
  • 0x5000A414FDCAN_RWD// FDCAN RAM Watchdog Register

    • [8:15]WDV (def=0x0) // Watchdog value
    • [0:7]WDC (def=0x0) // Watchdog configuration
  • 0x5000A418FDCAN_CCCR// FDCAN CC Control Register

    • [0]INIT (def=0x1) // Initialization
    • [1]CCE (def=0x0) // Configuration Change Enable
    • [2]ASM (def=0x0) // ASM Restricted Operation Mode
    • [3]CSA (def=0x0) // Clock Stop Acknowledge
    • [4]CSR (def=0x0) // Clock Stop Request
    • [5]MON (def=0x0) // Bus Monitoring Mode
    • [6]DAR (def=0x0) // Disable Automatic Retransmission
    • [7]TEST (def=0x0) // Test Mode Enable
    • [8]FDOE (def=0x0) // FD Operation Enable
    • [9]BRSE (def=0x0) // FDCAN Bit Rate Switching
    • [12]PXHD (def=0x0) // Protocol Exception Handling Disable
    • [13]EFBI (def=0x0) // Edge Filtering during Bus Integration
    • [14]TXP (def=0x0) // TXP
    • [15]NISO (def=0x0) // Non ISO Operation
  • 0x5000A41CFDCAN_NBTP// FDCAN Nominal Bit Timing and Prescaler Register

    • [25:31]NSJW (def=0x3) // Nominal (Re)Synchronization Jump Width
    • [16:24]NBRP (def=0x0) // Bit Rate Prescaler
    • [8:15]NTSEG1 (def=0xA) // Nominal Time segment before sample point
    • [0:6]NTSEG2 (def=0x3) // Nominal Time segment after sample point
  • 0x5000A420FDCAN_TSCC// FDCAN Timestamp Counter Configuration Register

    • [16:19]TCP (def=0x0) // Timestamp Counter Prescaler
    • [0:1]TSS (def=0x0) // Timestamp Select
  • 0x5000A424FDCAN_TSCV// FDCAN Timestamp Counter Value Register

    • [0:15]TSC (def=0x0) // Timestamp Counter
  • 0x5000A428FDCAN_TOCC// FDCAN Timeout Counter Configuration Register

    • [0]ETOC (def=0x0) // Enable Timeout Counter
    • [1:2]TOS (def=0x0) // Timeout Select
    • [16:31]TOP (def=0xFFFF) // Timeout Period
  • 0x5000A42CFDCAN_TOCV// FDCAN Timeout Counter Value Register

    • [0:15]TOC (def=0xFFFF) // Timeout Counter
  • 0x5000A440FDCAN_ECR// FDCAN Error Counter Register

    • [16:23]CEL (def=0x0) // AN Error Logging
    • [15]RP (def=0x0) // Receive Error Passive
    • [8:14]REC (def=0x0) // Receive Error Counter
    • [0:7]TEC (def=0x0) // Transmit Error Counter
  • 0x5000A444FDCAN_PSR// FDCAN Protocol Status Register

    • [0:2]LEC (def=0x7) // Last Error Code
    • [3:4]ACT (def=0x0) // Activity
    • [5]EP (def=0x0) // Error Passive
    • [6]EW (def=0x0) // Warning Status
    • [7]BO (def=0x0) // Bus_Off Status
    • [8:10]DLEC (def=0x7) // Data Last Error Code
    • [11]RESI (def=0x0) // ESI flag of last received FDCAN Message
    • [12]RBRS (def=0x0) // BRS flag of last received FDCAN Message
    • [13]REDL (def=0x0) // Received FDCAN Message
    • [14]PXE (def=0x0) // Protocol Exception Event
    • [16:22]TDCV (def=0x0) // Transmitter Delay Compensation Value
  • 0x5000A448FDCAN_TDCR// FDCAN Transmitter Delay Compensation Register

    • [0:6]TDCF (def=0x0) // Transmitter Delay Compensation Filter Window Length
    • [8:14]TDCO (def=0x0) // Transmitter Delay Compensation Offset
  • 0x5000A450FDCAN_IR// FDCAN Interrupt Register

    • [0]RF0N (def=0x0) // RF0N
    • [1]RF0F (def=0x0) // RF0F
    • [2]RF0L (def=0x0) // RF0L
    • [3]RF1N (def=0x0) // RF1N
    • [4]RF1F (def=0x0) // RF1F
    • [5]RF1L (def=0x0) // RF1L
    • [6]HPM (def=0x0) // HPM
    • [7]TC (def=0x0) // TC
    • [8]TCF (def=0x0) // TCF
    • [9]TFE (def=0x0) // TFE
    • [10]TEFN (def=0x0) // TEFN
    • [11]TEFF (def=0x0) // TEFF
    • [12]TEFL (def=0x0) // TEFL
    • [13]TSW (def=0x0) // TSW
    • [14]MRAF (def=0x0) // MRAF
    • [15]TOO (def=0x0) // TOO
    • [16]ELO (def=0x0) // ELO
    • [17]EP (def=0x0) // EP
    • [18]EW (def=0x0) // EW
    • [19]BO (def=0x0) // BO
    • [20]WDI (def=0x0) // WDI
    • [21]PEA (def=0x0) // PEA
    • [22]PED (def=0x0) // PED
    • [23]ARA (def=0x0) // ARA
  • 0x5000A454FDCAN_IE// FDCAN Interrupt Enable Register

    • [0]RF0NE (def=0x0) // Rx FIFO 0 New Message Enable
    • [1]RF0FE (def=0x0) // Rx FIFO 0 Full Enable
    • [2]RF0LE (def=0x0) // Rx FIFO 0 Message Lost Enable
    • [3]RF1NE (def=0x0) // Rx FIFO 1 New Message Enable
    • [4]RF1FE (def=0x0) // Rx FIFO 1 Watermark Reached Enable
    • [5]RF1LE (def=0x0) // Rx FIFO 1 Message Lost Enable
    • [6]HPME (def=0x0) // High Priority Message Enable
    • [7]TCE (def=0x0) // Transmission Completed Enable
    • [8]TCFE (def=0x0) // Transmission Cancellation Finished Enable
    • [9]TEFE (def=0x0) // Tx FIFO Empty Enable
    • [10]TEFNE (def=0x0) // Tx Event FIFO New Entry Enable
    • [11]TEFFE (def=0x0) // Tx Event FIFO Full Enable
    • [12]TEFLE (def=0x0) // Tx Event FIFO Element Lost Enable
    • [13]TSWE (def=0x0) // TSWE
    • [14]MRAFE (def=0x0) // Message RAM Access Failure Enable
    • [15]TOOE (def=0x0) // Timeout Occurred Enable
    • [16]ELOE (def=0x0) // Error Logging Overflow Enable
    • [17]EPE (def=0x0) // Error Passive Enable
    • [18]EWE (def=0x0) // Warning Status Enable
    • [19]BOE (def=0x0) // Bus_Off Status Enable
    • [20]WDIE (def=0x0) // Watchdog Interrupt Enable
    • [21]PEAE (def=0x0) // Protocol Error in Arbitration Phase Enable
    • [22]PEDE (def=0x0) // Protocol Error in Data Phase Enable
    • [23]ARAE (def=0x0) // Access to Reserved Address Enable
  • 0x5000A458FDCAN_ILS// FDCAN Interrupt Line Select Register

    • [0]RxFIFO0 (def=0x0) // RxFIFO0
    • [1]RxFIFO1 (def=0x0) // RxFIFO1
    • [2]SMSG (def=0x0) // SMSG
    • [3]TFERR (def=0x0) // TFERR
    • [4]MISC (def=0x0) // MISC
    • [5]BERR (def=0x0) // BERR
    • [6]PERR (def=0x0) // PERR
  • 0x5000A45CFDCAN_ILE// FDCAN Interrupt Line Enable Register

    • [0]EINT0 (def=0x0) // Enable Interrupt Line 0
    • [1]EINT1 (def=0x0) // Enable Interrupt Line 1
  • 0x5000A480FDCAN_RXGFC// FDCAN Global Filter Configuration Register

    • [0]RRFE (def=0x0) // Reject Remote Frames Extended
    • [1]RRFS (def=0x0) // Reject Remote Frames Standard
    • [2:3]ANFE (def=0x0) // Accept Non-matching Frames Extended
    • [4:5]ANFS (def=0x0) // Accept Non-matching Frames Standard
    • [8]F1OM (def=0x0) // F1OM
    • [9]F0OM (def=0x0) // F0OM
    • [16:20]LSS (def=0x0) // LSS
    • [24:27]LSE (def=0x0) // LSE
  • 0x5000A484FDCAN_XIDAM// FDCAN Extended ID and Mask Register

    • [0:28]EIDM (def=0x1FFFFFFF) // Extended ID Mask
  • 0x5000A488FDCAN_HPMS// FDCAN High Priority Message Status Register

    • [0:2]BIDX (def=0x0) // Buffer Index
    • [6:7]MSI (def=0x0) // Message Storage Indicator
    • [8:12]FIDX (def=0x0) // Filter Index
    • [15]FLST (def=0x0) // Filter List
  • 0x5000A490FDCAN_RXF0S// FDCAN Rx FIFO 0 Status Register

    • [0:3]F0FL (def=0x0) // Rx FIFO 0 Fill Level
    • [8:9]F0GI (def=0x0) // Rx FIFO 0 Get Index
    • [16:17]F0PI (def=0x0) // Rx FIFO 0 Put Index
    • [24]F0F (def=0x0) // Rx FIFO 0 Full
    • [25]RF0L (def=0x0) // Rx FIFO 0 Message Lost
  • 0x5000A494FDCAN_RXF0A// CAN Rx FIFO 0 Acknowledge Register

    • [0:2]F0AI (def=0x0) // Rx FIFO 0 Acknowledge Index
  • 0x5000A498FDCAN_RXF1S// FDCAN Rx FIFO 1 Status Register

    • [0:3]F1FL (def=0x0) // Rx FIFO 1 Fill Level
    • [8:9]F1GI (def=0x0) // Rx FIFO 1 Get Index
    • [16:17]F1PI (def=0x0) // Rx FIFO 1 Put Index
    • [24]F1F (def=0x0) // Rx FIFO 1 Full
    • [25]RF1L (def=0x0) // Rx FIFO 1 Message Lost
  • 0x5000A49CFDCAN_RXF1A// FDCAN Rx FIFO 1 Acknowledge Register

    • [0:2]F1AI (def=0x0) // Rx FIFO 1 Acknowledge Index
  • 0x5000A4C0FDCAN_TXBC// FDCAN Tx buffer configuration register

    • [24]TFQM (def=0x0) // Tx FIFO/Queue Mode
  • 0x5000A4C4FDCAN_TXFQS// FDCAN Tx FIFO/Queue Status Register

    • [0:2]TFFL (def=0x3) // Tx FIFO Free Level
    • [8:9]TFGI (def=0x0) // TFGI
    • [16:17]TFQPI (def=0x0) // Tx FIFO/Queue Put Index
    • [21]TFQF (def=0x0) // Tx FIFO/Queue Full
  • 0x5000A4C8FDCAN_TXBRP// FDCAN Tx Buffer Request Pending Register

    • [0:2]TRP (def=0x0) // Transmission Request Pending
  • 0x5000A4CCFDCAN_TXBAR// FDCAN Tx Buffer Add Request Register

    • [0:2]AR (def=0x0) // Add Request
  • 0x5000A4D0FDCAN_TXBCR// FDCAN Tx Buffer Cancellation Request Register

    • [0:2]CR (def=0x0) // Cancellation Request
  • 0x5000A4D4FDCAN_TXBTO// FDCAN Tx Buffer Transmission Occurred Register

    • [0:2]TO (def=0x0) // Transmission Occurred.
  • 0x5000A4D8FDCAN_TXBCF// FDCAN Tx Buffer Cancellation Finished Register

    • [0:2]CF (def=0x0) // Cancellation Finished
  • 0x5000A4DCFDCAN_TXBTIE// FDCAN Tx Buffer Transmission Interrupt Enable Register

    • [0:2]TIE (def=0x0) // Transmission Interrupt Enable
  • 0x5000A4E0FDCAN_TXBCIE// FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

    • [0:2]CFIE (def=0x0) // Cancellation Finished Interrupt Enable
  • 0x5000A4E4FDCAN_TXEFS// FDCAN Tx Event FIFO Status Register

    • [0:2]EFFL (def=0x0) // Event FIFO Fill Level
    • [8:9]EFGI (def=0x0) // Event FIFO Get Index.
    • [16:17]EFPI (def=0x0) // Event FIFO Put Index
    • [24]EFF (def=0x0) // Event FIFO Full.
    • [25]TEFL (def=0x0) // Tx Event FIFO Element Lost.
  • 0x5000A4E8FDCAN_TXEFA// FDCAN Tx Event FIFO Acknowledge Register

    • [0:1]EFAI (def=0x0) // Event FIFO Acknowledge Index
  • 0x5000A500FDCAN_CKDIV// FDCAN CFG clock divider register

    • [0:3]PDIV (def=0x0) // PDIV
• 0x40023000CRC// Cyclic redundancy check calculation unit

  • 0x40023000DR// Data register

    • [0:31]DR (def=0xFFFFFFFF) // Data register bits
  • 0x40023004IDR// Independent data register

    • [0:31]IDR (def=0x0) // General-purpose 8-bit data register bits
  • 0x40023008CR// Control register

    • [7]REV_OUT (def=0x0) // Reverse output data
    • [5:6]REV_IN (def=0x0) // Reverse input data
    • [3:4]POLYSIZE (def=0x0) // Polynomial size
    • [0]RESET (def=0x0) // RESET bit
  • 0x40023010INIT// Initial CRC value

    • [0:31]CRC_INIT (def=0xFFFFFFFF) // Programmable initial CRC value
  • 0x40023014POL// polynomial

    • [0:31]POL (def=0x4C11DB7) // Programmable polynomial
• 0x50023000SEC_CRC//

  • 0x50023000DR// Data register

    • [0:31]DR (def=0xFFFFFFFF) // Data register bits
  • 0x50023004IDR// Independent data register

    • [0:31]IDR (def=0x0) // General-purpose 8-bit data register bits
  • 0x50023008CR// Control register

    • [7]REV_OUT (def=0x0) // Reverse output data
    • [5:6]REV_IN (def=0x0) // Reverse input data
    • [3:4]POLYSIZE (def=0x0) // Polynomial size
    • [0]RESET (def=0x0) // RESET bit
  • 0x50023010INIT// Initial CRC value

    • [0:31]CRC_INIT (def=0xFFFFFFFF) // Programmable initial CRC value
  • 0x50023014POL// polynomial

    • [0:31]POL (def=0x4C11DB7) // Programmable polynomial
• 0x40006000CRS// Clock recovery system

  • 0x40006000CR// control register

    • [8:14]TRIM (def=0x40) // HSI48 oscillator smooth trimming
    • [7]SWSYNC (def=0x0) // Generate software SYNC event
    • [6]AUTOTRIMEN (def=0x0) // Automatic trimming enable
    • [5]CEN (def=0x0) // Frequency error counter enable
    • [3]ESYNCIE (def=0x0) // Expected SYNC interrupt enable
    • [2]ERRIE (def=0x0) // Synchronization or trimming error interrupt enable
    • [1]SYNCWARNIE (def=0x0) // SYNC warning interrupt enable
    • [0]SYNCOKIE (def=0x0) // SYNC event OK interrupt enable
  • 0x40006004CFGR// configuration register

    • [31]SYNCPOL (def=0x0) // SYNC polarity selection
    • [28:29]SYNCSRC (def=0x2) // SYNC signal source selection
    • [24:26]SYNCDIV (def=0x0) // SYNC divider
    • [16:23]FELIM (def=0x22) // Frequency error limit
    • [0:15]RELOAD (def=0xBB7F) // Counter reload value
  • 0x40006008ISR// interrupt and status register

    • [16:31]FECAP (def=0x0) // Frequency error capture
    • [15]FEDIR (def=0x0) // Frequency error direction
    • [10]TRIMOVF (def=0x0) // Trimming overflow or underflow
    • [9]SYNCMISS (def=0x0) // SYNC missed
    • [8]SYNCERR (def=0x0) // SYNC error
    • [3]ESYNCF (def=0x0) // Expected SYNC flag
    • [2]ERRF (def=0x0) // Error flag
    • [1]SYNCWARNF (def=0x0) // SYNC warning flag
    • [0]SYNCOKF (def=0x0) // SYNC event OK flag
  • 0x4000600CICR// interrupt flag clear register

    • [3]ESYNCC (def=0x0) // Expected SYNC clear flag
    • [2]ERRC (def=0x0) // Error clear flag
    • [1]SYNCWARNC (def=0x0) // SYNC warning clear flag
    • [0]SYNCOKC (def=0x0) // SYNC event OK clear flag
  interrupts:
  • [74] CRS // Clock recovery system global interrupt
• 0x50006000SEC_CRS//

  • 0x50006000CR// control register

    • [8:14]TRIM (def=0x40) // HSI48 oscillator smooth trimming
    • [7]SWSYNC (def=0x0) // Generate software SYNC event
    • [6]AUTOTRIMEN (def=0x0) // Automatic trimming enable
    • [5]CEN (def=0x0) // Frequency error counter enable
    • [3]ESYNCIE (def=0x0) // Expected SYNC interrupt enable
    • [2]ERRIE (def=0x0) // Synchronization or trimming error interrupt enable
    • [1]SYNCWARNIE (def=0x0) // SYNC warning interrupt enable
    • [0]SYNCOKIE (def=0x0) // SYNC event OK interrupt enable
  • 0x50006004CFGR// configuration register

    • [31]SYNCPOL (def=0x0) // SYNC polarity selection
    • [28:29]SYNCSRC (def=0x2) // SYNC signal source selection
    • [24:26]SYNCDIV (def=0x0) // SYNC divider
    • [16:23]FELIM (def=0x22) // Frequency error limit
    • [0:15]RELOAD (def=0xBB7F) // Counter reload value
  • 0x50006008ISR// interrupt and status register

    • [16:31]FECAP (def=0x0) // Frequency error capture
    • [15]FEDIR (def=0x0) // Frequency error direction
    • [10]TRIMOVF (def=0x0) // Trimming overflow or underflow
    • [9]SYNCMISS (def=0x0) // SYNC missed
    • [8]SYNCERR (def=0x0) // SYNC error
    • [3]ESYNCF (def=0x0) // Expected SYNC flag
    • [2]ERRF (def=0x0) // Error flag
    • [1]SYNCWARNF (def=0x0) // SYNC warning flag
    • [0]SYNCOKF (def=0x0) // SYNC event OK flag
  • 0x5000600CICR// interrupt flag clear register

    • [3]ESYNCC (def=0x0) // Expected SYNC clear flag
    • [2]ERRC (def=0x0) // Error clear flag
    • [1]SYNCWARNC (def=0x0) // SYNC warning clear flag
    • [0]SYNCOKC (def=0x0) // SYNC event OK clear flag
• 0x40013800USART1// Universal synchronous asynchronous receiver transmitter

  • 0x40013800CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x40013800CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x40013804CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x40013808CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x4001380CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x40013810GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40013814RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x40013818RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x4001381CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x4001381CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x40013820ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x40013824RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x40013828TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x4001382CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x40013830AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
  interrupts:
  • [49] USART1 // USART1 global interrupt
• 0x50013800SEC_USART1//

  • 0x50013800CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x50013800CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x50013804CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x50013808CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x5001380CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x50013810GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x50013814RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x50013818RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x5001381CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x5001381CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x50013820ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x50013824RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x50013828TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x5001382CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x50013830AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
• 0x40004400USART2//

  • 0x40004400CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x40004400CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x40004404CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x40004408CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x4000440CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x40004410GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40004414RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x40004418RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x4000441CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x4000441CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x40004420ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x40004424RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x40004428TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x4000442CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x40004430AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
  interrupts:
  • [50] USART2 // USART2 global interrupt
• 0x50004400SEC_USART2//

  • 0x50004400CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x50004400CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x50004404CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x50004408CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x5000440CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x50004410GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x50004414RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x50004418RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x5000441CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x5000441CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x50004420ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x50004424RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x50004428TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x5000442CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x50004430AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
• 0x40004800USART3//

  • 0x40004800CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x40004800CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x40004804CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x40004808CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x4000480CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x40004810GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40004814RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x40004818RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x4000481CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x4000481CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x40004820ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x40004824RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x40004828TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x4000482CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x40004830AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
  interrupts:
  • [51] USART3 // USART3 global interrupt
• 0x50004800SEC_USART3//

  • 0x50004800CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x50004800CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x50004804CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x50004808CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x5000480CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x50004810GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x50004814RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x50004818RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x5000481CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x5000481CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x50004820ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x50004824RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x50004828TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x5000482CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x50004830AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
• 0x40004C00UART4//

  • 0x40004C00CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x40004C00CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x40004C04CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x40004C08CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x40004C0CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x40004C10GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40004C14RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x40004C18RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x40004C1CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x40004C1CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x40004C20ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x40004C24RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x40004C28TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x40004C2CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x40004C30AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
  interrupts:
  • [52] UART4 // UART4 global interrupt
• 0x50004C00SEC_UART4//

  • 0x50004C00CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x50004C00CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x50004C04CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x50004C08CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x50004C0CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x50004C10GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x50004C14RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x50004C18RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x50004C1CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x50004C1CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x50004C20ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x50004C24RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x50004C28TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x50004C2CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x50004C30AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
• 0x40005000UART5//

  • 0x40005000CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x40005000CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x40005004CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x40005008CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x4000500CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x40005010GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40005014RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x40005018RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x4000501CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x4000501CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x40005020ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x40005024RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x40005028TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x4000502CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x40005030AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
  interrupts:
  • [53] UART5 // UART5 global interrupt
• 0x50005000SEC_UART5//

  • 0x50005000CR1_enabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interruptenable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
    • [30]TXFEIE (def=0x0) // TXFEIE
    • [31]RXFFIE (def=0x0) // RXFFIE
  • 0x50005000CR1_disabled// Control register 1

    • [28]M1 (def=0x0) // Word length
    • [27]EOBIE (def=0x0) // End of Block interrupt enable
    • [26]RTOIE (def=0x0) // Receiver timeout interrupt enable
    • [21:25]DEAT (def=0x0) // DEAT
    • [16:20]DEDT (def=0x0) // DEDT
    • [15]OVER8 (def=0x0) // Oversampling mode
    • [14]CMIE (def=0x0) // Character match interrupt enable
    • [13]MME (def=0x0) // Mute mode enable
    • [12]M0 (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Receiver wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXFNFIE (def=0x0) // TXFIFO not full interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXFNEIE (def=0x0) // RXFIFO not empty interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]UESM (def=0x0) // USART enable in Stop mode
    • [0]UE (def=0x0) // USART enable
    • [29]FIFOEN (def=0x0) // FIFOEN
  • 0x50005004CR2// Control register 2

    • [24:31]ADD (def=0x0) // Address of the USART node
    • [23]RTOEN (def=0x0) // Receiver timeout enable
    • [21:22]ABRMOD (def=0x0) // Auto baud rate mode
    • [20]ABREN (def=0x0) // Auto baud rate enable
    • [19]MSBFIRST (def=0x0) // Most significant bit first
    • [18]DATAINV (def=0x0) // Binary data inversion
    • [17]TXINV (def=0x0) // TX pin active level inversion
    • [16]RXINV (def=0x0) // RX pin active level inversion
    • [15]SWAP (def=0x0) // Swap TX/RX pins
    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // LIN break detection length
    • [4]ADDM7 (def=0x0) // 7-bit Address Detection/4-bit Address Detection
    • [0]SLVEN (def=0x0) // SLVEN
    • [3]DIS_NSS (def=0x0) // DIS_NSS
  • 0x50005008CR3// Control register 3

    • [17:19]SCARCNT (def=0x0) // Smartcard auto-retry count
    • [15]DEP (def=0x0) // Driver enable polarity selection
    • [14]DEM (def=0x0) // Driver enable mode
    • [13]DDRE (def=0x0) // DMA Disable on Reception Error
    • [12]OVRDIS (def=0x0) // Overrun Disable
    • [11]ONEBIT (def=0x0) // One sample bit method enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // Ir low-power
    • [1]IREN (def=0x0) // Ir mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
    • [23]TXFTIE (def=0x0) // TXFTIE
    • [24]TCBGTIE (def=0x0) // TCBGTIE
    • [25:27]RXFTCFG (def=0x0) // RXFTCFG
    • [28]RXFTIE (def=0x0) // RXFTIE
    • [29:31]TXFTCFG (def=0x0) // TXFTCFG
  • 0x5000500CBRR// Baud rate register

    • [0:15]BRR (def=0x0) // BRR
  • 0x50005010GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x50005014RTOR// Receiver timeout register

    • [24:31]BLEN (def=0x0) // Block Length
    • [0:23]RTO (def=0x0) // Receiver timeout value
  • 0x50005018RQR// Request register

    • [4]TXFRQ (def=0x0) // Transmit data flush request
    • [3]RXFRQ (def=0x0) // Receive data flush request
    • [2]MMRQ (def=0x0) // Mute mode request
    • [1]SBKRQ (def=0x0) // Send break request
    • [0]ABRRQ (def=0x0) // Auto baud rate request
  • 0x5000501CISR_enabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [23]TXFE (def=0x1) // TXFE
    • [24]RXFF (def=0x0) // RXFF
    • [25]TCBGT (def=0x1) // TCBGT
    • [26]RXFT (def=0x0) // RXFT
    • [27]TXFT (def=0x0) // TXFT
  • 0x5000501CISR_disabled// Interrupt & status register

    • [22]REACK (def=0x0) // REACK
    • [21]TEACK (def=0x0) // TEACK
    • [19]RWU (def=0x0) // RWU
    • [18]SBKF (def=0x0) // SBKF
    • [17]CMF (def=0x0) // CMF
    • [16]BUSY (def=0x0) // BUSY
    • [15]ABRF (def=0x0) // ABRF
    • [14]ABRE (def=0x0) // ABRE
    • [13]UDR (def=0x0) // UDR
    • [12]EOBF (def=0x0) // EOBF
    • [11]RTOF (def=0x0) // RTOF
    • [10]CTS (def=0x0) // CTS
    • [9]CTSIF (def=0x0) // CTSIF
    • [8]LBDF (def=0x0) // LBDF
    • [7]TXFNF (def=0x1) // TXFNF
    • [6]TC (def=0x1) // TC
    • [5]RXFNE (def=0x0) // RXFNE
    • [4]IDLE (def=0x0) // IDLE
    • [3]ORE (def=0x0) // ORE
    • [2]NE (def=0x0) // NE
    • [1]FE (def=0x0) // FE
    • [0]PE (def=0x0) // PE
    • [25]TCBGT (def=0x0) // TCBGT
  • 0x50005020ICR// Interrupt flag clear register

    • [17]CMCF (def=0x0) // Character match clear flag
    • [12]EOBCF (def=0x0) // End of block clear flag
    • [11]RTOCF (def=0x0) // Receiver timeout clear flag
    • [9]CTSCF (def=0x0) // CTS clear flag
    • [8]LBDCF (def=0x0) // LIN break detection clear flag
    • [6]TCCF (def=0x0) // Transmission complete clear flag
    • [4]IDLECF (def=0x0) // Idle line detected clear flag
    • [3]ORECF (def=0x0) // Overrun error clear flag
    • [2]NECF (def=0x0) // Noise detected clear flag
    • [1]FECF (def=0x0) // Framing error clear flag
    • [0]PECF (def=0x0) // Parity error clear flag
    • [5]TXFECF (def=0x0) // TXFECF
    • [7]TCBGTCF (def=0x0) // TCBGTCF
    • [13]UDRCF (def=0x0) // UDRCF
  • 0x50005024RDR// Receive data register

    • [0:8]RDR (def=0x0) // Receive data value
  • 0x50005028TDR// Transmit data register

    • [0:8]TDR (def=0x0) // Transmit data value
  • 0x5000502CPRESC// PRESC

    • [0:3]PRESCALER (def=0x0) // PRESCALER
  • 0x50005030AUTOCR// AUTOCR

    • [31]TECLREN (def=0x1) // TECLREN
    • [18]IDLEDIS (def=0x0) // IDLEDIS
    • [19:22]TRIGSEL (def=0x0) // TRIGSEL
    • [17]TRIGEN (def=0x0) // TRIGEN
    • [16]TRIGPOL (def=0x0) // TRIPOL
    • [0:15]TDN (def=0x0) // TDN
• 0x420C0400HASH// Hash processor

  • 0x420C0400CR// control register

    • [2]INIT (def=0x0) // Initialize message digest calculation
    • [3]DMAE (def=0x0) // DMA enable
    • [4:5]DATATYPE (def=0x0) // Data type selection
    • [6]MODE (def=0x0) // Mode selection
    • [17:18]ALGO (def=0x0) // Algorithm selection
    • [8:11]NBW (def=0x0) // Number of words already pushed
    • [12]DINNE (def=0x0) // DIN not empty
    • [13]MDMAT (def=0x0) // Multiple DMA Transfers
    • [16]LKEY (def=0x0) // Long key selection
  • 0x420C0404DIN// data input register

    • [0:31]DATAIN (def=0x0) // Data input
  • 0x420C0408STR// start register

    • [8]DCAL (def=0x0) // Digest calculation
    • [0:4]NBLW (def=0x0) // Number of valid bits in the last word of the message
  • 0x420C040CHRA0// HASH aliased digest register 0

    • [0:31]H0 (def=0x0) // H0
  • 0x420C0410HRA1// HASH aliased digest register 1

    • [0:31]H1 (def=0x0) // H1
  • 0x420C0414HRA2// HASH aliased digest register 2

    • [0:31]H2 (def=0x0) // H2
  • 0x420C0418HRA3// HASH aliased digest register 3

    • [0:31]H3 (def=0x0) // H3
  • 0x420C041CHRA4// HASH aliased digest register 4

    • [0:31]H4 (def=0x0) // H4
  • 0x420C0710HR0// digest register 0

    • [0:31]H0 (def=0x0) // H0
  • 0x420C0714HR1// digest register 1

    • [0:31]H1 (def=0x0) // H1
  • 0x420C0718HR2// digest register 4

    • [0:31]H2 (def=0x0) // H2
  • 0x420C071CHR3// digest register 3

    • [0:31]H3 (def=0x0) // H3
  • 0x420C0720HR4// digest register 4

    • [0:31]H4 (def=0x0) // H4
  • 0x420C0724HR5// supplementary digest register 5

    • [0:31]H5 (def=0x0) // H5
  • 0x420C0728HR6// supplementary digest register 6

    • [0:31]H6 (def=0x0) // H6
  • 0x420C072CHR7// supplementary digest register 7

    • [0:31]H7 (def=0x0) // H7
  • 0x420C0420IMR// interrupt enable register

    • [1]DCIE (def=0x0) // Digest calculation completion interrupt enable
    • [0]DINIE (def=0x0) // Data input interrupt enable
  • 0x420C0424SR// status register

    • [3]BUSY (def=0x0) // Busy bit
    • [2]DMAS (def=0x0) // DMA Status
    • [1]DCIS (def=0x0) // Digest calculation completion interrupt status
    • [0]DINIS (def=0x1) // Data input interrupt status
    • [16:20]NBWE (def=0x0) // Number of words expected
    • [15]DINNE (def=0x0) // DIN not empty
    • [9:13]NBWP (def=0x0) // Number of words already pushed
  • 0x420C04F8CSR0// context swap registers

    • [0:31]CSR0 (def=0x0) // CSR0
  • 0x420C04FCCSR1// context swap registers

    • [0:31]CSR1 (def=0x0) // CSR1
  • 0x420C0500CSR2// context swap registers

    • [0:31]CSR2 (def=0x0) // CSR2
  • 0x420C0504CSR3// context swap registers

    • [0:31]CSR3 (def=0x0) // CSR3
  • 0x420C0508CSR4// context swap registers

    • [0:31]CSR4 (def=0x0) // CSR4
  • 0x420C050CCSR5// context swap registers

    • [0:31]CSR5 (def=0x0) // CSR5
  • 0x420C0510CSR6// context swap registers

    • [0:31]CSR6 (def=0x0) // CSR6
  • 0x420C0514CSR7// context swap registers

    • [0:31]CSR7 (def=0x0) // CSR7
  • 0x420C0518CSR8// context swap registers

    • [0:31]CSR8 (def=0x0) // CSR8
  • 0x420C051CCSR9// context swap registers

    • [0:31]CSR9 (def=0x0) // CSR9
  • 0x420C0520CSR10// context swap registers

    • [0:31]CSR10 (def=0x0) // CSR10
  • 0x420C0524CSR11// context swap registers

    • [0:31]CSR11 (def=0x0) // CSR11
  • 0x420C0528CSR12// context swap registers

    • [0:31]CSR12 (def=0x0) // CSR12
  • 0x420C052CCSR13// context swap registers

    • [0:31]CSR13 (def=0x0) // CSR13
  • 0x420C0530CSR14// context swap registers

    • [0:31]CSR14 (def=0x0) // CSR14
  • 0x420C0534CSR15// context swap registers

    • [0:31]CSR15 (def=0x0) // CSR15
  • 0x420C0538CSR16// context swap registers

    • [0:31]CSR16 (def=0x0) // CSR16
  • 0x420C053CCSR17// context swap registers

    • [0:31]CSR17 (def=0x0) // CSR17
  • 0x420C0540CSR18// context swap registers

    • [0:31]CSR18 (def=0x0) // CSR18
  • 0x420C0544CSR19// context swap registers

    • [0:31]CSR19 (def=0x0) // CSR19
  • 0x420C0548CSR20// context swap registers

    • [0:31]CSR20 (def=0x0) // CSR20
  • 0x420C054CCSR21// context swap registers

    • [0:31]CSR21 (def=0x0) // CSR21
  • 0x420C0550CSR22// context swap registers

    • [0:31]CSR22 (def=0x0) // CSR22
  • 0x420C0554CSR23// context swap registers

    • [0:31]CSR23 (def=0x0) // CSR23
  • 0x420C0558CSR24// context swap registers

    • [0:31]CSR24 (def=0x0) // CSR24
  • 0x420C055CCSR25// context swap registers

    • [0:31]CSR25 (def=0x0) // CSR25
  • 0x420C0560CSR26// context swap registers

    • [0:31]CSR26 (def=0x0) // CSR26
  • 0x420C0564CSR27// context swap registers

    • [0:31]CSR27 (def=0x0) // CSR27
  • 0x420C0568CSR28// context swap registers

    • [0:31]CSR28 (def=0x0) // CSR28
  • 0x420C056CCSR29// context swap registers

    • [0:31]CSR29 (def=0x0) // CSR29
  • 0x420C0570CSR30// context swap registers

    • [0:31]CSR30 (def=0x0) // CSR30
  • 0x420C0574CSR31// context swap registers

    • [0:31]CSR31 (def=0x0) // CSR31
  • 0x420C0578CSR32// context swap registers

    • [0:31]CSR32 (def=0x0) // CSR32
  • 0x420C057CCSR33// context swap registers

    • [0:31]CSR33 (def=0x0) // CSR33
  • 0x420C0580CSR34// context swap registers

    • [0:31]CSR34 (def=0x0) // CSR34
  • 0x420C0584CSR35// context swap registers

    • [0:31]CSR35 (def=0x0) // CSR35
  • 0x420C0588CSR36// context swap registers

    • [0:31]CSR36 (def=0x0) // CSR36
  • 0x420C058CCSR37// context swap registers

    • [0:31]CSR37 (def=0x0) // CSR37
  • 0x420C0590CSR38// context swap registers

    • [0:31]CSR38 (def=0x0) // CSR38
  • 0x420C0594CSR39// context swap registers

    • [0:31]CSR39 (def=0x0) // CSR39
  • 0x420C0598CSR40// context swap registers

    • [0:31]CSR40 (def=0x0) // CSR40
  • 0x420C059CCSR41// context swap registers

    • [0:31]CSR41 (def=0x0) // CSR41
  • 0x420C05A0CSR42// context swap registers

    • [0:31]CSR42 (def=0x0) // CSR42
  • 0x420C05A4CSR43// context swap registers

    • [0:31]CSR43 (def=0x0) // CSR43
  • 0x420C05A8CSR44// context swap registers

    • [0:31]CSR44 (def=0x0) // CSR44
  • 0x420C05ACCSR45// context swap registers

    • [0:31]CSR45 (def=0x0) // CSR45
  • 0x420C05B0CSR46// context swap registers

    • [0:31]CSR46 (def=0x0) // CSR46
  • 0x420C05B4CSR47// context swap registers

    • [0:31]CSR47 (def=0x0) // CSR47
  • 0x420C05B8CSR48// context swap registers

    • [0:31]CSR48 (def=0x0) // CSR48
  • 0x420C05BCCSR49// context swap registers

    • [0:31]CSR49 (def=0x0) // CSR49
  • 0x420C05C0CSR50// context swap registers

    • [0:31]CSR50 (def=0x0) // CSR50
  • 0x420C05C4CSR51// context swap registers

    • [0:31]CSR51 (def=0x0) // CSR51
  • 0x420C05C8CSR52// context swap registers

    • [0:31]CSR52 (def=0x0) // CSR52
  • 0x420C05CCCSR53// context swap registers

    • [0:31]CSR53 (def=0x0) // CSR53
  interrupts:
  • [96] HASH // HASH interrupt
• 0x520C0400SEC_HASH//

  • 0x520C0400CR// control register

    • [2]INIT (def=0x0) // Initialize message digest calculation
    • [3]DMAE (def=0x0) // DMA enable
    • [4:5]DATATYPE (def=0x0) // Data type selection
    • [6]MODE (def=0x0) // Mode selection
    • [17:18]ALGO (def=0x0) // Algorithm selection
    • [8:11]NBW (def=0x0) // Number of words already pushed
    • [12]DINNE (def=0x0) // DIN not empty
    • [13]MDMAT (def=0x0) // Multiple DMA Transfers
    • [16]LKEY (def=0x0) // Long key selection
  • 0x520C0404DIN// data input register

    • [0:31]DATAIN (def=0x0) // Data input
  • 0x520C0408STR// start register

    • [8]DCAL (def=0x0) // Digest calculation
    • [0:4]NBLW (def=0x0) // Number of valid bits in the last word of the message
  • 0x520C040CHRA0// HASH aliased digest register 0

    • [0:31]H0 (def=0x0) // H0
  • 0x520C0410HRA1// HASH aliased digest register 1

    • [0:31]H1 (def=0x0) // H1
  • 0x520C0414HRA2// HASH aliased digest register 2

    • [0:31]H2 (def=0x0) // H2
  • 0x520C0418HRA3// HASH aliased digest register 3

    • [0:31]H3 (def=0x0) // H3
  • 0x520C041CHRA4// HASH aliased digest register 4

    • [0:31]H4 (def=0x0) // H4
  • 0x520C0710HR0// digest register 0

    • [0:31]H0 (def=0x0) // H0
  • 0x520C0714HR1// digest register 1

    • [0:31]H1 (def=0x0) // H1
  • 0x520C0718HR2// digest register 4

    • [0:31]H2 (def=0x0) // H2
  • 0x520C071CHR3// digest register 3

    • [0:31]H3 (def=0x0) // H3
  • 0x520C0720HR4// digest register 4

    • [0:31]H4 (def=0x0) // H4
  • 0x520C0724HR5// supplementary digest register 5

    • [0:31]H5 (def=0x0) // H5
  • 0x520C0728HR6// supplementary digest register 6

    • [0:31]H6 (def=0x0) // H6
  • 0x520C072CHR7// supplementary digest register 7

    • [0:31]H7 (def=0x0) // H7
  • 0x520C0420IMR// interrupt enable register

    • [1]DCIE (def=0x0) // Digest calculation completion interrupt enable
    • [0]DINIE (def=0x0) // Data input interrupt enable
  • 0x520C0424SR// status register

    • [3]BUSY (def=0x0) // Busy bit
    • [2]DMAS (def=0x0) // DMA Status
    • [1]DCIS (def=0x0) // Digest calculation completion interrupt status
    • [0]DINIS (def=0x1) // Data input interrupt status
    • [16:20]NBWE (def=0x0) // Number of words expected
    • [15]DINNE (def=0x0) // DIN not empty
    • [9:13]NBWP (def=0x0) // Number of words already pushed
  • 0x520C04F8CSR0// context swap registers

    • [0:31]CSR0 (def=0x0) // CSR0
  • 0x520C04FCCSR1// context swap registers

    • [0:31]CSR1 (def=0x0) // CSR1
  • 0x520C0500CSR2// context swap registers

    • [0:31]CSR2 (def=0x0) // CSR2
  • 0x520C0504CSR3// context swap registers

    • [0:31]CSR3 (def=0x0) // CSR3
  • 0x520C0508CSR4// context swap registers

    • [0:31]CSR4 (def=0x0) // CSR4
  • 0x520C050CCSR5// context swap registers

    • [0:31]CSR5 (def=0x0) // CSR5
  • 0x520C0510CSR6// context swap registers

    • [0:31]CSR6 (def=0x0) // CSR6
  • 0x520C0514CSR7// context swap registers

    • [0:31]CSR7 (def=0x0) // CSR7
  • 0x520C0518CSR8// context swap registers

    • [0:31]CSR8 (def=0x0) // CSR8
  • 0x520C051CCSR9// context swap registers

    • [0:31]CSR9 (def=0x0) // CSR9
  • 0x520C0520CSR10// context swap registers

    • [0:31]CSR10 (def=0x0) // CSR10
  • 0x520C0524CSR11// context swap registers

    • [0:31]CSR11 (def=0x0) // CSR11
  • 0x520C0528CSR12// context swap registers

    • [0:31]CSR12 (def=0x0) // CSR12
  • 0x520C052CCSR13// context swap registers

    • [0:31]CSR13 (def=0x0) // CSR13
  • 0x520C0530CSR14// context swap registers

    • [0:31]CSR14 (def=0x0) // CSR14
  • 0x520C0534CSR15// context swap registers

    • [0:31]CSR15 (def=0x0) // CSR15
  • 0x520C0538CSR16// context swap registers

    • [0:31]CSR16 (def=0x0) // CSR16
  • 0x520C053CCSR17// context swap registers

    • [0:31]CSR17 (def=0x0) // CSR17
  • 0x520C0540CSR18// context swap registers

    • [0:31]CSR18 (def=0x0) // CSR18
  • 0x520C0544CSR19// context swap registers

    • [0:31]CSR19 (def=0x0) // CSR19
  • 0x520C0548CSR20// context swap registers

    • [0:31]CSR20 (def=0x0) // CSR20
  • 0x520C054CCSR21// context swap registers

    • [0:31]CSR21 (def=0x0) // CSR21
  • 0x520C0550CSR22// context swap registers

    • [0:31]CSR22 (def=0x0) // CSR22
  • 0x520C0554CSR23// context swap registers

    • [0:31]CSR23 (def=0x0) // CSR23
  • 0x520C0558CSR24// context swap registers

    • [0:31]CSR24 (def=0x0) // CSR24
  • 0x520C055CCSR25// context swap registers

    • [0:31]CSR25 (def=0x0) // CSR25
  • 0x520C0560CSR26// context swap registers

    • [0:31]CSR26 (def=0x0) // CSR26
  • 0x520C0564CSR27// context swap registers

    • [0:31]CSR27 (def=0x0) // CSR27
  • 0x520C0568CSR28// context swap registers

    • [0:31]CSR28 (def=0x0) // CSR28
  • 0x520C056CCSR29// context swap registers

    • [0:31]CSR29 (def=0x0) // CSR29
  • 0x520C0570CSR30// context swap registers

    • [0:31]CSR30 (def=0x0) // CSR30
  • 0x520C0574CSR31// context swap registers

    • [0:31]CSR31 (def=0x0) // CSR31
  • 0x520C0578CSR32// context swap registers

    • [0:31]CSR32 (def=0x0) // CSR32
  • 0x520C057CCSR33// context swap registers

    • [0:31]CSR33 (def=0x0) // CSR33
  • 0x520C0580CSR34// context swap registers

    • [0:31]CSR34 (def=0x0) // CSR34
  • 0x520C0584CSR35// context swap registers

    • [0:31]CSR35 (def=0x0) // CSR35
  • 0x520C0588CSR36// context swap registers

    • [0:31]CSR36 (def=0x0) // CSR36
  • 0x520C058CCSR37// context swap registers

    • [0:31]CSR37 (def=0x0) // CSR37
  • 0x520C0590CSR38// context swap registers

    • [0:31]CSR38 (def=0x0) // CSR38
  • 0x520C0594CSR39// context swap registers

    • [0:31]CSR39 (def=0x0) // CSR39
  • 0x520C0598CSR40// context swap registers

    • [0:31]CSR40 (def=0x0) // CSR40
  • 0x520C059CCSR41// context swap registers

    • [0:31]CSR41 (def=0x0) // CSR41
  • 0x520C05A0CSR42// context swap registers

    • [0:31]CSR42 (def=0x0) // CSR42
  • 0x520C05A4CSR43// context swap registers

    • [0:31]CSR43 (def=0x0) // CSR43
  • 0x520C05A8CSR44// context swap registers

    • [0:31]CSR44 (def=0x0) // CSR44
  • 0x520C05ACCSR45// context swap registers

    • [0:31]CSR45 (def=0x0) // CSR45
  • 0x520C05B0CSR46// context swap registers

    • [0:31]CSR46 (def=0x0) // CSR46
  • 0x520C05B4CSR47// context swap registers

    • [0:31]CSR47 (def=0x0) // CSR47
  • 0x520C05B8CSR48// context swap registers

    • [0:31]CSR48 (def=0x0) // CSR48
  • 0x520C05BCCSR49// context swap registers

    • [0:31]CSR49 (def=0x0) // CSR49
  • 0x520C05C0CSR50// context swap registers

    • [0:31]CSR50 (def=0x0) // CSR50
  • 0x520C05C4CSR51// context swap registers

    • [0:31]CSR51 (def=0x0) // CSR51
  • 0x520C05C8CSR52// context swap registers

    • [0:31]CSR52 (def=0x0) // CSR52
  • 0x520C05CCCSR53// context swap registers

    • [0:31]CSR53 (def=0x0) // CSR53
• 0x46007C00TAMP// Tamper and backup registers

  • 0x46007C00TAMP_CR1// TAMP control register 1

    • [0]TAMP1E (def=0x0) // Tamper detection on TAMP_IN1 enable
    • [1]TAMP2E (def=0x0) // Tamper detection on TAMP_IN2 enable
    • [2]TAMP3E (def=0x0) // Tamper detection on TAMP_IN3 enable
    • [3]TAMP4E (def=0x0) // Tamper detection on TAMP_IN4 enable
    • [4]TAMP5E (def=0x0) // Tamper detection on TAMP_IN5 enable
    • [5]TAMP6E (def=0x0) // Tamper detection on TAMP_IN6 enable
    • [6]TAMP7E (def=0x0) // Tamper detection on TAMP_IN7 enable
    • [7]TAMP8E (def=0x0) // Tamper detection on TAMP_IN8 enable
    • [16]ITAMP1E (def=0x0) // Internal tamper 1 enable
    • [17]ITAMP2E (def=0x0) // Internal tamper 2 enable
    • [18]ITAMP3E (def=0x0) // Internal tamper 3 enable
    • [20]ITAMP5E (def=0x0) // Internal tamper 5 enable
    • [21]ITAMP6E (def=0x0) // Internal tamper 6 enable
    • [22]ITAMP7E (def=0x0) // Internal tamper 7 enable
    • [23]ITAMP8E (def=0x0) // Internal tamper 8 enable
    • [24]ITAMP9E (def=0x0) // Internal tamper 9 enable
    • [26]ITAMP11E (def=0x0) // Internal tamper 11 enable
    • [27]ITAMP12E (def=0x0) // Internal tamper 12 enable
    • [28]ITAMP13E (def=0x0) // Internal tamper 13 enable
  • 0x46007C04TAMP_CR2// TAMP control register 2

    • [0]TAMP1NOER (def=0x0) // Tamper 1 no erase
    • [1]TAMP2NOER (def=0x0) // Tamper 2 no erase
    • [2]TAMP3NOER (def=0x0) // Tamper 3 no erase
    • [3]TAMP4NOER (def=0x0) // Tamper 4 no erase
    • [4]TAMP5NOER (def=0x0) // Tamper 5 no erase
    • [5]TAMP6NOER (def=0x0) // Tamper 6 no erase
    • [6]TAMP7NOER (def=0x0) // Tamper 7 no erase
    • [7]TAMP8NOER (def=0x0) // Tamper 8 no erase
    • [16]TAMP1MSK (def=0x0) // Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
    • [17]TAMP2MSK (def=0x0) // Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
    • [18]TAMP3MSK (def=0x0) // Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
    • [22]BKBLOCK (def=0x0) // Backup registers and device secrets access blocked
    • [23]BKERASE (def=0x0) // Backup registers and device secrets erase Writing '1€™ to this bit reset the backup registers and
    • [24]TAMP1TRG (def=0x0) // Active level for tamper 1 input If TAMPFLT = 00 Tamper 1 input rising edge and high level trigger
    • [25]TAMP2TRG (def=0x0) // Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers
    • [26]TAMP3TRG (def=0x0) // Active level for tamper 3 input If TAMPFLT = 00 Tamper 3 input rising edge and high level trigger
    • [27]TAMP4TRG (def=0x0) // Active level for tamper 4 input (active mode disabled) If TAMPFLT = 00 Tamper 4 input rising edge
    • [28]TAMP5TRG (def=0x0) // Active level for tamper 5 input (active mode disabled) If TAMPFLT = 00 Tamper 5 input rising edge
    • [29]TAMP6TRG (def=0x0) // Active level for tamper 6 input (active mode disabled) If TAMPFLT = 00 Tamper 6 input rising edge
    • [30]TAMP7TRG (def=0x0) // Active level for tamper 7 input (active mode disabled) If TAMPFLT = 00 Tamper 7 input rising edge
    • [31]TAMP8TRG (def=0x0) // Active level for tamper 8 input (active mode disabled) If TAMPFLT = 00 Tamper 8 input rising edge
  • 0x46007C08TAMP_CR3// TAMP control register 3

    • [0]ITAMP1NOER (def=0x0) // Internal Tamper 1 no erase
    • [1]ITAMP2NOER (def=0x0) // Internal Tamper 2 no erase
    • [2]ITAMP3NOER (def=0x0) // Internal Tamper 3 no erase
    • [4]ITAMP5NOER (def=0x0) // Internal Tamper 5 no erase
    • [5]ITAMP6NOER (def=0x0) // Internal Tamper 6 no erase
    • [6]ITAMP7NOER (def=0x0) // Internal Tamper 7 no erase
    • [7]ITAMP8NOER (def=0x0) // Internal Tamper 8 no erase
    • [8]ITAMP9NOER (def=0x0) // Internal Tamper 9 no erase
    • [10]ITAMP11NOER (def=0x0) // Internal Tamper 11 no erase
    • [11]ITAMP12NOER (def=0x0) // Internal Tamper 12 no erase
    • [12]ITAMP13NOER (def=0x0) // Internal Tamper 13 no erase
  • 0x46007C0CTAMP_FLTCR// TAMP filter control register

    • [0:2]TAMPFREQ (def=0x0) // Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled
    • [3:4]TAMPFLT (def=0x0) // TAMP_INx filter count These bits determines the number of consecutive samples at the specified leve
    • [5:6]TAMPPRCH (def=0x0) // TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is a
    • [7]TAMPPUDIS (def=0x0) // TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each s
  • 0x46007C10TAMP_ATCR1// TAMP active tamper control register 1

    • [0]TAMP1AM (def=0x0) // Tamper 1 active mode
    • [1]TAMP2AM (def=0x0) // Tamper 2 active mode
    • [2]TAMP3AM (def=0x0) // Tamper 3 active mode
    • [3]TAMP4AM (def=0x0) // Tamper 4 active mode
    • [4]TAMP5AM (def=0x0) // Tamper 5 active mode
    • [5]TAMP6AM (def=0x0) // Tamper 6 active mode
    • [6]TAMP7AM (def=0x0) // Tamper 7 active mode
    • [7]TAMP8AM (def=0x0) // Tamper 8 active mode
    • [8:9]ATOSEL1 (def=0x0) // Active tamper shared output 1 selection The selected output must be available in the package pinout
    • [10:11]ATOSEL2 (def=0x0) // Active tamper shared output 2 selection The selected output must be available in the package pinout
    • [12:13]ATOSEL3 (def=0x0) // Active tamper shared output 3 selection The selected output must be available in the package pinout
    • [14:15]ATOSEL4 (def=0x0) // Active tamper shared output 4 selection The selected output must be available in the package pinout
    • [16:18]ATCKSEL (def=0x7) // Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous pr
    • [24:26]ATPER (def=0x0) // Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE
    • [30]ATOSHARE (def=0x0) // Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOU
    • [31]FLTEN (def=0x0) // Active tamper filter enable
  • 0x46007C14TAMP_ATSEEDR// TAMP active tamper seed register

    • [0:31]SEED (def=0x0) // Pseudo-random generator seed value This register must be written four times with 32-bit values to p
  • 0x46007C18TAMP_ATOR// TAMP active tamper output register

    • [0:7]PRNG (def=0x0) // Pseudo-random generator value This field provides the values of the PRNG output. Because of potenti
    • [14]SEEDF (def=0x0) // Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It i
    • [15]INITS (def=0x0) // Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the fir
  • 0x46007C1CTAMP_ATCR2// TAMP active tamper control register 2

    • [8:10]ATOSEL1 (def=0x0) // Active tamper shared output 1 selection The selected output must be available in the package pinout
    • [11:13]ATOSEL2 (def=0x0) // Active tamper shared output 2 selection The selected output must be available in the package pinout
    • [14:16]ATOSEL3 (def=0x0) // Active tamper shared output 3 selection The selected output must be available in the package pinout
    • [17:19]ATOSEL4 (def=0x0) // Active tamper shared output 4 selection The selected output must be available in the package pinout
    • [20:22]ATOSEL5 (def=0x0) // Active tamper shared output 5 selection The selected output must be available in the package pinout
    • [23:25]ATOSEL6 (def=0x0) // Active tamper shared output 6 selection The selected output must be available in the package pinout
    • [26:28]ATOSEL7 (def=0x0) // Active tamper shared output 7 selection The selected output must be available in the package pinout
    • [29:31]ATOSEL8 (def=0x0) // Active tamper shared output 8 selection The selected output must be available in the package pinout
  • 0x46007C20TAMP_SECCFGR// TAMP secure mode register

    • [0:7]BKPRWSEC (def=0x0) // Backup registers read/write protection offset Protection zone 1 is defined for backup registers fro
    • [15]CNT1SEC (def=0x0) // Monotonic counter 1 secure protection
    • [16:23]BKPWSEC (def=0x0) // Backup registers write protection offset Protection zone 2 is defined for backup registers from TAM
    • [30]BHKLOCK (def=0x0) // Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared
    • [31]TAMPSEC (def=0x0) // Tamper protection (excluding monotonic counters and backup registers) Note: Refer to for details o
  • 0x46007C24TAMP_PRIVCR// TAMP privilege mode control register

    • [15]CNT1PRIV (def=0x0) // Monotonic counter 1 privilege protection
    • [29]BKPRWPRIV (def=0x0) // Backup registers zone 1 privilege protection
    • [30]BKPWPRIV (def=0x0) // Backup registers zone 2 privilege protection
    • [31]TAMPPRIV (def=0x0) // Tamper privilege protection (excluding backup registers) Note: Refer to for details on the read pr
  • 0x46007C2CTAMP_IER// TAMP interrupt enable register

    • [0]TAMP1IE (def=0x0) // Tamper 1 interrupt enable
    • [1]TAMP2IE (def=0x0) // Tamper 2 interrupt enable
    • [2]TAMP3IE (def=0x0) // Tamper 3 interrupt enable
    • [3]TAMP4IE (def=0x0) // Tamper 4 interrupt enable
    • [4]TAMP5IE (def=0x0) // Tamper 5 interrupt enable
    • [5]TAMP6IE (def=0x0) // Tamper 6 interrupt enable
    • [6]TAMP7IE (def=0x0) // Tamper 7interrupt enable
    • [7]TAMP8IE (def=0x0) // Tamper 8 interrupt enable
    • [16]ITAMP1IE (def=0x0) // Internal tamper 1 interrupt enable
    • [17]ITAMP2IE (def=0x0) // Internal tamper 2 interrupt enable
    • [18]ITAMP3IE (def=0x0) // Internal tamper 3 interrupt enable
    • [20]ITAMP5IE (def=0x0) // Internal tamper 5 interrupt enable
    • [21]ITAMP6IE (def=0x0) // Internal tamper 6 interrupt enable
    • [22]ITAMP7IE (def=0x0) // Internal tamper 7 interrupt enable
    • [23]ITAMP8IE (def=0x0) // Internal tamper 8 interrupt enable
    • [24]ITAMP9IE (def=0x0) // Internal tamper 9 interrupt enable
    • [26]ITAMP11IE (def=0x0) // Internal tamper 11 interrupt enable
    • [27]ITAMP12IE (def=0x0) // Internal tamper 12 interrupt enable
    • [28]ITAMP13IE (def=0x0) // Internal tamper 13 interrupt enable
  • 0x46007C30TAMP_SR// TAMP status register

    • [0]TAMP1F (def=0x0) // TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [1]TAMP2F (def=0x0) // TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [2]TAMP3F (def=0x0) // TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [3]TAMP4F (def=0x0) // TAMP4 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [4]TAMP5F (def=0x0) // TAMP5 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [5]TAMP6F (def=0x0) // TAMP6 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [6]TAMP7F (def=0x0) // TAMP7 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [7]TAMP8F (def=0x0) // TAMP8 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [16]ITAMP1F (def=0x0) // Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on th
    • [17]ITAMP2F (def=0x0) // Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on th
    • [18]ITAMP3F (def=0x0) // Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on th
    • [20]ITAMP5F (def=0x0) // Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on th
    • [21]ITAMP6F (def=0x0) // Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on th
    • [22]ITAMP7F (def=0x0) // Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on th
    • [23]ITAMP8F (def=0x0) // Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on th
    • [24]ITAMP9F (def=0x0) // Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on th
    • [26]ITAMP11F (def=0x0) // Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on t
    • [27]ITAMP12F (def=0x0) // Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on t
    • [28]ITAMP13F (def=0x0) // Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on t
  • 0x46007C34TAMP_MISR// TAMP non-secure masked interrupt status register

    • [0]TAMP1MF (def=0x0) // TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure in
    • [1]TAMP2MF (def=0x0) // TAMP2 non-secure interrupt masked flag This flag is set by hardware when the tamper 2 non-secure in
    • [2]TAMP3MF (def=0x0) // TAMP3 non-secure interrupt masked flag This flag is set by hardware when the tamper 3 non-secure in
    • [3]TAMP4MF (def=0x0) // TAMP4 non-secure interrupt masked flag This flag is set by hardware when the tamper 4 non-secure in
    • [4]TAMP5MF (def=0x0) // TAMP5 non-secure interrupt masked flag This flag is set by hardware when the tamper 5 non-secure in
    • [5]TAMP6MF (def=0x0) // TAMP6 non-secure interrupt masked flag This flag is set by hardware when the tamper 6 non-secure in
    • [6]TAMP7MF (def=0x0) // TAMP7 non-secure interrupt masked flag This flag is set by hardware when the tamper 7 non-secure in
    • [7]TAMP8MF (def=0x0) // TAMP8 non-secure interrupt masked flag This flag is set by hardware when the tamper 8 non-secure in
    • [16]ITAMP1MF (def=0x0) // Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [17]ITAMP2MF (def=0x0) // Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [18]ITAMP3MF (def=0x0) // Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [20]ITAMP5MF (def=0x0) // Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [21]ITAMP6MF (def=0x0) // Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [22]ITAMP7MF (def=0x0) // VCORE monitoring tamper non-secure interrupt masked flag This flag is set by hardware when the inte
    • [23]ITAMP8MF (def=0x0) // Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [24]ITAMP9MF (def=0x0) // internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [26]ITAMP11MF (def=0x0) // internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal
    • [27]ITAMP12MF (def=0x0) // internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal
    • [28]ITAMP13MF (def=0x0) // internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal
  • 0x46007C38TAMP_SMISR// TAMP secure masked interrupt status register

    • [0]TAMP1MF (def=0x0) // TAMP1 secure interrupt masked flag This flag is set by hardware when the tamper 1 secure interrupt
    • [1]TAMP2MF (def=0x0) // TAMP2 secure interrupt masked flag This flag is set by hardware when the tamper 2 secure interrupt
    • [2]TAMP3MF (def=0x0) // TAMP3 secure interrupt masked flag This flag is set by hardware when the tamper 3 secure interrupt
    • [3]TAMP4MF (def=0x0) // TAMP4 secure interrupt masked flag This flag is set by hardware when the tamper 4 secure interrupt
    • [4]TAMP5MF (def=0x0) // TAMP5 secure interrupt masked flag This flag is set by hardware when the tamper 5 secure interrupt
    • [5]TAMP6MF (def=0x0) // TAMP6 secure interrupt masked flag This flag is set by hardware when the tamper 6 secure interrupt
    • [6]TAMP7MF (def=0x0) // TAMP7 secure interrupt masked flag This flag is set by hardware when the tamper 7 secure interrupt
    • [7]TAMP8MF (def=0x0) // TAMP8 secure interrupt masked flag This flag is set by hardware when the tamper 8 secure interrupt
    • [16]ITAMP1MF (def=0x0) // Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [17]ITAMP2MF (def=0x0) // Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [18]ITAMP3MF (def=0x0) // Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [20]ITAMP5MF (def=0x0) // Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [21]ITAMP6MF (def=0x0) // Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [22]ITAMP7MF (def=0x0) // VCORE monitoring tamper secure interrupt masked flag This flag is set by hardware when the internal
    • [23]ITAMP8MF (def=0x0) // Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [24]ITAMP9MF (def=0x0) // internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [26]ITAMP11MF (def=0x0) // internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamp
    • [27]ITAMP12MF (def=0x0) // internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamp
    • [28]ITAMP13MF (def=0x0) // internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamp
  • 0x46007C3CTAMP_SCR// TAMP status clear register

    • [0]CTAMP1F (def=0x0) // Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
    • [1]CTAMP2F (def=0x0) // Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
    • [2]CTAMP3F (def=0x0) // Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
    • [3]CTAMP4F (def=0x0) // Clear TAMP4 detection flag Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register.
    • [4]CTAMP5F (def=0x0) // Clear TAMP5 detection flag Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register.
    • [5]CTAMP6F (def=0x0) // Clear TAMP6 detection flag Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register.
    • [6]CTAMP7F (def=0x0) // Clear TAMP7 detection flag Writing 1 in this bit clears the TAMP7F bit in the TAMP_SR register.
    • [7]CTAMP8F (def=0x0) // Clear TAMP8 detection flag Writing 1 in this bit clears the TAMP8F bit in the TAMP_SR register.
    • [16]CITAMP1F (def=0x0) // Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register.
    • [17]CITAMP2F (def=0x0) // Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register.
    • [18]CITAMP3F (def=0x0) // Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
    • [20]CITAMP5F (def=0x0) // Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
    • [21]CITAMP6F (def=0x0) // Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
    • [22]CITAMP7F (def=0x0) // Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register.
    • [23]CITAMP8F (def=0x0) // Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register.
    • [24]CITAMP9F (def=0x0) // Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register.
    • [26]CITAMP11F (def=0x0) // Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register.
    • [27]CITAMP12F (def=0x0) // Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register.
    • [28]CITAMP13F (def=0x0) // Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register.
  • 0x46007C40TAMP_COUNT1R// TAMP monotonic counter 1 register

    • [0:31]COUNT (def=0x0) // This register is read-only only and is incremented by one when a write access is done to this regis
  • 0x46007C54TAMP_ERCFGR// TAMP erase configuration register

    • [0]ERCFG0 (def=0x0) // Configurable device secrets configuration
  • 0x46007D00TAMP_BKP0R// TAMP backup 0 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D04TAMP_BKP1R// TAMP backup 1 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D08TAMP_BKP2R// TAMP backup 2 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D0CTAMP_BKP3R// TAMP backup 3 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D10TAMP_BKP4R// TAMP backup 4 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D14TAMP_BKP5R// TAMP backup 5 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D18TAMP_BKP6R// TAMP backup 6 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D1CTAMP_BKP7R// TAMP backup 7 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D20TAMP_BKP8R// TAMP backup 8 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D24TAMP_BKP9R// TAMP backup 9 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D28TAMP_BKP10R// TAMP backup 10 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D2CTAMP_BKP11R// TAMP backup 11 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D30TAMP_BKP12R// TAMP backup 12 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D34TAMP_BKP13R// TAMP backup 13 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D38TAMP_BKP14R// TAMP backup 14 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D3CTAMP_BKP15R// TAMP backup 15 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D40TAMP_BKP16R// TAMP backup 16 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D44TAMP_BKP17R// TAMP backup 17 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D48TAMP_BKP18R// TAMP backup 18 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D4CTAMP_BKP19R// TAMP backup 19 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D50TAMP_BKP20R// TAMP backup 20 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D54TAMP_BKP21R// TAMP backup 21 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D58TAMP_BKP22R// TAMP backup 22 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D5CTAMP_BKP23R// TAMP backup 23 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D60TAMP_BKP24R// TAMP backup 24 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D64TAMP_BKP25R// TAMP backup 25 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D68TAMP_BKP26R// TAMP backup 26 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D6CTAMP_BKP27R// TAMP backup 27 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D70TAMP_BKP28R// TAMP backup 28 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D74TAMP_BKP29R// TAMP backup 29 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D78TAMP_BKP30R// TAMP backup 30 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x46007D7CTAMP_BKP31R// TAMP backup 31 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  interrupts:
  • [4] TAMP // Tamper global interrupts
• 0x56007C00SEC_TAMP//

  • 0x56007C00TAMP_CR1// TAMP control register 1

    • [0]TAMP1E (def=0x0) // Tamper detection on TAMP_IN1 enable
    • [1]TAMP2E (def=0x0) // Tamper detection on TAMP_IN2 enable
    • [2]TAMP3E (def=0x0) // Tamper detection on TAMP_IN3 enable
    • [3]TAMP4E (def=0x0) // Tamper detection on TAMP_IN4 enable
    • [4]TAMP5E (def=0x0) // Tamper detection on TAMP_IN5 enable
    • [5]TAMP6E (def=0x0) // Tamper detection on TAMP_IN6 enable
    • [6]TAMP7E (def=0x0) // Tamper detection on TAMP_IN7 enable
    • [7]TAMP8E (def=0x0) // Tamper detection on TAMP_IN8 enable
    • [16]ITAMP1E (def=0x0) // Internal tamper 1 enable
    • [17]ITAMP2E (def=0x0) // Internal tamper 2 enable
    • [18]ITAMP3E (def=0x0) // Internal tamper 3 enable
    • [20]ITAMP5E (def=0x0) // Internal tamper 5 enable
    • [21]ITAMP6E (def=0x0) // Internal tamper 6 enable
    • [22]ITAMP7E (def=0x0) // Internal tamper 7 enable
    • [23]ITAMP8E (def=0x0) // Internal tamper 8 enable
    • [24]ITAMP9E (def=0x0) // Internal tamper 9 enable
    • [26]ITAMP11E (def=0x0) // Internal tamper 11 enable
    • [27]ITAMP12E (def=0x0) // Internal tamper 12 enable
    • [28]ITAMP13E (def=0x0) // Internal tamper 13 enable
  • 0x56007C04TAMP_CR2// TAMP control register 2

    • [0]TAMP1NOER (def=0x0) // Tamper 1 no erase
    • [1]TAMP2NOER (def=0x0) // Tamper 2 no erase
    • [2]TAMP3NOER (def=0x0) // Tamper 3 no erase
    • [3]TAMP4NOER (def=0x0) // Tamper 4 no erase
    • [4]TAMP5NOER (def=0x0) // Tamper 5 no erase
    • [5]TAMP6NOER (def=0x0) // Tamper 6 no erase
    • [6]TAMP7NOER (def=0x0) // Tamper 7 no erase
    • [7]TAMP8NOER (def=0x0) // Tamper 8 no erase
    • [16]TAMP1MSK (def=0x0) // Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
    • [17]TAMP2MSK (def=0x0) // Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
    • [18]TAMP3MSK (def=0x0) // Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
    • [22]BKBLOCK (def=0x0) // Backup registers and device secrets access blocked
    • [23]BKERASE (def=0x0) // Backup registers and device secrets erase Writing '1€™ to this bit reset the backup registers and
    • [24]TAMP1TRG (def=0x0) // Active level for tamper 1 input If TAMPFLT = 00 Tamper 1 input rising edge and high level trigger
    • [25]TAMP2TRG (def=0x0) // Active level for tamper 2 input If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers
    • [26]TAMP3TRG (def=0x0) // Active level for tamper 3 input If TAMPFLT = 00 Tamper 3 input rising edge and high level trigger
    • [27]TAMP4TRG (def=0x0) // Active level for tamper 4 input (active mode disabled) If TAMPFLT = 00 Tamper 4 input rising edge
    • [28]TAMP5TRG (def=0x0) // Active level for tamper 5 input (active mode disabled) If TAMPFLT = 00 Tamper 5 input rising edge
    • [29]TAMP6TRG (def=0x0) // Active level for tamper 6 input (active mode disabled) If TAMPFLT = 00 Tamper 6 input rising edge
    • [30]TAMP7TRG (def=0x0) // Active level for tamper 7 input (active mode disabled) If TAMPFLT = 00 Tamper 7 input rising edge
    • [31]TAMP8TRG (def=0x0) // Active level for tamper 8 input (active mode disabled) If TAMPFLT = 00 Tamper 8 input rising edge
  • 0x56007C08TAMP_CR3// TAMP control register 3

    • [0]ITAMP1NOER (def=0x0) // Internal Tamper 1 no erase
    • [1]ITAMP2NOER (def=0x0) // Internal Tamper 2 no erase
    • [2]ITAMP3NOER (def=0x0) // Internal Tamper 3 no erase
    • [4]ITAMP5NOER (def=0x0) // Internal Tamper 5 no erase
    • [5]ITAMP6NOER (def=0x0) // Internal Tamper 6 no erase
    • [6]ITAMP7NOER (def=0x0) // Internal Tamper 7 no erase
    • [7]ITAMP8NOER (def=0x0) // Internal Tamper 8 no erase
    • [8]ITAMP9NOER (def=0x0) // Internal Tamper 9 no erase
    • [10]ITAMP11NOER (def=0x0) // Internal Tamper 11 no erase
    • [11]ITAMP12NOER (def=0x0) // Internal Tamper 12 no erase
    • [12]ITAMP13NOER (def=0x0) // Internal Tamper 13 no erase
  • 0x56007C0CTAMP_FLTCR// TAMP filter control register

    • [0:2]TAMPFREQ (def=0x0) // Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled
    • [3:4]TAMPFLT (def=0x0) // TAMP_INx filter count These bits determines the number of consecutive samples at the specified leve
    • [5:6]TAMPPRCH (def=0x0) // TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is a
    • [7]TAMPPUDIS (def=0x0) // TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each s
  • 0x56007C10TAMP_ATCR1// TAMP active tamper control register 1

    • [0]TAMP1AM (def=0x0) // Tamper 1 active mode
    • [1]TAMP2AM (def=0x0) // Tamper 2 active mode
    • [2]TAMP3AM (def=0x0) // Tamper 3 active mode
    • [3]TAMP4AM (def=0x0) // Tamper 4 active mode
    • [4]TAMP5AM (def=0x0) // Tamper 5 active mode
    • [5]TAMP6AM (def=0x0) // Tamper 6 active mode
    • [6]TAMP7AM (def=0x0) // Tamper 7 active mode
    • [7]TAMP8AM (def=0x0) // Tamper 8 active mode
    • [8:9]ATOSEL1 (def=0x0) // Active tamper shared output 1 selection The selected output must be available in the package pinout
    • [10:11]ATOSEL2 (def=0x0) // Active tamper shared output 2 selection The selected output must be available in the package pinout
    • [12:13]ATOSEL3 (def=0x0) // Active tamper shared output 3 selection The selected output must be available in the package pinout
    • [14:15]ATOSEL4 (def=0x0) // Active tamper shared output 4 selection The selected output must be available in the package pinout
    • [16:18]ATCKSEL (def=0x7) // Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous pr
    • [24:26]ATPER (def=0x0) // Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE
    • [30]ATOSHARE (def=0x0) // Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOU
    • [31]FLTEN (def=0x0) // Active tamper filter enable
  • 0x56007C14TAMP_ATSEEDR// TAMP active tamper seed register

    • [0:31]SEED (def=0x0) // Pseudo-random generator seed value This register must be written four times with 32-bit values to p
  • 0x56007C18TAMP_ATOR// TAMP active tamper output register

    • [0:7]PRNG (def=0x0) // Pseudo-random generator value This field provides the values of the PRNG output. Because of potenti
    • [14]SEEDF (def=0x0) // Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It i
    • [15]INITS (def=0x0) // Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the fir
  • 0x56007C1CTAMP_ATCR2// TAMP active tamper control register 2

    • [8:10]ATOSEL1 (def=0x0) // Active tamper shared output 1 selection The selected output must be available in the package pinout
    • [11:13]ATOSEL2 (def=0x0) // Active tamper shared output 2 selection The selected output must be available in the package pinout
    • [14:16]ATOSEL3 (def=0x0) // Active tamper shared output 3 selection The selected output must be available in the package pinout
    • [17:19]ATOSEL4 (def=0x0) // Active tamper shared output 4 selection The selected output must be available in the package pinout
    • [20:22]ATOSEL5 (def=0x0) // Active tamper shared output 5 selection The selected output must be available in the package pinout
    • [23:25]ATOSEL6 (def=0x0) // Active tamper shared output 6 selection The selected output must be available in the package pinout
    • [26:28]ATOSEL7 (def=0x0) // Active tamper shared output 7 selection The selected output must be available in the package pinout
    • [29:31]ATOSEL8 (def=0x0) // Active tamper shared output 8 selection The selected output must be available in the package pinout
  • 0x56007C20TAMP_SECCFGR// TAMP secure mode register

    • [0:7]BKPRWSEC (def=0x0) // Backup registers read/write protection offset Protection zone 1 is defined for backup registers fro
    • [15]CNT1SEC (def=0x0) // Monotonic counter 1 secure protection
    • [16:23]BKPWSEC (def=0x0) // Backup registers write protection offset Protection zone 2 is defined for backup registers from TAM
    • [30]BHKLOCK (def=0x0) // Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared
    • [31]TAMPSEC (def=0x0) // Tamper protection (excluding monotonic counters and backup registers) Note: Refer to for details o
  • 0x56007C24TAMP_PRIVCR// TAMP privilege mode control register

    • [15]CNT1PRIV (def=0x0) // Monotonic counter 1 privilege protection
    • [29]BKPRWPRIV (def=0x0) // Backup registers zone 1 privilege protection
    • [30]BKPWPRIV (def=0x0) // Backup registers zone 2 privilege protection
    • [31]TAMPPRIV (def=0x0) // Tamper privilege protection (excluding backup registers) Note: Refer to for details on the read pr
  • 0x56007C2CTAMP_IER// TAMP interrupt enable register

    • [0]TAMP1IE (def=0x0) // Tamper 1 interrupt enable
    • [1]TAMP2IE (def=0x0) // Tamper 2 interrupt enable
    • [2]TAMP3IE (def=0x0) // Tamper 3 interrupt enable
    • [3]TAMP4IE (def=0x0) // Tamper 4 interrupt enable
    • [4]TAMP5IE (def=0x0) // Tamper 5 interrupt enable
    • [5]TAMP6IE (def=0x0) // Tamper 6 interrupt enable
    • [6]TAMP7IE (def=0x0) // Tamper 7interrupt enable
    • [7]TAMP8IE (def=0x0) // Tamper 8 interrupt enable
    • [16]ITAMP1IE (def=0x0) // Internal tamper 1 interrupt enable
    • [17]ITAMP2IE (def=0x0) // Internal tamper 2 interrupt enable
    • [18]ITAMP3IE (def=0x0) // Internal tamper 3 interrupt enable
    • [20]ITAMP5IE (def=0x0) // Internal tamper 5 interrupt enable
    • [21]ITAMP6IE (def=0x0) // Internal tamper 6 interrupt enable
    • [22]ITAMP7IE (def=0x0) // Internal tamper 7 interrupt enable
    • [23]ITAMP8IE (def=0x0) // Internal tamper 8 interrupt enable
    • [24]ITAMP9IE (def=0x0) // Internal tamper 9 interrupt enable
    • [26]ITAMP11IE (def=0x0) // Internal tamper 11 interrupt enable
    • [27]ITAMP12IE (def=0x0) // Internal tamper 12 interrupt enable
    • [28]ITAMP13IE (def=0x0) // Internal tamper 13 interrupt enable
  • 0x56007C30TAMP_SR// TAMP status register

    • [0]TAMP1F (def=0x0) // TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [1]TAMP2F (def=0x0) // TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [2]TAMP3F (def=0x0) // TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [3]TAMP4F (def=0x0) // TAMP4 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [4]TAMP5F (def=0x0) // TAMP5 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [5]TAMP6F (def=0x0) // TAMP6 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [6]TAMP7F (def=0x0) // TAMP7 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [7]TAMP8F (def=0x0) // TAMP8 detection flag This flag is set by hardware when a tamper detection event is detected on the
    • [16]ITAMP1F (def=0x0) // Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on th
    • [17]ITAMP2F (def=0x0) // Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on th
    • [18]ITAMP3F (def=0x0) // Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on th
    • [20]ITAMP5F (def=0x0) // Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on th
    • [21]ITAMP6F (def=0x0) // Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on th
    • [22]ITAMP7F (def=0x0) // Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on th
    • [23]ITAMP8F (def=0x0) // Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on th
    • [24]ITAMP9F (def=0x0) // Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on th
    • [26]ITAMP11F (def=0x0) // Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on t
    • [27]ITAMP12F (def=0x0) // Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on t
    • [28]ITAMP13F (def=0x0) // Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on t
  • 0x56007C34TAMP_MISR// TAMP non-secure masked interrupt status register

    • [0]TAMP1MF (def=0x0) // TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure in
    • [1]TAMP2MF (def=0x0) // TAMP2 non-secure interrupt masked flag This flag is set by hardware when the tamper 2 non-secure in
    • [2]TAMP3MF (def=0x0) // TAMP3 non-secure interrupt masked flag This flag is set by hardware when the tamper 3 non-secure in
    • [3]TAMP4MF (def=0x0) // TAMP4 non-secure interrupt masked flag This flag is set by hardware when the tamper 4 non-secure in
    • [4]TAMP5MF (def=0x0) // TAMP5 non-secure interrupt masked flag This flag is set by hardware when the tamper 5 non-secure in
    • [5]TAMP6MF (def=0x0) // TAMP6 non-secure interrupt masked flag This flag is set by hardware when the tamper 6 non-secure in
    • [6]TAMP7MF (def=0x0) // TAMP7 non-secure interrupt masked flag This flag is set by hardware when the tamper 7 non-secure in
    • [7]TAMP8MF (def=0x0) // TAMP8 non-secure interrupt masked flag This flag is set by hardware when the tamper 8 non-secure in
    • [16]ITAMP1MF (def=0x0) // Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [17]ITAMP2MF (def=0x0) // Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [18]ITAMP3MF (def=0x0) // Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [20]ITAMP5MF (def=0x0) // Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [21]ITAMP6MF (def=0x0) // Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [22]ITAMP7MF (def=0x0) // VCORE monitoring tamper non-secure interrupt masked flag This flag is set by hardware when the inte
    • [23]ITAMP8MF (def=0x0) // Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [24]ITAMP9MF (def=0x0) // internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal t
    • [26]ITAMP11MF (def=0x0) // internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal
    • [27]ITAMP12MF (def=0x0) // internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal
    • [28]ITAMP13MF (def=0x0) // internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal
  • 0x56007C38TAMP_SMISR// TAMP secure masked interrupt status register

    • [0]TAMP1MF (def=0x0) // TAMP1 secure interrupt masked flag This flag is set by hardware when the tamper 1 secure interrupt
    • [1]TAMP2MF (def=0x0) // TAMP2 secure interrupt masked flag This flag is set by hardware when the tamper 2 secure interrupt
    • [2]TAMP3MF (def=0x0) // TAMP3 secure interrupt masked flag This flag is set by hardware when the tamper 3 secure interrupt
    • [3]TAMP4MF (def=0x0) // TAMP4 secure interrupt masked flag This flag is set by hardware when the tamper 4 secure interrupt
    • [4]TAMP5MF (def=0x0) // TAMP5 secure interrupt masked flag This flag is set by hardware when the tamper 5 secure interrupt
    • [5]TAMP6MF (def=0x0) // TAMP6 secure interrupt masked flag This flag is set by hardware when the tamper 6 secure interrupt
    • [6]TAMP7MF (def=0x0) // TAMP7 secure interrupt masked flag This flag is set by hardware when the tamper 7 secure interrupt
    • [7]TAMP8MF (def=0x0) // TAMP8 secure interrupt masked flag This flag is set by hardware when the tamper 8 secure interrupt
    • [16]ITAMP1MF (def=0x0) // Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [17]ITAMP2MF (def=0x0) // Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [18]ITAMP3MF (def=0x0) // Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [20]ITAMP5MF (def=0x0) // Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [21]ITAMP6MF (def=0x0) // Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [22]ITAMP7MF (def=0x0) // VCORE monitoring tamper secure interrupt masked flag This flag is set by hardware when the internal
    • [23]ITAMP8MF (def=0x0) // Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [24]ITAMP9MF (def=0x0) // internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tampe
    • [26]ITAMP11MF (def=0x0) // internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamp
    • [27]ITAMP12MF (def=0x0) // internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamp
    • [28]ITAMP13MF (def=0x0) // internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamp
  • 0x56007C3CTAMP_SCR// TAMP status clear register

    • [0]CTAMP1F (def=0x0) // Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
    • [1]CTAMP2F (def=0x0) // Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
    • [2]CTAMP3F (def=0x0) // Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
    • [3]CTAMP4F (def=0x0) // Clear TAMP4 detection flag Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register.
    • [4]CTAMP5F (def=0x0) // Clear TAMP5 detection flag Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register.
    • [5]CTAMP6F (def=0x0) // Clear TAMP6 detection flag Writing 1 in this bit clears the TAMP6F bit in the TAMP_SR register.
    • [6]CTAMP7F (def=0x0) // Clear TAMP7 detection flag Writing 1 in this bit clears the TAMP7F bit in the TAMP_SR register.
    • [7]CTAMP8F (def=0x0) // Clear TAMP8 detection flag Writing 1 in this bit clears the TAMP8F bit in the TAMP_SR register.
    • [16]CITAMP1F (def=0x0) // Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register.
    • [17]CITAMP2F (def=0x0) // Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register.
    • [18]CITAMP3F (def=0x0) // Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
    • [20]CITAMP5F (def=0x0) // Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
    • [21]CITAMP6F (def=0x0) // Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
    • [22]CITAMP7F (def=0x0) // Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register.
    • [23]CITAMP8F (def=0x0) // Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register.
    • [24]CITAMP9F (def=0x0) // Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register.
    • [26]CITAMP11F (def=0x0) // Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register.
    • [27]CITAMP12F (def=0x0) // Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register.
    • [28]CITAMP13F (def=0x0) // Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register.
  • 0x56007C40TAMP_COUNT1R// TAMP monotonic counter 1 register

    • [0:31]COUNT (def=0x0) // This register is read-only only and is incremented by one when a write access is done to this regis
  • 0x56007C54TAMP_ERCFGR// TAMP erase configuration register

    • [0]ERCFG0 (def=0x0) // Configurable device secrets configuration
  • 0x56007D00TAMP_BKP0R// TAMP backup 0 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D04TAMP_BKP1R// TAMP backup 1 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D08TAMP_BKP2R// TAMP backup 2 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D0CTAMP_BKP3R// TAMP backup 3 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D10TAMP_BKP4R// TAMP backup 4 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D14TAMP_BKP5R// TAMP backup 5 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D18TAMP_BKP6R// TAMP backup 6 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D1CTAMP_BKP7R// TAMP backup 7 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D20TAMP_BKP8R// TAMP backup 8 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D24TAMP_BKP9R// TAMP backup 9 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D28TAMP_BKP10R// TAMP backup 10 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D2CTAMP_BKP11R// TAMP backup 11 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D30TAMP_BKP12R// TAMP backup 12 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D34TAMP_BKP13R// TAMP backup 13 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D38TAMP_BKP14R// TAMP backup 14 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D3CTAMP_BKP15R// TAMP backup 15 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D40TAMP_BKP16R// TAMP backup 16 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D44TAMP_BKP17R// TAMP backup 17 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D48TAMP_BKP18R// TAMP backup 18 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D4CTAMP_BKP19R// TAMP backup 19 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D50TAMP_BKP20R// TAMP backup 20 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D54TAMP_BKP21R// TAMP backup 21 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D58TAMP_BKP22R// TAMP backup 22 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D5CTAMP_BKP23R// TAMP backup 23 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D60TAMP_BKP24R// TAMP backup 24 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D64TAMP_BKP25R// TAMP backup 25 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D68TAMP_BKP26R// TAMP backup 26 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D6CTAMP_BKP27R// TAMP backup 27 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D70TAMP_BKP28R// TAMP backup 28 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D74TAMP_BKP29R// TAMP backup 29 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D78TAMP_BKP30R// TAMP backup 30 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
  • 0x56007D7CTAMP_BKP31R// TAMP backup 31 register

    • [0:31]BKP (def=0x0) // The application can write or read data to and from these registers. In the default (ERASE) configur
• 0x40025000MDF1// Multi-function digital filter

  • 0x40025000GCR// MDF global control register

    • [0]TRGO (def=0x0) // TRGO
    • [4:7]ILVNB (def=0x0) // ILVNB
  • 0x40025004CKGCR// MDF clock generator control register

    • [0]CKGDEN (def=0x0) // CKGDEN
    • [1]CCK0EN (def=0x0) // CCK0EN
    • [2]CCK1EN (def=0x0) // CCK1EN
    • [4]CKGMOD (def=0x0) // CKGMOD
    • [5]CCK0DIR (def=0x0) // CCK0DIR
    • [6]CCK1DIR (def=0x0) // CCK1DIR
    • [8]TRGSENS (def=0x0) // TRGSENS
    • [12:15]TRGSRC (def=0x0) // TRGSRC
    • [16:19]CCKDIV (def=0x0) // CCKDIV
    • [24:30]PROCDIV (def=0x0) // PROCDIV
    • [31]CKGACTIVE (def=0x0) // CKGACTIVE
  • 0x40025080MDF_SITF0CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x40025100MDF_SITF1CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag
  • 0x40025180MDF_SITF2CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag
  • 0x40025200MDF_SITF3CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x40025280MDF_SITF4CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x40025300MDF_SITF5CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x40025084MDF_BSMX0CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025104MDF_BSMX1CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025184MDF_BSMX2CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025204MDF_BSMX3CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025284MDF_BSMX4CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025304MDF_BSMX5CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025088MDF_DFLT0CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software.
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x40025108MDF_DFLT1CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x40025188MDF_DFLT2CR// This register is used to control the digital filter 2.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x40025208MDF_DFLT3CR// This register is used to control the digital filter 3.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x40025288MDF_DFLT4CR// This register is used to control the digital filter 4.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x40025308MDF_DFLT5CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x4002508CMDF_DFLT0CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x4002510CMDF_DFLT1CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x4002518CMDF_DFLT2CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x4002520CMDF_DFLT3CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x4002528CMDF_DFLT4CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x4002530CMDF_DFLT5CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x40025090MDF_DFLT0RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025110MDF_DFLT1RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025190MDF_DFLT2RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025210MDF_DFLT3RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025290MDF_DFLT4RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025310MDF_DFLT5RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x40025094MDF_DFLT0INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025114MDF_DFLT1INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025194MDF_DFLT2INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025214MDF_DFLT3INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025294MDF_DFLT4INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025314MDF_DFLT5INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x40025098MDF_OLD0CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025118MDF_OLD1CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025198MDF_OLD2CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025218MDF_OLD3CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025298MDF_OLD4CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025318MDF_OLD5CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x4002509CMDF_OLD0THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x4002511CMDF_OLD1THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x4002519CMDF_OLD2THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x4002521CMDF_OLD3THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x4002529CMDF_OLD4THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x4002531CMDF_OLD5THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x400250A0MDF_OLD0THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x40025120MDF_OLD1THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x400251A0MDF_OLD2THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x40025220MDF_OLD3THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x400252A0MDF_OLD4THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x40025320MDF_OLD5THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x400250A4MDF_DLY0CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x40025124MDF_DLY1CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x400251A4MDF_DLY2CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x40025224MDF_DLY3CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x400252A4MDF_DLY4CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x40025324MDF_DLY5CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x400250A8MDF_SCD0CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025128MDF_SCD1CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x400251A8MDF_SCD2CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025228MDF_SCD3CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x400252A8MDF_SCD4CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x40025328MDF_SCD5CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x400250ACMDF_DFLT0IER// This register is used for allowing or not the events to generate an interrupt.

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x400250B0MDF_DFLT0ISR// MDF DFLT0 interrupt status register 0

    • [0]FTHF (def=0x0) // FTHF
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x4002512CMDF_DFLT1IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x400251ACMDF_DFLT2IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x4002522CMDF_DFLT3IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x400252ACMDF_DFLT4IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x4002532CMDF_DFLT5IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x40025130MDF_DFLT1ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x400251B0MDF_DFLT2ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x40025230MDF_DFLT3ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x400252B0MDF_DFLT4ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x40025330MDF_DFLT5ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x400250B4MDF_OEC0CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x40025134MDF_OEC1CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x400251B4MDF_OEC2CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x40025234MDF_OEC3CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x400252B4MDF_OEC4CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x40025334MDF_OEC5CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x400250ECMDF_SNPS0DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x4002516CMDF_SNPS1DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x400251ECMDF_SNPS2DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x4002526CMDF_SNPS3DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x400252ECMDF_SNPS4DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x4002536CMDF_SNPS5DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x400250F0MDF_DFLT0DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x40025170MDF_DFLT1DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x400251F0MDF_DFLT2DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x40025270MDF_DFLT3DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x400252F0MDF_DFLT4DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x40025370MDF_DFLT5DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  interrupts:
  • [102] MDF1_FLT0 // MDF1 filter 0 global interrupt
  • [103] MDF1_FLT1 // MDF1 filter 1 global interrupt
  • [104] MDF1_FLT2 // MDF1 filter 2 global interrupt
  • [105] MDF1_FLT3 // MDF1 filter 3 global interrupt
  • [121] MDF1_FLT4 // MDF1 filter 4 global interrupt
  • [122] MDF1_FLT5 // MDF1 filter 5 global interrupt
• 0x50025000SEC_MDF1//

  • 0x50025000GCR// MDF global control register

    • [0]TRGO (def=0x0) // TRGO
    • [4:7]ILVNB (def=0x0) // ILVNB
  • 0x50025004CKGCR// MDF clock generator control register

    • [0]CKGDEN (def=0x0) // CKGDEN
    • [1]CCK0EN (def=0x0) // CCK0EN
    • [2]CCK1EN (def=0x0) // CCK1EN
    • [4]CKGMOD (def=0x0) // CKGMOD
    • [5]CCK0DIR (def=0x0) // CCK0DIR
    • [6]CCK1DIR (def=0x0) // CCK1DIR
    • [8]TRGSENS (def=0x0) // TRGSENS
    • [12:15]TRGSRC (def=0x0) // TRGSRC
    • [16:19]CCKDIV (def=0x0) // CCKDIV
    • [24:30]PROCDIV (def=0x0) // PROCDIV
    • [31]CKGACTIVE (def=0x0) // CKGACTIVE
  • 0x50025080MDF_SITF0CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x50025100MDF_SITF1CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag
  • 0x50025180MDF_SITF2CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag
  • 0x50025200MDF_SITF3CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x50025280MDF_SITF4CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x50025300MDF_SITF5CR// This register is used to control the serial interfaces (SITFx).

    • [0]SITFEN (def=0x0) // Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial
    • [1:2]SCKSRC (def=0x0) // Serial clock source Set and cleared by software. This bit is used to select the clock source of the
    • [4:5]SITFMOD (def=0x0) // Serial interface type Set and cleared by software. This field is used to defined the serial interfa
    • [8:12]STH (def=0x1F) // Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Man
    • [31]SITFACTIVE (def=0x0) // Serial interface Active flag Set and cleared by hardware. This flag must be used by the application
  • 0x50025084MDF_BSMX0CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025104MDF_BSMX1CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025184MDF_BSMX2CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025204MDF_BSMX3CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025284MDF_BSMX4CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025304MDF_BSMX5CR// This register is used to select the bitstream to be provided to the corresponding digital filter an

    • [0:4]BSSEL (def=0x0) // Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be p
    • [31]BSMXACTIVE (def=0x0) // BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025088MDF_DFLT0CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software.
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x50025108MDF_DFLT1CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x50025188MDF_DFLT2CR// This register is used to control the digital filter 2.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x50025208MDF_DFLT3CR// This register is used to control the digital filter 3.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x50025288MDF_DFLT4CR// This register is used to control the digital filter 4.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x50025308MDF_DFLT5CR// This register is used to control the digital filter x.

    • [0]DFLTEN (def=0x0) // Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisi
    • [1]DMAEN (def=0x0) // DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA
    • [2]FTH (def=0x0) // RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO thres
    • [4:6]ACQMOD (def=0x0) // Digital filter Trigger mode Set and cleared by software. This field is used to select the filter tr
    • [8]TRGSENS (def=0x0) // Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to sel
    • [12:15]TRGSRC (def=0x0) // Digital filter Trigger signal selection, Set and cleared by software. This field is used to select
    • [16]SNPSFMT (def=0x0) // Snapshot data format Set and cleared by software. This field is used to select the data format for
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded Set and cleared by software. This field is used to define the num
    • [30]DFLTRUN (def=0x0) // Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filte
    • [31]DFLTACTIVE (def=0x0) // Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is
  • 0x5002508CMDF_DFLT0CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x5002510CMDF_DFLT1CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x5002518CMDF_DFLT2CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x5002520CMDF_DFLT3CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x5002528CMDF_DFLT4CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x5002530CMDF_DFLT5CICR// This register is used to control the main CIC filter.

    • [0:1]DATSRC (def=0x0) // Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from t
    • [4:6]CICMOD (def=0x0) // Select the CIC mode Set and cleared by software. This field allows the application to select the co
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection Set and cleared by software. This bit is used to allow the applicati
    • [20:25]SCALE (def=0x0) // Scaling factor selection Set and cleared by software. This field is used to allow the application t
  • 0x50025090MDF_DFLT0RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025110MDF_DFLT1RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025190MDF_DFLT2RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025210MDF_DFLT3RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025290MDF_DFLT4RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025310MDF_DFLT5RSFR// This register is used to control the reshape and HPF filters.

    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter a
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decima
    • [7]HPFBYP (def=0x0) // High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filte
    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cu
  • 0x50025094MDF_DFLT0INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025114MDF_DFLT1INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025194MDF_DFLT2INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025214MDF_DFLT3INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025294MDF_DFLT4INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025314MDF_DFLT5INTR// This register is used to the integrator (INT) settings.

    • [0:1]INTDIV (def=0x0) // Integrator output division Set and cleared by software. This bit is used to rescale the signal at t
    • [4:10]INTVAL (def=0x0) // Integration value selection Set and cleared by software. This field is used to select the integrati
  • 0x50025098MDF_OLD0CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025118MDF_OLD1CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025198MDF_OLD2CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025218MDF_OLD3CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025298MDF_OLD4CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025318MDF_OLD5CR// This register is used to configure the Out-of Limit Detector function.

    • [0]OLDEN (def=0x0) // Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value)
    • [1]THINB (def=0x0) // Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is low
    • [4:7]BKOLD (def=0x0) // Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break
    • [12:13]ACICN (def=0x0) // OLD CIC order selection Set and cleared by software. This field allows the application to select th
    • [17:21]ACICD (def=0x0) // OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the app
    • [31]OLDACTIVE (def=0x0) // OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x5002509CMDF_OLD0THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x5002511CMDF_OLD1THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x5002519CMDF_OLD2THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x5002521CMDF_OLD3THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x5002529CMDF_OLD4THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x5002531CMDF_OLD5THLR// This register is used for the adjustment of the Out-off Limit low threshold.

    • [0:25]OLDTHL (def=0x0) // OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The r
  • 0x500250A0MDF_OLD0THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x50025120MDF_OLD1THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x500251A0MDF_OLD2THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x50025220MDF_OLD3THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x500252A0MDF_OLD4THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x50025320MDF_OLD5THHR// This register is used for the adjustment of the Out-off Limit high threshold.

    • [0:25]OLDTHH (def=0x0) // OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The
  • 0x500250A4MDF_DLY0CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x50025124MDF_DLY1CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x500251A4MDF_DLY2CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x50025224MDF_DLY3CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x500252A4MDF_DLY4CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x50025324MDF_DLY5CR// This register is used for the adjustment stream delays.

    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that
    • [31]SKPBF (def=0x0) // Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence
  • 0x500250A8MDF_SCD0CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025128MDF_SCD1CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x500251A8MDF_SCD2CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025228MDF_SCD3CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x500252A8MDF_SCD4CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x50025328MDF_SCD5CR// This register is used for the adjustment stream delays.

    • [0]SCDEN (def=0x0) // Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disab
    • [4:7]BKSCD (def=0x0) // Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break
    • [12:19]SCDT (def=0x0) // Short-circuit detector threshold Set and cleared by software. These bits are written by software to
    • [31]SCDACTIVE (def=0x0) // SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to
  • 0x500250ACMDF_DFLT0IER// This register is used for allowing or not the events to generate an interrupt.

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x500250B0MDF_DFLT0ISR// MDF DFLT0 interrupt status register 0

    • [0]FTHF (def=0x0) // FTHF
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x5002512CMDF_DFLT1IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x500251ACMDF_DFLT2IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x5002522CMDF_DFLT3IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x500252ACMDF_DFLT4IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x5002532CMDF_DFLT5IER// MDF DFLTx interrupt enable register x

    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disa
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled -
    • [2]SSDRIE (def=0x0) // Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrup
    • [4]OLDIE (def=0x0) // Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: O
    • [7]SSOVRIE (def=0x0) // Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disa
    • [8]SCDIE (def=0x0) // Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled -
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabl
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt
    • [11]RFOVRIE (def=0x0) // Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun in
  • 0x50025130MDF_DFLT1ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x500251B0MDF_DFLT2ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x50025230MDF_DFLT3ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x500252B0MDF_DFLT4ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x50025330MDF_DFLT5ISR// This register contains the status flags for each digital filter path.

    • [0]FTHF (def=0x0) // RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [1]DOVRF (def=0x0) // Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Readin
    • [2]SSDRF (def=0x0) // Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [3]RXNEF (def=0x0) // RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 m
    • [4]OLDF (def=0x0) // Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0
    • [5]THLF (def=0x0) // Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This
    • [6]THHF (def=0x0) // High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . Thi
    • [7]SSOVRF (def=0x0) // Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Rea
    • [8]SCDF (def=0x0) // Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [9]SATF (def=0x0) // Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0:
    • [10]CKABF (def=0x0) // Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . -
    • [11]RFOVRF (def=0x0) // Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit
  • 0x500250B4MDF_OEC0CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x50025134MDF_OEC1CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x500251B4MDF_OEC2CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x50025234MDF_OEC3CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x500252B4MDF_OEC4CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x50025334MDF_OEC5CR// This register contains the offset compensation value.

    • [0:25]OFFSET (def=0x0) // Offset error compensation Set and cleared by software. If the application attempts to write a new o
  • 0x500250ECMDF_SNPS0DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x5002516CMDF_SNPS1DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x500251ECMDF_SNPS2DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x5002526CMDF_SNPS3DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x500252ECMDF_SNPS4DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x5002536CMDF_SNPS5DR// This register is used to read the data processed by each digital filter in snapshot mode.

    • [0:8]MCICDC (def=0x0) // Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT
    • [9:15]EXTSDR (def=0x0) // Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data pro
    • [16:31]SDR (def=0x0) // Contains the 16 MSB of the last valid data processed by the digital filter.
  • 0x500250F0MDF_DFLT0DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x50025170MDF_DFLT1DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x500251F0MDF_DFLT2DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x50025270MDF_DFLT3DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x500252F0MDF_DFLT4DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
  • 0x50025370MDF_DFLT5DR// This register is used to read the data processed by each digital filter.

    • [8:31]DR (def=0x0) // Data processed by digital filter.
• 0x46024000ADF1// ADF1

  • 0x46024000ADF_GCR// ADF Global Control Register

    • [0]TRGO (def=0x0) // Trigger output control Set by software and reset by
  • 0x46024004ADF_CKGCR// ADF clock generator control register

    • [31]CKGACTIVE (def=0x0) // Clock generator active flag
    • [24:30]PROCDIV (def=0x0) // Divider to control the serial interface clock
    • [16:19]CCKDIV (def=0x0) // Divider to control the ADF_CCK clock
    • [12:15]TRGSRC (def=0x0) // Digital filter trigger signal selection
    • [8]TRGSENS (def=0x0) // CKGEN trigger sensitivity selection
    • [6]CCK1DIR (def=0x0) // ADF_CCK1 direction
    • [5]CCK0DIR (def=0x0) // ADF_CCK0 direction
    • [4]CKGMOD (def=0x0) // Clock generator mode
    • [2]CCK1EN (def=0x0) // ADF_CCK1 clock enable
    • [1]CCK0EN (def=0x0) // ADF_CCK0 clock enable
    • [0]CKGDEN (def=0x0) // CKGEN dividers enable
  • 0x46024080ADF_SITF0CR// ADF serial interface control register 0

    • [31]SITFACTIVE (def=0x0) // SITFACTIVE
    • [8:12]STH (def=0x1F) // STH
    • [4:5]SITFMOD (def=0x0) // SITFMOD
    • [1:2]SCKSRC (def=0x0) // SCKSRC
    • [0]SITFEN (def=0x0) // SITFEN
  • 0x46024084ADF_BSMX0CR// ADF bitstream matrix control register 0

    • [31]BSMXACTIVE (def=0x0) // BSMX active flag
    • [0:4]BSSEL (def=0x0) // Bitstream selection
  • 0x46024088ADF_DFLT0CR// ADF digital filter control register 0

    • [31]DFLTACTIVE (def=0x0) // DFLT0 active flag
    • [30]DFLTRUN (def=0x0) // DFLT0 run status flag
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded
    • [12:15]TRGSRC (def=0x0) // DFLT0 trigger signal selection
    • [4:6]ACQMOD (def=0x0) // DFLT0 trigger mode
    • [2]FTH (def=0x0) // RXFIFO threshold selection
    • [1]DMAEN (def=0x0) // DMA requests enable
    • [0]DFLTEN (def=0x0) // DFLT0 enable
  • 0x4602408CADF_DFLT0CICR// ADF digital filer configuration register 0

    • [20:25]SCALE (def=0x0) // Scaling factor selection
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection
    • [4:6]CICMOD (def=0x0) // Select the CIC order
    • [0:1]DATSRC (def=0x0) // Source data for the digital filter
  • 0x46024090ADF_DFLT0RSFR// ADF reshape filter configuration register 0

    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency
    • [7]HPFBYP (def=0x0) // High-pass filter bypass
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio
    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass
  • 0x460240A4ADF_DLY0CR// ADF delay control register 0

    • [31]SKPBF (def=0x0) // Skip busy flag
    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream
  • 0x460240ACADF_DFLT0IER// ADF DFLT0 interrupt enable register

    • [13]SDLVLIE (def=0x0) // SAD sound-level value ready enable
    • [12]SDDETIE (def=0x0) // Sound activity detection interrupt enable
    • [11]RFOVRIE (def=0x0) // Reshape filter overrun interrupt enable
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable
    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable
  • 0x460240B0ADF_DFLT0ISR// ADF DFLT0 interrupt status register 0

    • [13]SDLVLF (def=0x0) // Sound level value ready flag
    • [12]SDDETF (def=0x0) // Sound activity detection flag
    • [11]RFOVRF (def=0x0) // Reshape filter overrun detection flag
    • [10]CKABF (def=0x0) // Clock absence detection flag
    • [9]SATF (def=0x0) // Saturation detection flag
    • [3]RXNEF (def=0x0) // RXFIFO not empty flag
    • [1]DOVRF (def=0x0) // Data overflow flag
    • [0]FTHF (def=0x0) // RXFIFO threshold flag
  • 0x460240B8ADF_SADCR// ADF SAD control register

    • [31]SADACTIVE (def=0x0) // SAD Active flag
    • [12:13]SADMOD (def=0x0) // SAD working mode
    • [8:10]FRSIZE (def=0x0) // Frame size
    • [7]HYSTEN (def=0x0) // Hysteresis enable
    • [4:5]SADST (def=0x0) // SAD state
    • [3]DETCFG (def=0x0) // Sound trigger event configuration
    • [1:2]DATCAP (def=0x0) // Data capture mode
    • [0]SADEN (def=0x0) // Sound activity detector enable
  • 0x460240BCADF_SADCFGR// ADF SAD configuration register

    • [16:28]ANMIN (def=0x0) // ANMIN
    • [12:14]HGOVR (def=0x0) // Hangover time window
    • [8:10]LFRNB (def=0x0) // LFRNB
    • [4:6]ANSLP (def=0x0) // ANSLP
    • [0:3]SNTHR (def=0x0) // SNTHR
  • 0x460240C0ADF_SADSDLVR// ADF SAD sound level register

    • [0:14]SDLVL (def=0x0) // SDLVL
  • 0x460240C4ADF_SADANLVR// ADF SAD ambient noise level register

    • [0:14]ANLVL (def=0x0) // ANLVL
  • 0x460240F0ADF_DFLT0DR// ADF digital filter data register 0

    • [8:31]DR (def=0x0) // DR
  interrupts:
  • [112] ADF1_FLT0 // ADF1 filter 0 global interrupt
• 0x56024000SEC_ADF1//

  • 0x56024000ADF_GCR// ADF Global Control Register

    • [0]TRGO (def=0x0) // Trigger output control Set by software and reset by
  • 0x56024004ADF_CKGCR// ADF clock generator control register

    • [31]CKGACTIVE (def=0x0) // Clock generator active flag
    • [24:30]PROCDIV (def=0x0) // Divider to control the serial interface clock
    • [16:19]CCKDIV (def=0x0) // Divider to control the ADF_CCK clock
    • [12:15]TRGSRC (def=0x0) // Digital filter trigger signal selection
    • [8]TRGSENS (def=0x0) // CKGEN trigger sensitivity selection
    • [6]CCK1DIR (def=0x0) // ADF_CCK1 direction
    • [5]CCK0DIR (def=0x0) // ADF_CCK0 direction
    • [4]CKGMOD (def=0x0) // Clock generator mode
    • [2]CCK1EN (def=0x0) // ADF_CCK1 clock enable
    • [1]CCK0EN (def=0x0) // ADF_CCK0 clock enable
    • [0]CKGDEN (def=0x0) // CKGEN dividers enable
  • 0x56024080ADF_SITF0CR// ADF serial interface control register 0

    • [31]SITFACTIVE (def=0x0) // SITFACTIVE
    • [8:12]STH (def=0x1F) // STH
    • [4:5]SITFMOD (def=0x0) // SITFMOD
    • [1:2]SCKSRC (def=0x0) // SCKSRC
    • [0]SITFEN (def=0x0) // SITFEN
  • 0x56024084ADF_BSMX0CR// ADF bitstream matrix control register 0

    • [31]BSMXACTIVE (def=0x0) // BSMX active flag
    • [0:4]BSSEL (def=0x0) // Bitstream selection
  • 0x56024088ADF_DFLT0CR// ADF digital filter control register 0

    • [31]DFLTACTIVE (def=0x0) // DFLT0 active flag
    • [30]DFLTRUN (def=0x0) // DFLT0 run status flag
    • [20:27]NBDIS (def=0x0) // Number of samples to be discarded
    • [12:15]TRGSRC (def=0x0) // DFLT0 trigger signal selection
    • [4:6]ACQMOD (def=0x0) // DFLT0 trigger mode
    • [2]FTH (def=0x0) // RXFIFO threshold selection
    • [1]DMAEN (def=0x0) // DMA requests enable
    • [0]DFLTEN (def=0x0) // DFLT0 enable
  • 0x5602408CADF_DFLT0CICR// ADF digital filer configuration register 0

    • [20:25]SCALE (def=0x0) // Scaling factor selection
    • [8:16]MCICD (def=0x0) // CIC decimation ratio selection
    • [4:6]CICMOD (def=0x0) // Select the CIC order
    • [0:1]DATSRC (def=0x0) // Source data for the digital filter
  • 0x56024090ADF_DFLT0RSFR// ADF reshape filter configuration register 0

    • [8:9]HPFC (def=0x0) // High-pass filter cut-off frequency
    • [7]HPFBYP (def=0x0) // High-pass filter bypass
    • [4]RSFLTD (def=0x0) // Reshaper filter decimation ratio
    • [0]RSFLTBYP (def=0x0) // Reshaper filter bypass
  • 0x560240A4ADF_DLY0CR// ADF delay control register 0

    • [31]SKPBF (def=0x0) // Skip busy flag
    • [0:6]SKPDLY (def=0x0) // Delay to apply to a bitstream
  • 0x560240ACADF_DFLT0IER// ADF DFLT0 interrupt enable register

    • [13]SDLVLIE (def=0x0) // SAD sound-level value ready enable
    • [12]SDDETIE (def=0x0) // Sound activity detection interrupt enable
    • [11]RFOVRIE (def=0x0) // Reshape filter overrun interrupt enable
    • [10]CKABIE (def=0x0) // Clock absence detection interrupt enable
    • [9]SATIE (def=0x0) // Saturation detection interrupt enable
    • [1]DOVRIE (def=0x0) // Data overflow interrupt enable
    • [0]FTHIE (def=0x0) // RXFIFO threshold interrupt enable
  • 0x560240B0ADF_DFLT0ISR// ADF DFLT0 interrupt status register 0

    • [13]SDLVLF (def=0x0) // Sound level value ready flag
    • [12]SDDETF (def=0x0) // Sound activity detection flag
    • [11]RFOVRF (def=0x0) // Reshape filter overrun detection flag
    • [10]CKABF (def=0x0) // Clock absence detection flag
    • [9]SATF (def=0x0) // Saturation detection flag
    • [3]RXNEF (def=0x0) // RXFIFO not empty flag
    • [1]DOVRF (def=0x0) // Data overflow flag
    • [0]FTHF (def=0x0) // RXFIFO threshold flag
  • 0x560240B8ADF_SADCR// ADF SAD control register

    • [31]SADACTIVE (def=0x0) // SAD Active flag
    • [12:13]SADMOD (def=0x0) // SAD working mode
    • [8:10]FRSIZE (def=0x0) // Frame size
    • [7]HYSTEN (def=0x0) // Hysteresis enable
    • [4:5]SADST (def=0x0) // SAD state
    • [3]DETCFG (def=0x0) // Sound trigger event configuration
    • [1:2]DATCAP (def=0x0) // Data capture mode
    • [0]SADEN (def=0x0) // Sound activity detector enable
  • 0x560240BCADF_SADCFGR// ADF SAD configuration register

    • [16:28]ANMIN (def=0x0) // ANMIN
    • [12:14]HGOVR (def=0x0) // Hangover time window
    • [8:10]LFRNB (def=0x0) // LFRNB
    • [4:6]ANSLP (def=0x0) // ANSLP
    • [0:3]SNTHR (def=0x0) // SNTHR
  • 0x560240C0ADF_SADSDLVR// ADF SAD sound level register

    • [0:14]SDLVL (def=0x0) // SDLVL
  • 0x560240C4ADF_SADANLVR// ADF SAD ambient noise level register

    • [0:14]ANLVL (def=0x0) // ANLVL
  • 0x560240F0ADF_DFLT0DR// ADF digital filter data register 0

    • [8:31]DR (def=0x0) // DR
• 0x46020000LPGPIO1// LPGPIO1

  • 0x46020000LPGPIO_MODER// LPGPIO port mode register

    • [15]MODE15 (def=0x0) // MODE15
    • [14]MODE14 (def=0x0) // MODE14
    • [13]MODE13 (def=0x0) // MODE13
    • [12]MODE12 (def=0x0) // MODE12
    • [11]MODE11 (def=0x0) // MODE11
    • [10]MODE10 (def=0x0) // MODE10
    • [9]MODE9 (def=0x0) // MODE9
    • [8]MODE8 (def=0x0) // MODE8
    • [7]MODE7 (def=0x0) // MODE7
    • [6]MODE6 (def=0x0) // MODE6
    • [5]MODE5 (def=0x0) // MODE5
    • [4]MODE4 (def=0x0) // MODE4
    • [3]MODE3 (def=0x0) // MODE3
    • [2]MODE2 (def=0x0) // MODE2
    • [1]MODE1 (def=0x0) // MODE1
    • [0]MODE0 (def=0x0) // MODE0
  • 0x46020010LPGPIO_IDR// LPGPIO port input data register

    • [0:15]IDy (def=0x0) // IDy
  • 0x46020014LPGPIO_ODR// LPGPIO port output data register

    • [15]ODy15 (def=0x0) // ODy15
    • [14]ODy14 (def=0x0) // ODy14
    • [13]ODy13 (def=0x0) // ODy13
    • [12]ODy12 (def=0x0) // ODy12
    • [11]ODy11 (def=0x0) // ODy11
    • [10]ODy10 (def=0x0) // ODy10
    • [9]ODy9 (def=0x0) // ODy9
    • [8]ODy8 (def=0x0) // ODy8
    • [7]ODy7 (def=0x0) // ODy7
    • [6]ODy6 (def=0x0) // ODy6
    • [5]ODy5 (def=0x0) // ODy5
    • [4]ODy4 (def=0x0) // ODy4
    • [3]ODy3 (def=0x0) // ODy3
    • [2]ODy2 (def=0x0) // ODy2
    • [1]ODy1 (def=0x0) // ODy1
    • [0]ODy0 (def=0x0) // ODy0
  • 0x46020018LPGPIO_BSRR// LPGPIO port bit set/reset register

    • [31]BRy31 (def=0x0) // BRy31
    • [30]BRy30 (def=0x0) // BRy30
    • [29]BRy29 (def=0x0) // BRy29
    • [28]BRy28 (def=0x0) // BRy28
    • [27]BRy27 (def=0x0) // BRy27
    • [26]BRy26 (def=0x0) // BRy26
    • [25]BRy25 (def=0x0) // BRy25
    • [24]BRy24 (def=0x0) // BRy24
    • [23]BRy23 (def=0x0) // BRy23
    • [22]BRy22 (def=0x0) // BRy22
    • [21]BRy21 (def=0x0) // BRy21
    • [20]BRy20 (def=0x0) // BRy20
    • [19]BRy19 (def=0x0) // BRy19
    • [18]BRy18 (def=0x0) // BRy18
    • [17]BRy17 (def=0x0) // BRy17
    • [16]BRy16 (def=0x0) // BRy16
    • [15]BSy15 (def=0x0) // BSy15
    • [14]BSy14 (def=0x0) // BSy14
    • [13]BSy13 (def=0x0) // BSy13
    • [12]BSy12 (def=0x0) // BSy12
    • [11]BSy11 (def=0x0) // BSy11
    • [10]BSy10 (def=0x0) // BSy10
    • [9]BSy9 (def=0x0) // BSy9
    • [8]BSy8 (def=0x0) // BSy8
    • [7]BSy7 (def=0x0) // BSy7
    • [6]BSy6 (def=0x0) // BSy6
    • [5]BSy5 (def=0x0) // BSy5
    • [4]BSy4 (def=0x0) // BSy4
    • [3]BSy3 (def=0x0) // BSy3
    • [2]BSy2 (def=0x0) // BSy2
    • [1]BSy1 (def=0x0) // BSy1
    • [0]BSy0 (def=0x0) // BSy0
  • 0x46020028LPGPIO_BRR// LPGPIO port bit reset register

    • [15]BRy15 (def=0x0) // BRy15
    • [14]BRy14 (def=0x0) // BRy14
    • [13]BRy13 (def=0x0) // BRy13
    • [12]BRy12 (def=0x0) // BRy12
    • [11]BRy11 (def=0x0) // BRy11
    • [10]BRy10 (def=0x0) // BRy10
    • [9]BRy9 (def=0x0) // BRy9
    • [8]BRy8 (def=0x0) // BRy8
    • [7]BRy7 (def=0x0) // BRy7
    • [6]BRy6 (def=0x0) // BRy6
    • [5]BRy5 (def=0x0) // BRy5
    • [4]BRy4 (def=0x0) // BRy4
    • [3]BRy3 (def=0x0) // BRy3
    • [2]BRy2 (def=0x0) // BRy2
    • [1]BRy1 (def=0x0) // BRy1
    • [0]BRy0 (def=0x0) // BRy0
• 0x56020000SEC_LPGPIO1//

  • 0x56020000LPGPIO_MODER// LPGPIO port mode register

    • [15]MODE15 (def=0x0) // MODE15
    • [14]MODE14 (def=0x0) // MODE14
    • [13]MODE13 (def=0x0) // MODE13
    • [12]MODE12 (def=0x0) // MODE12
    • [11]MODE11 (def=0x0) // MODE11
    • [10]MODE10 (def=0x0) // MODE10
    • [9]MODE9 (def=0x0) // MODE9
    • [8]MODE8 (def=0x0) // MODE8
    • [7]MODE7 (def=0x0) // MODE7
    • [6]MODE6 (def=0x0) // MODE6
    • [5]MODE5 (def=0x0) // MODE5
    • [4]MODE4 (def=0x0) // MODE4
    • [3]MODE3 (def=0x0) // MODE3
    • [2]MODE2 (def=0x0) // MODE2
    • [1]MODE1 (def=0x0) // MODE1
    • [0]MODE0 (def=0x0) // MODE0
  • 0x56020010LPGPIO_IDR// LPGPIO port input data register

    • [0:15]IDy (def=0x0) // IDy
  • 0x56020014LPGPIO_ODR// LPGPIO port output data register

    • [15]ODy15 (def=0x0) // ODy15
    • [14]ODy14 (def=0x0) // ODy14
    • [13]ODy13 (def=0x0) // ODy13
    • [12]ODy12 (def=0x0) // ODy12
    • [11]ODy11 (def=0x0) // ODy11
    • [10]ODy10 (def=0x0) // ODy10
    • [9]ODy9 (def=0x0) // ODy9
    • [8]ODy8 (def=0x0) // ODy8
    • [7]ODy7 (def=0x0) // ODy7
    • [6]ODy6 (def=0x0) // ODy6
    • [5]ODy5 (def=0x0) // ODy5
    • [4]ODy4 (def=0x0) // ODy4
    • [3]ODy3 (def=0x0) // ODy3
    • [2]ODy2 (def=0x0) // ODy2
    • [1]ODy1 (def=0x0) // ODy1
    • [0]ODy0 (def=0x0) // ODy0
  • 0x56020018LPGPIO_BSRR// LPGPIO port bit set/reset register

    • [31]BRy31 (def=0x0) // BRy31
    • [30]BRy30 (def=0x0) // BRy30
    • [29]BRy29 (def=0x0) // BRy29
    • [28]BRy28 (def=0x0) // BRy28
    • [27]BRy27 (def=0x0) // BRy27
    • [26]BRy26 (def=0x0) // BRy26
    • [25]BRy25 (def=0x0) // BRy25
    • [24]BRy24 (def=0x0) // BRy24
    • [23]BRy23 (def=0x0) // BRy23
    • [22]BRy22 (def=0x0) // BRy22
    • [21]BRy21 (def=0x0) // BRy21
    • [20]BRy20 (def=0x0) // BRy20
    • [19]BRy19 (def=0x0) // BRy19
    • [18]BRy18 (def=0x0) // BRy18
    • [17]BRy17 (def=0x0) // BRy17
    • [16]BRy16 (def=0x0) // BRy16
    • [15]BSy15 (def=0x0) // BSy15
    • [14]BSy14 (def=0x0) // BSy14
    • [13]BSy13 (def=0x0) // BSy13
    • [12]BSy12 (def=0x0) // BSy12
    • [11]BSy11 (def=0x0) // BSy11
    • [10]BSy10 (def=0x0) // BSy10
    • [9]BSy9 (def=0x0) // BSy9
    • [8]BSy8 (def=0x0) // BSy8
    • [7]BSy7 (def=0x0) // BSy7
    • [6]BSy6 (def=0x0) // BSy6
    • [5]BSy5 (def=0x0) // BSy5
    • [4]BSy4 (def=0x0) // BSy4
    • [3]BSy3 (def=0x0) // BSy3
    • [2]BSy2 (def=0x0) // BSy2
    • [1]BSy1 (def=0x0) // BSy1
    • [0]BSy0 (def=0x0) // BSy0
  • 0x56020028LPGPIO_BRR// LPGPIO port bit reset register

    • [15]BRy15 (def=0x0) // BRy15
    • [14]BRy14 (def=0x0) // BRy14
    • [13]BRy13 (def=0x0) // BRy13
    • [12]BRy12 (def=0x0) // BRy12
    • [11]BRy11 (def=0x0) // BRy11
    • [10]BRy10 (def=0x0) // BRy10
    • [9]BRy9 (def=0x0) // BRy9
    • [8]BRy8 (def=0x0) // BRy8
    • [7]BRy7 (def=0x0) // BRy7
    • [6]BRy6 (def=0x0) // BRy6
    • [5]BRy5 (def=0x0) // BRy5
    • [4]BRy4 (def=0x0) // BRy4
    • [3]BRy3 (def=0x0) // BRy3
    • [2]BRy2 (def=0x0) // BRy2
    • [1]BRy1 (def=0x0) // BRy1
    • [0]BRy0 (def=0x0) // BRy0
• 0x420C4000OCTOSPIM// OCTOSPI I/O manager

  • 0x420C4000CR// control register

    • [16:23]REQ2ACK_TIME (def=0x0) // REQ to ACK time
    • [0]MUXEN (def=0x0) // Multiplexed mode enable
  • 0x420C4004P1CR// OCTOSPI I/O manager Port 1 configuration register

    • [25:26]IOHSRC (def=0x1) // IOHSR
    • [24]IOHEN (def=0x1) // IOHEN
    • [17:18]IOLSRC (def=0x0) // IOLSRC
    • [16]IOLEN (def=0x1) // IOLEN
    • [9]NCSSRC (def=0x0) // NCSSRC
    • [8]NCSEN (def=0x1) // NCSEN
    • [5]DQSSRC (def=0x0) // DQSSRC
    • [4]DQSEN (def=0x1) // DQSEN
    • [1]CLKSRC (def=0x0) // CLKSRC
    • [0]CLKEN (def=0x1) // CLKEN
  • 0x420C4008P2CR// OCTOSPI I/O manager Port 2 configuration register

    • [25:26]IOHSRC (def=0x3) // IOHSR
    • [24]IOHEN (def=0x1) // IOHEN
    • [17:18]IOLSRC (def=0x2) // IOLSRC
    • [16]IOLEN (def=0x1) // IOLEN
    • [9]NCSSRC (def=0x1) // NCSSRC
    • [8]NCSEN (def=0x1) // NCSEN
    • [5]DQSSRC (def=0x1) // DQSSRC
    • [4]DQSEN (def=0x1) // DQSEN
    • [1]CLKSRC (def=0x1) // CLKSRC
    • [0]CLKEN (def=0x1) // CLKEN
• 0x520C4000SEC_OCTOSPIM//

  • 0x520C4000CR// control register

    • [16:23]REQ2ACK_TIME (def=0x0) // REQ to ACK time
    • [0]MUXEN (def=0x0) // Multiplexed mode enable
  • 0x520C4004P1CR// OCTOSPI I/O manager Port 1 configuration register

    • [25:26]IOHSRC (def=0x1) // IOHSR
    • [24]IOHEN (def=0x1) // IOHEN
    • [17:18]IOLSRC (def=0x0) // IOLSRC
    • [16]IOLEN (def=0x1) // IOLEN
    • [9]NCSSRC (def=0x0) // NCSSRC
    • [8]NCSEN (def=0x1) // NCSEN
    • [5]DQSSRC (def=0x0) // DQSSRC
    • [4]DQSEN (def=0x1) // DQSEN
    • [1]CLKSRC (def=0x0) // CLKSRC
    • [0]CLKEN (def=0x1) // CLKEN
  • 0x520C4008P2CR// OCTOSPI I/O manager Port 2 configuration register

    • [25:26]IOHSRC (def=0x3) // IOHSR
    • [24]IOHEN (def=0x1) // IOHEN
    • [17:18]IOLSRC (def=0x2) // IOLSRC
    • [16]IOLEN (def=0x1) // IOLEN
    • [9]NCSSRC (def=0x1) // NCSSRC
    • [8]NCSEN (def=0x1) // NCSEN
    • [5]DQSSRC (def=0x1) // DQSSRC
    • [4]DQSEN (def=0x1) // DQSEN
    • [1]CLKSRC (def=0x1) // CLKSRC
    • [0]CLKEN (def=0x1) // CLKEN
• 0x42028000ADC1// ADC1

  • 0x42028000ADC_ISR// ADC interrupt and status register

    • [0]ADRDY (def=0x0) // ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the
    • [1]EOSMP (def=0x0) // End of sampling flag This bit is set by hardware during the conversion of any channel (only for reg
    • [2]EOC (def=0x0) // End of conversion flag This bit is set by hardware at the end of each regular conversion of a chann
    • [3]EOS (def=0x0) // End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular
    • [4]OVR (def=0x0) // ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a
    • [5]JEOC (def=0x0) // Injected channel end of conversion flag This bit is set by hardware at the end of each injected con
    • [6]JEOS (def=0x0) // Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of
    • [7]AWD1 (def=0x0) // Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [8]AWD2 (def=0x0) // Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [9]AWD3 (def=0x0) // Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [12]LDORDY (def=0x0) // ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply
  • 0x42028004ADC_IER// ADC interrupt enable register

    • [0]ADRDYIE (def=0x0) // ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready
    • [1]EOSMPIE (def=0x0) // End of sampling flag interrupt enable for regular conversions This bit is set and cleared by softwa
    • [2]EOCIE (def=0x0) // End of regular conversion interrupt enable This bit is set and cleared by software to enable/disabl
    • [3]EOSIE (def=0x0) // End of regular sequence of conversions interrupt enable This bit is set and cleared by software to
    • [4]OVRIE (def=0x0) // Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun inte
    • [5]JEOCIE (def=0x0) // End of injected conversion interrupt enable This bit is set and cleared by software to enable/disab
    • [6]JEOSIE (def=0x0) // End of injected sequence of conversions interrupt enable This bit is set and cleared by software to
    • [7]AWD1IE (def=0x0) // Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the an
    • [8]AWD2IE (def=0x0) // Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the an
    • [9]AWD3IE (def=0x0) // Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the an
  • 0x42028008ADC_CR// ADC control register

    • [0]ADEN (def=0x0) // ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to o
    • [1]ADDIS (def=0x0) // ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into
    • [2]ADSTART (def=0x0) // ADC start of regular conversion This bit is set by software to start ADC conversion of regular chan
    • [3]JADSTART (def=0x0) // ADC start of injected conversion This bit is set by software to start ADC conversion of injected ch
    • [4]ADSTP (def=0x0) // ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing r
    • [5]JADSTP (def=0x0) // ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing
    • [16]ADCALLIN (def=0x0) // Linearity calibration This bit is set and cleared by software to enable the linearity calibration.
    • [24:27]CALINDEX (def=0x0) // Calibration factor This bitfield controls the calibration factor to be read or written. Calibration
    • [28]ADVREGEN (def=0x0) // ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Befo
    • [29]DEEPPWD (def=0x1) // Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mo
    • [31]ADCAL (def=0x0) // ADC calibration This bit is set by software to start the ADC calibration. It is cleared by hardware
  • 0x4202800CADC_CFGR1// ADC configuration register

    • [0:1]DMNGT (def=0x0) // Data management configuration This bit is set and cleared by software to select how the ADC interfa
    • [2:3]RES (def=0x0) // Data resolution These bits are written by software to select the resolution of the conversion. Note
    • [5:9]EXTSEL (def=0x0) // External trigger selection for regular group These bits select the external event used to trigger t
    • [10:11]EXTEN (def=0x0) // External trigger enable and polarity selection for regular channels These bits are set and cleared
    • [12]OVRMOD (def=0x0) // Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed.
    • [13]CONT (def=0x0) // Single / continuous conversion mode for regular conversions This bit is set and cleared by software
    • [14]AUTDLY (def=0x0) // Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed
    • [16]DISCEN (def=0x0) // Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable D
    • [17:19]DISCNUM (def=0x0) // Discontinuous mode channel count These bits are written by software to define the number of regular
    • [20]JDISCEN (def=0x0) // Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable d
    • [22]AWD1SGL (def=0x0) // Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by softwar
    • [23]AWD1EN (def=0x0) // Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The soft
    • [24]JAWD1EN (def=0x0) // Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The sof
    • [25]JAUTO (def=0x0) // Automatic injected group conversion This bit is set and cleared by software to enable/disable autom
    • [26:30]AWD1CH (def=0x0) // Analog watchdog 1 channel selection These bits are set and cleared by software. They select the inp
  • 0x42028010ADC_CFGR2// ADC configuration register 2

    • [0]ROVSE (def=0x0) // Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling.
    • [1]JOVSE (def=0x0) // Injected Oversampling Enable This bit is set and cleared by software to enable injected oversamplin
    • [5:8]OVSS (def=0x0) // Oversampling right shift This bit field is set and cleared by software to define the right shifting
    • [9]TROVS (def=0x0) // Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversamp
    • [10]ROVSM (def=0x0) // Regular Oversampling mode This bit is set and cleared by software to select the regular oversamplin
    • [13]BULB (def=0x0) // Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRI
    • [14]SWTRIG (def=0x0) // Software trigger bit for sampling time control trigger mode This bit is set and cleared by software
    • [15]SMPTRIG (def=0x0) // Sampling time control trigger mode This bit is set and cleared by software to enable the sampling t
    • [16:25]OSR (def=0x0) // Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2
    • [27]LFTRIG (def=0x0) // Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to writ
    • [28:31]LSHIFT (def=0x0) // Left shift factor This bitfield is set and cleared by software to define the left shifting applied
  • 0x42028014ADC_SMPR1// ADC sample time register 1

    • [0:2]SMP0 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [3:5]SMP1 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [6:8]SMP2 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [9:11]SMP3 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [12:14]SMP4 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [15:17]SMP5 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [18:20]SMP6 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [21:23]SMP7 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [24:26]SMP8 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [27:29]SMP9 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
  • 0x42028018ADC_SMPR2// ADC sample time register 2

    • [0:2]SMP10 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [3:5]SMP11 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [6:8]SMP12 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [9:11]SMP13 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [12:14]SMP14 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [15:17]SMP15 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [18:20]SMP16 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [21:23]SMP17 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [24:26]SMP18 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [27:29]SMP19 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
  • 0x4202801CADC_PCSEL// ADC channel preselection register

    • [0]PCSEL0 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [1]PCSEL1 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [2]PCSEL2 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [3]PCSEL3 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [4]PCSEL4 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [5]PCSEL5 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [6]PCSEL6 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [7]PCSEL7 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [8]PCSEL8 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [9]PCSEL9 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [10]PCSEL10 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [11]PCSEL11 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [12]PCSEL12 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [13]PCSEL13 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [14]PCSEL14 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [15]PCSEL15 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [16]PCSEL16 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [17]PCSEL17 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [18]PCSEL18 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [19]PCSEL19 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
  • 0x42028030ADC_SQR1// ADC regular sequence register 1

    • [0:3]L (def=0x0) // Regular channel sequence length These bits are written by software to define the total number of co
    • [6:10]SQ1 (def=0x0) // 1st conversion in regular sequence These bits are written by software with the channel number (0..1
    • [12:16]SQ2 (def=0x0) // 2nd conversion in regular sequence These bits are written by software with the channel number (0..1
    • [18:22]SQ3 (def=0x0) // 3rd conversion in regular sequence These bits are written by software with the channel number (0..1
    • [24:28]SQ4 (def=0x0) // 4th conversion in regular sequence These bits are written by software with the channel number (0..1
  • 0x42028034ADC_SQR2// ADC regular sequence register 2

    • [0:4]SQ5 (def=0x0) // 5th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [6:10]SQ6 (def=0x0) // 6th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [12:16]SQ7 (def=0x0) // 7th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [18:22]SQ8 (def=0x0) // 8th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [24:28]SQ9 (def=0x0) // 9th conversion in regular sequence These bits are written by software with the channel number (0..1
  • 0x42028038ADC_SQR3// ADC regular sequence register 3

    • [0:4]SQ10 (def=0x0) // 10th conversion in regular sequence These bits are written by software with the channel number (0..
    • [6:10]SQ11 (def=0x0) // 11th conversion in regular sequence These bits are written by software with the channel number (0..
    • [12:16]SQ12 (def=0x0) // 12th conversion in regular sequence These bits are written by software with the channel number (0..
    • [18:22]SQ13 (def=0x0) // 13th conversion in regular sequence These bits are written by software with the channel number (0..
    • [24:28]SQ14 (def=0x0) // 14th conversion in regular sequence These bits are written by software with the channel number (0..
  • 0x4202803CADC_SQR4// ADC regular sequence register 4

    • [0:4]SQ15 (def=0x0) // 15th conversion in regular sequence These bits are written by software with the channel number (0..
    • [6:10]SQ16 (def=0x0) // 16th conversion in regular sequence These bits are written by software with the channel number (0..
  • 0x42028040ADC_DR// ADC regular Data Register

    • [0:31]RDATA (def=0x0) // Regular data converted These bits are read-only. They contain the conversion result from the last c
  • 0x4202804CADC_JSQR// ADC injected sequence register

    • [0:1]JL (def=0x0) // Injected channel sequence length These bits are written by software to define the total number of c
    • [2:6]JEXTSEL (def=0x0) // External trigger selection for injected group These bits select the external event used to trigger
    • [7:8]JEXTEN (def=0x0) // External trigger enable and polarity selection for injected channels These bits are set and cleared
    • [9:13]JSQ1 (def=0x0) // 1st conversion in the injected sequence These bits are written by software with the channel number
    • [15:19]JSQ2 (def=0x0) // 2nd conversion in the injected sequence These bits are written by software with the channel number
    • [21:25]JSQ3 (def=0x0) // 3rd conversion in the injected sequence These bits are written by software with the channel number
    • [27:31]JSQ4 (def=0x0) // 4th conversion in the injected sequence These bits are written by software with the channel number
  • 0x42028060ADC_OFR1// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x42028064ADC_OFR2// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x42028068ADC_OFR3// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x4202806CADC_OFR4// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x42028070ADC_GCOMP// ADC gain compensation register

    • [0:13]GCOMPCOEFF (def=0x0) // Gain compensation coefficient These bits are set and cleared by software to program the gain compen
    • [31]GCOMP (def=0x0) // Gain compensation mode This bit is set and cleared by software to enable the gain compensation mode
  • 0x42028080ADC_JDR1// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x42028084ADC_JDR2// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x42028088ADC_JDR3// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x4202808CADC_JDR4// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x420280A0ADC_AWD2CR// ADC analog watchdog 2 configuration register

    • [0:19]AWD2CH (def=0x0) // Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and sel
  • 0x420280A4ADC_AWD3CR// ADC analog watchdog 3 configuration register

    • [0:19]AWD3CH (def=0x0) // Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and sel
  • 0x420280A8ADC_LTR1// ADC watchdog threshold register 1

    • [0:24]LTR1 (def=0x0) // Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold
  • 0x420280ACADC_HTR1// ADC watchdog threshold register 1

    • [0:24]HTR1 (def=0x1FFFFFF) // Analog watchdog 1 higher threshold These bits are written by software to define the higher threshol
    • [29:31]AWDFILT1 (def=0x0) // Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software
  • 0x420280B0ADC_LTR2// ADC watchdog lower threshold register 2

    • [0:24]LTR2 (def=0x0) // Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold
  • 0x420280B4ADC_HTR2// ADC watchdog higher threshold register 2

    • [0:24]HTR2 (def=0x1FFFFFF) // Analog watchdog 2 higher threshold These bits are written by software to define the higher threshol
  • 0x420280B8ADC_LTR3// ADC watchdog lower threshold register 3

    • [0:24]LTR3 (def=0x0) // Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold
  • 0x420280BCADC_HTR3// ADC watchdog higher threshold register 3

    • [0:24]HTR3 (def=0x1FFFFFF) // Analog watchdog 3 higher threshold These bits are written by software to define the higher threshol
  • 0x420280C0ADC_DIFSEL// ADC differential mode selection register

    • [0:19]DIFSEL (def=0x0) // Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow selec
  • 0x420280C4ADC_CALFACT// ADC user control register

    • [0:7]I_APB_ADDR (def=0x0) // Delayed write access address This bitfield contains the address that is being written during delaye
    • [8:15]I_APB_DATA (def=0x0) // Delayed write access data This bitfield contains the data that are being written during delayed wri
    • [16]VALIDITY (def=0x0) // Delayed write access status bit This bit indicates the communication status between the ADC digital
    • [24]LATCH_COEF (def=0x0) // Calibration factor latch enable bit This bit latches the calibration factor in the CALFACT[31:0] bi
    • [25]CAPTURE_COEF (def=0x0) // Calibration factor capture enable bit This bit enables the internal calibration factor capture.
  • 0x420280C8ADC_CALFACT2// ADC calibration factor register

    • [0:31]CALFACT (def=0x0) // Linearity or offset calibration factor These bits can be written either by hardware or by software.
  interrupts:
  • [37] ADC1 // ADC1 (16 bits) global interrupt
• 0x52028000SEC_ADC1//

  • 0x52028000ADC_ISR// ADC interrupt and status register

    • [0]ADRDY (def=0x0) // ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the
    • [1]EOSMP (def=0x0) // End of sampling flag This bit is set by hardware during the conversion of any channel (only for reg
    • [2]EOC (def=0x0) // End of conversion flag This bit is set by hardware at the end of each regular conversion of a chann
    • [3]EOS (def=0x0) // End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular
    • [4]OVR (def=0x0) // ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a
    • [5]JEOC (def=0x0) // Injected channel end of conversion flag This bit is set by hardware at the end of each injected con
    • [6]JEOS (def=0x0) // Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of
    • [7]AWD1 (def=0x0) // Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [8]AWD2 (def=0x0) // Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [9]AWD3 (def=0x0) // Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values pr
    • [12]LDORDY (def=0x0) // ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply
  • 0x52028004ADC_IER// ADC interrupt enable register

    • [0]ADRDYIE (def=0x0) // ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready
    • [1]EOSMPIE (def=0x0) // End of sampling flag interrupt enable for regular conversions This bit is set and cleared by softwa
    • [2]EOCIE (def=0x0) // End of regular conversion interrupt enable This bit is set and cleared by software to enable/disabl
    • [3]EOSIE (def=0x0) // End of regular sequence of conversions interrupt enable This bit is set and cleared by software to
    • [4]OVRIE (def=0x0) // Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun inte
    • [5]JEOCIE (def=0x0) // End of injected conversion interrupt enable This bit is set and cleared by software to enable/disab
    • [6]JEOSIE (def=0x0) // End of injected sequence of conversions interrupt enable This bit is set and cleared by software to
    • [7]AWD1IE (def=0x0) // Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the an
    • [8]AWD2IE (def=0x0) // Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the an
    • [9]AWD3IE (def=0x0) // Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the an
  • 0x52028008ADC_CR// ADC control register

    • [0]ADEN (def=0x0) // ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to o
    • [1]ADDIS (def=0x0) // ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into
    • [2]ADSTART (def=0x0) // ADC start of regular conversion This bit is set by software to start ADC conversion of regular chan
    • [3]JADSTART (def=0x0) // ADC start of injected conversion This bit is set by software to start ADC conversion of injected ch
    • [4]ADSTP (def=0x0) // ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing r
    • [5]JADSTP (def=0x0) // ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing
    • [16]ADCALLIN (def=0x0) // Linearity calibration This bit is set and cleared by software to enable the linearity calibration.
    • [24:27]CALINDEX (def=0x0) // Calibration factor This bitfield controls the calibration factor to be read or written. Calibration
    • [28]ADVREGEN (def=0x0) // ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Befo
    • [29]DEEPPWD (def=0x1) // Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mo
    • [31]ADCAL (def=0x0) // ADC calibration This bit is set by software to start the ADC calibration. It is cleared by hardware
  • 0x5202800CADC_CFGR1// ADC configuration register

    • [0:1]DMNGT (def=0x0) // Data management configuration This bit is set and cleared by software to select how the ADC interfa
    • [2:3]RES (def=0x0) // Data resolution These bits are written by software to select the resolution of the conversion. Note
    • [5:9]EXTSEL (def=0x0) // External trigger selection for regular group These bits select the external event used to trigger t
    • [10:11]EXTEN (def=0x0) // External trigger enable and polarity selection for regular channels These bits are set and cleared
    • [12]OVRMOD (def=0x0) // Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed.
    • [13]CONT (def=0x0) // Single / continuous conversion mode for regular conversions This bit is set and cleared by software
    • [14]AUTDLY (def=0x0) // Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed
    • [16]DISCEN (def=0x0) // Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable D
    • [17:19]DISCNUM (def=0x0) // Discontinuous mode channel count These bits are written by software to define the number of regular
    • [20]JDISCEN (def=0x0) // Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable d
    • [22]AWD1SGL (def=0x0) // Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by softwar
    • [23]AWD1EN (def=0x0) // Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The soft
    • [24]JAWD1EN (def=0x0) // Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The sof
    • [25]JAUTO (def=0x0) // Automatic injected group conversion This bit is set and cleared by software to enable/disable autom
    • [26:30]AWD1CH (def=0x0) // Analog watchdog 1 channel selection These bits are set and cleared by software. They select the inp
  • 0x52028010ADC_CFGR2// ADC configuration register 2

    • [0]ROVSE (def=0x0) // Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling.
    • [1]JOVSE (def=0x0) // Injected Oversampling Enable This bit is set and cleared by software to enable injected oversamplin
    • [5:8]OVSS (def=0x0) // Oversampling right shift This bit field is set and cleared by software to define the right shifting
    • [9]TROVS (def=0x0) // Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversamp
    • [10]ROVSM (def=0x0) // Regular Oversampling mode This bit is set and cleared by software to select the regular oversamplin
    • [13]BULB (def=0x0) // Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRI
    • [14]SWTRIG (def=0x0) // Software trigger bit for sampling time control trigger mode This bit is set and cleared by software
    • [15]SMPTRIG (def=0x0) // Sampling time control trigger mode This bit is set and cleared by software to enable the sampling t
    • [16:25]OSR (def=0x0) // Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2
    • [27]LFTRIG (def=0x0) // Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to writ
    • [28:31]LSHIFT (def=0x0) // Left shift factor This bitfield is set and cleared by software to define the left shifting applied
  • 0x52028014ADC_SMPR1// ADC sample time register 1

    • [0:2]SMP0 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [3:5]SMP1 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [6:8]SMP2 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [9:11]SMP3 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [12:14]SMP4 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [15:17]SMP5 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [18:20]SMP6 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [21:23]SMP7 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [24:26]SMP8 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [27:29]SMP9 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
  • 0x52028018ADC_SMPR2// ADC sample time register 2

    • [0:2]SMP10 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [3:5]SMP11 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [6:8]SMP12 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [9:11]SMP13 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [12:14]SMP14 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [15:17]SMP15 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [18:20]SMP16 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [21:23]SMP17 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [24:26]SMP18 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
    • [27:29]SMP19 (def=0x0) // Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sam
  • 0x5202801CADC_PCSEL// ADC channel preselection register

    • [0]PCSEL0 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [1]PCSEL1 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [2]PCSEL2 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [3]PCSEL3 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [4]PCSEL4 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [5]PCSEL5 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [6]PCSEL6 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [7]PCSEL7 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [8]PCSEL8 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [9]PCSEL9 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [10]PCSEL10 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [11]PCSEL11 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [12]PCSEL12 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [13]PCSEL13 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [14]PCSEL14 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [15]PCSEL15 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [16]PCSEL16 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [17]PCSEL17 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [18]PCSEL18 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
    • [19]PCSEL19 (def=0x0) // Channel i (VINP[i]) preselection These bits are written by software to preselect the input channel
  • 0x52028030ADC_SQR1// ADC regular sequence register 1

    • [0:3]L (def=0x0) // Regular channel sequence length These bits are written by software to define the total number of co
    • [6:10]SQ1 (def=0x0) // 1st conversion in regular sequence These bits are written by software with the channel number (0..1
    • [12:16]SQ2 (def=0x0) // 2nd conversion in regular sequence These bits are written by software with the channel number (0..1
    • [18:22]SQ3 (def=0x0) // 3rd conversion in regular sequence These bits are written by software with the channel number (0..1
    • [24:28]SQ4 (def=0x0) // 4th conversion in regular sequence These bits are written by software with the channel number (0..1
  • 0x52028034ADC_SQR2// ADC regular sequence register 2

    • [0:4]SQ5 (def=0x0) // 5th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [6:10]SQ6 (def=0x0) // 6th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [12:16]SQ7 (def=0x0) // 7th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [18:22]SQ8 (def=0x0) // 8th conversion in regular sequence These bits are written by software with the channel number (0..1
    • [24:28]SQ9 (def=0x0) // 9th conversion in regular sequence These bits are written by software with the channel number (0..1
  • 0x52028038ADC_SQR3// ADC regular sequence register 3

    • [0:4]SQ10 (def=0x0) // 10th conversion in regular sequence These bits are written by software with the channel number (0..
    • [6:10]SQ11 (def=0x0) // 11th conversion in regular sequence These bits are written by software with the channel number (0..
    • [12:16]SQ12 (def=0x0) // 12th conversion in regular sequence These bits are written by software with the channel number (0..
    • [18:22]SQ13 (def=0x0) // 13th conversion in regular sequence These bits are written by software with the channel number (0..
    • [24:28]SQ14 (def=0x0) // 14th conversion in regular sequence These bits are written by software with the channel number (0..
  • 0x5202803CADC_SQR4// ADC regular sequence register 4

    • [0:4]SQ15 (def=0x0) // 15th conversion in regular sequence These bits are written by software with the channel number (0..
    • [6:10]SQ16 (def=0x0) // 16th conversion in regular sequence These bits are written by software with the channel number (0..
  • 0x52028040ADC_DR// ADC regular Data Register

    • [0:31]RDATA (def=0x0) // Regular data converted These bits are read-only. They contain the conversion result from the last c
  • 0x5202804CADC_JSQR// ADC injected sequence register

    • [0:1]JL (def=0x0) // Injected channel sequence length These bits are written by software to define the total number of c
    • [2:6]JEXTSEL (def=0x0) // External trigger selection for injected group These bits select the external event used to trigger
    • [7:8]JEXTEN (def=0x0) // External trigger enable and polarity selection for injected channels These bits are set and cleared
    • [9:13]JSQ1 (def=0x0) // 1st conversion in the injected sequence These bits are written by software with the channel number
    • [15:19]JSQ2 (def=0x0) // 2nd conversion in the injected sequence These bits are written by software with the channel number
    • [21:25]JSQ3 (def=0x0) // 3rd conversion in the injected sequence These bits are written by software with the channel number
    • [27:31]JSQ4 (def=0x0) // 4th conversion in the injected sequence These bits are written by software with the channel number
  • 0x52028060ADC_OFR1// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x52028064ADC_OFR2// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x52028068ADC_OFR3// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x5202806CADC_OFR4// ADC offset register

    • [0:23]OFFSET (def=0x0) // Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by softwa
    • [24]POSOFF (def=0x0) // offset sign This bit is set and cleared by software to enable the positive offset. Note: The softwa
    • [25]USAT (def=0x0) // Unsigned saturation enable This bit is written by software to enable or disable the unsigned satura
    • [26]SSAT (def=0x0) // Signed saturation enable This bit is written by software to enable or disable the Signed saturation
    • [27:31]OFFSET_CH (def=0x0) // Channel selection for the data offset y These bits are written by software to define the channel to
  • 0x52028070ADC_GCOMP// ADC gain compensation register

    • [0:13]GCOMPCOEFF (def=0x0) // Gain compensation coefficient These bits are set and cleared by software to program the gain compen
    • [31]GCOMP (def=0x0) // Gain compensation mode This bit is set and cleared by software to enable the gain compensation mode
  • 0x52028080ADC_JDR1// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x52028084ADC_JDR2// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x52028088ADC_JDR3// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x5202808CADC_JDR4// ADC injected data register

    • [0:31]JDATA (def=0x0) // Injected data These bits are read-only. They contain the conversion result from injected channel y.
  • 0x520280A0ADC_AWD2CR// ADC analog watchdog 2 configuration register

    • [0:19]AWD2CH (def=0x0) // Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and sel
  • 0x520280A4ADC_AWD3CR// ADC analog watchdog 3 configuration register

    • [0:19]AWD3CH (def=0x0) // Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and sel
  • 0x520280A8ADC_LTR1// ADC watchdog threshold register 1

    • [0:24]LTR1 (def=0x0) // Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold
  • 0x520280ACADC_HTR1// ADC watchdog threshold register 1

    • [0:24]HTR1 (def=0x1FFFFFF) // Analog watchdog 1 higher threshold These bits are written by software to define the higher threshol
    • [29:31]AWDFILT1 (def=0x0) // Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software
  • 0x520280B0ADC_LTR2// ADC watchdog lower threshold register 2

    • [0:24]LTR2 (def=0x0) // Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold
  • 0x520280B4ADC_HTR2// ADC watchdog higher threshold register 2

    • [0:24]HTR2 (def=0x1FFFFFF) // Analog watchdog 2 higher threshold These bits are written by software to define the higher threshol
  • 0x520280B8ADC_LTR3// ADC watchdog lower threshold register 3

    • [0:24]LTR3 (def=0x0) // Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold
  • 0x520280BCADC_HTR3// ADC watchdog higher threshold register 3

    • [0:24]HTR3 (def=0x1FFFFFF) // Analog watchdog 3 higher threshold These bits are written by software to define the higher threshol
  • 0x520280C0ADC_DIFSEL// ADC differential mode selection register

    • [0:19]DIFSEL (def=0x0) // Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow selec
  • 0x520280C4ADC_CALFACT// ADC user control register

    • [0:7]I_APB_ADDR (def=0x0) // Delayed write access address This bitfield contains the address that is being written during delaye
    • [8:15]I_APB_DATA (def=0x0) // Delayed write access data This bitfield contains the data that are being written during delayed wri
    • [16]VALIDITY (def=0x0) // Delayed write access status bit This bit indicates the communication status between the ADC digital
    • [24]LATCH_COEF (def=0x0) // Calibration factor latch enable bit This bit latches the calibration factor in the CALFACT[31:0] bi
    • [25]CAPTURE_COEF (def=0x0) // Calibration factor capture enable bit This bit enables the internal calibration factor capture.
  • 0x520280C8ADC_CALFACT2// ADC calibration factor register

    • [0:31]CALFACT (def=0x0) // Linearity or offset calibration factor These bits can be written either by hardware or by software.
• 0x46021000ADC4// ADC4

  • 0x46021000ADC_ISR// ADC interrupt and status register

    • [12]LDORDY (def=0x0) // LDORDY
    • [11]EOCAL (def=0x0) // EOCAL
    • [9]AWD3 (def=0x0) // AWD3
    • [8]AWD2 (def=0x0) // AWD2
    • [7]AWD1 (def=0x0) // AWD1
    • [4]OVR (def=0x0) // OVR
    • [3]EOS (def=0x0) // EOS
    • [2]EOC (def=0x0) // EOC
    • [1]EOSMP (def=0x0) // EOSMP
    • [0]ADRDY (def=0x0) // ADRDY
  • 0x46021004ADC_IER// ADC interrupt enable register

    • [12]LDORDYIE (def=0x0) // LDORDYIE
    • [11]EOCALIE (def=0x0) // EOCALIE
    • [9]AWD3IE (def=0x0) // AWD3IE
    • [8]AWD2IE (def=0x0) // AWD2IE
    • [7]AWD1IE (def=0x0) // AWD1IE
    • [4]OVRIE (def=0x0) // OVRIE
    • [3]EOSIE (def=0x0) // EOSIE
    • [2]EOCIE (def=0x0) // EOCIE
    • [1]EOSMPIE (def=0x0) // EOSMPIE
    • [0]ADRDYIE (def=0x0) // ADRDYIE
  • 0x46021008ADC_CR// ADC control register

    • [31]ADCAL (def=0x0) // ADCAL
    • [28]ADVREGEN (def=0x0) // ADVREGEN
    • [4]ADSTP (def=0x0) // ADSTP
    • [2]ADSTART (def=0x0) // ADSTART
    • [1]ADDIS (def=0x0) // ADDIS
    • [0]ADEN (def=0x0) // ADEN
  • 0x4602100CADC_CFGR1// ADC configuration register

    • [26:30]AWD1CH (def=0x0) // AWD1CH
    • [23]AWD1EN (def=0x0) // AWD1EN
    • [22]AWD1SGL (def=0x0) // AWD1SGL
    • [21]CHSELRMOD (def=0x0) // CHSELRMOD
    • [16]DISCEN (def=0x0) // DISCEN
    • [14]WAIT (def=0x0) // WAIT
    • [13]CONT (def=0x0) // CONT
    • [12]OVRMOD (def=0x0) // OVRMOD
    • [10:11]EXTEN (def=0x0) // EXTEN
    • [6:8]EXTSEL (def=0x0) // EXTSEL
    • [5]ALIGN (def=0x0) // ALIGN
    • [4]SCANDIR (def=0x0) // SCANDIR
    • [2:3]RES (def=0x0) // RES
    • [1]DMACFG (def=0x0) // DMACFG
    • [0]DMAEN (def=0x0) // DMAEN
  • 0x46021010ADC_CFGR2// ADC configuration register 2

    • [29]LFTRIG (def=0x0) // LFTRIG
    • [9]TOVS (def=0x0) // TOVS
    • [5:8]OVSS (def=0x0) // OVSS
    • [2:4]OVSR (def=0x0) // OVSR
    • [0]OVSE (def=0x0) // OVSE
  • 0x46021014ADC_SMPR// ADC sample time register

    • [31]SMPSEL23 (def=0x0) // SMPSEL23
    • [30]SMPSEL22 (def=0x0) // SMPSEL22
    • [29]SMPSEL21 (def=0x0) // SMPSEL21
    • [28]SMPSEL20 (def=0x0) // SMPSEL20
    • [27]SMPSEL19 (def=0x0) // SMPSEL19
    • [26]SMPSEL18 (def=0x0) // SMPSEL18
    • [25]SMPSEL17 (def=0x0) // SMPSEL17
    • [24]SMPSEL16 (def=0x0) // SMPSEL16
    • [23]SMPSEL15 (def=0x0) // SMPSEL15
    • [22]SMPSEL14 (def=0x0) // SMPSEL14
    • [21]SMPSEL13 (def=0x0) // SMPSEL13
    • [20]SMPSEL12 (def=0x0) // SMPSEL12
    • [19]SMPSEL11 (def=0x0) // SMPSEL11
    • [18]SMPSEL10 (def=0x0) // SMPSEL10
    • [17]SMPSEL9 (def=0x0) // SMPSEL9
    • [16]SMPSEL8 (def=0x0) // SMPSEL8
    • [15]SMPSEL7 (def=0x0) // SMPSEL7
    • [14]SMPSEL6 (def=0x0) // SMPSEL6
    • [13]SMPSEL5 (def=0x0) // SMPSEL5
    • [12]SMPSEL4 (def=0x0) // SMPSEL4
    • [11]SMPSEL3 (def=0x0) // SMPSEL3
    • [10]SMPSEL2 (def=0x0) // SMPSEL2
    • [9]SMPSEL1 (def=0x0) // SMPSEL1
    • [8]SMPSEL0 (def=0x0) // SMPSEL0
    • [4:6]SMP2 (def=0x0) // SMP2
    • [0:2]SMP1 (def=0x0) // SMP1
  • 0x46021020ADC_AWD1TR// ADC watchdog threshold register

    • [16:27]HT1 (def=0xFFF) // HT1
    • [0:11]LT1 (def=0x0) // LT1
  • 0x46021024ADC_AWD2TR// ADC watchdog threshold register

    • [16:27]HT2 (def=0xFFF) // HT2
    • [0:11]LT2 (def=0x0) // LT2
  • 0x46021028ADC_CHSELRMOD0// ADC channel selection register [alternate]

    • [0:23]CHSEL (def=0x0) // CHSEL
  • 0x46021028ADC_CHSELRMOD1// ADC channel selection register [alternate]

    • [28:31]SQ8 (def=0x0) // SQ8
    • [24:27]SQ7 (def=0x0) // SQ7
    • [20:23]SQ6 (def=0x0) // SQ6
    • [16:19]SQ5 (def=0x0) // SQ5
    • [12:15]SQ4 (def=0x0) // SQ4
    • [8:11]SQ3 (def=0x0) // SQ3
    • [4:7]SQ2 (def=0x0) // SQ2
    • [0:3]SQ1 (def=0x0) // SQ1
  • 0x4602102CADC_AWD3TR// ADC watchdog threshold register

    • [16:27]HT3 (def=0xFFF) // HT3
    • [0:11]LT3 (def=0x0) // LT3
  • 0x46021040ADC_DR// ADC data register

    • [0:15]DATA (def=0x0) // DATA
  • 0x46021044ADC_PWR// ADC data register

    • [3]VREFSECSMP (def=0x0) // VREFSECSMP
    • [2]VREFPROT (def=0x0) // VREFPROT
    • [1]DPD (def=0x0) // DPD
    • [0]AUTOFF (def=0x0) // AUTOFF
  • 0x460210A0ADC_AWD2CR// ADC Analog Watchdog 2 Configuration register

    • [23]AWD2CH23 (def=0x0) // AWD2CH23
    • [22]AWD2CH22 (def=0x0) // AWD2CH22
    • [21]AWD2CH21 (def=0x0) // AWD2CH21
    • [20]AWD2CH20 (def=0x0) // AWD2CH20
    • [19]AWD2CH19 (def=0x0) // AWD2CH19
    • [18]AWD2CH18 (def=0x0) // AWD2CH18
    • [17]AWD2CH17 (def=0x0) // AWD2CH17
    • [16]AWD2CH16 (def=0x0) // AWD2CH16
    • [15]AWD2CH15 (def=0x0) // AWD2CH15
    • [14]AWD2CH14 (def=0x0) // AWD2CH14
    • [13]AWD2CH13 (def=0x0) // AWD2CH13
    • [12]AWD2CH12 (def=0x0) // AWD2CH12
    • [11]AWD2CH11 (def=0x0) // AWD2CH11
    • [10]AWD2CH10 (def=0x0) // AWD2CH10
    • [9]AWD2CH9 (def=0x0) // AWD2CH9
    • [8]AWD2CH8 (def=0x0) // AWD2CH8
    • [7]AWD2CH7 (def=0x0) // AWD2CH7
    • [6]AWD2CH6 (def=0x0) // AWD2CH6
    • [5]AWD2CH5 (def=0x0) // AWD2CH5
    • [4]AWD2CH4 (def=0x0) // AWD2CH4
    • [3]AWD2CH3 (def=0x0) // AWD2CH3
    • [2]AWD2CH2 (def=0x0) // AWD2CH2
    • [1]AWD2CH1 (def=0x0) // AWD2CH1
    • [0]AWD2CH0 (def=0x0) // AWD2CH0
  • 0x460210A4ADC_AWD3CR// ADC Analog Watchdog 3 Configuration register

    • [23]AWD3CH23 (def=0x0) // AWD3CH23
    • [22]AWD3CH22 (def=0x0) // AWD3CH22
    • [21]AWD3CH21 (def=0x0) // AWD3CH21
    • [20]AWD3CH20 (def=0x0) // AWD3CH20
    • [19]AWD3CH19 (def=0x0) // AWD3CH19
    • [18]AWD3CH18 (def=0x0) // AWD3CH18
    • [17]AWD3CH17 (def=0x0) // AWD3CH17
    • [16]AWD3CH16 (def=0x0) // AWD3CH16
    • [15]AWD3CH15 (def=0x0) // AWD3CH15
    • [14]AWD3CH14 (def=0x0) // AWD3CH14
    • [13]AWD3CH13 (def=0x0) // AWD3CH13
    • [12]AWD3CH12 (def=0x0) // AWD3CH12
    • [11]AWD3CH11 (def=0x0) // AWD3CH11
    • [10]AWD3CH10 (def=0x0) // AWD3CH10
    • [9]AWD3CH9 (def=0x0) // AWD3CH9
    • [8]AWD3CH8 (def=0x0) // AWD3CH8
    • [7]AWD3CH7 (def=0x0) // AWD3CH7
    • [6]AWD3CH6 (def=0x0) // AWD3CH6
    • [5]AWD3CH5 (def=0x0) // AWD3CH5
    • [4]AWD3CH4 (def=0x0) // AWD3CH4
    • [3]AWD3CH3 (def=0x0) // AWD3CH3
    • [2]AWD3CH2 (def=0x0) // AWD3CH2
    • [1]AWD3CH1 (def=0x0) // AWD3CH1
    • [0]AWD3CH0 (def=0x0) // AWD3CH0
  • 0x460210C4ADC_CALFACT// ADC Calibration factor

    • [0:6]CALFACT (def=0x0) // CALFACT
  • 0x460210D0ADC_OR// ADC option register

    • [0]CHN21SEL (def=0x0) // CHN21SEL
  • 0x46021308ADC_CCR// ADC common configuration register

    • [24]VBATEN (def=0x0) // VBATEN
    • [23]VSENSESEL (def=0x0) // VSENSESEL
    • [22]VREFEN (def=0x0) // VREFEN
    • [18:21]PRESC (def=0x0) // PRESC
  interrupts:
  • [113] ADC4 // ADC4 (12 bits) global interrupt
• 0x56021000SEC_ADC4//

  • 0x56021000ADC_ISR// ADC interrupt and status register

    • [12]LDORDY (def=0x0) // LDORDY
    • [11]EOCAL (def=0x0) // EOCAL
    • [9]AWD3 (def=0x0) // AWD3
    • [8]AWD2 (def=0x0) // AWD2
    • [7]AWD1 (def=0x0) // AWD1
    • [4]OVR (def=0x0) // OVR
    • [3]EOS (def=0x0) // EOS
    • [2]EOC (def=0x0) // EOC
    • [1]EOSMP (def=0x0) // EOSMP
    • [0]ADRDY (def=0x0) // ADRDY
  • 0x56021004ADC_IER// ADC interrupt enable register

    • [12]LDORDYIE (def=0x0) // LDORDYIE
    • [11]EOCALIE (def=0x0) // EOCALIE
    • [9]AWD3IE (def=0x0) // AWD3IE
    • [8]AWD2IE (def=0x0) // AWD2IE
    • [7]AWD1IE (def=0x0) // AWD1IE
    • [4]OVRIE (def=0x0) // OVRIE
    • [3]EOSIE (def=0x0) // EOSIE
    • [2]EOCIE (def=0x0) // EOCIE
    • [1]EOSMPIE (def=0x0) // EOSMPIE
    • [0]ADRDYIE (def=0x0) // ADRDYIE
  • 0x56021008ADC_CR// ADC control register

    • [31]ADCAL (def=0x0) // ADCAL
    • [28]ADVREGEN (def=0x0) // ADVREGEN
    • [4]ADSTP (def=0x0) // ADSTP
    • [2]ADSTART (def=0x0) // ADSTART
    • [1]ADDIS (def=0x0) // ADDIS
    • [0]ADEN (def=0x0) // ADEN
  • 0x5602100CADC_CFGR1// ADC configuration register

    • [26:30]AWD1CH (def=0x0) // AWD1CH
    • [23]AWD1EN (def=0x0) // AWD1EN
    • [22]AWD1SGL (def=0x0) // AWD1SGL
    • [21]CHSELRMOD (def=0x0) // CHSELRMOD
    • [16]DISCEN (def=0x0) // DISCEN
    • [14]WAIT (def=0x0) // WAIT
    • [13]CONT (def=0x0) // CONT
    • [12]OVRMOD (def=0x0) // OVRMOD
    • [10:11]EXTEN (def=0x0) // EXTEN
    • [6:8]EXTSEL (def=0x0) // EXTSEL
    • [5]ALIGN (def=0x0) // ALIGN
    • [4]SCANDIR (def=0x0) // SCANDIR
    • [2:3]RES (def=0x0) // RES
    • [1]DMACFG (def=0x0) // DMACFG
    • [0]DMAEN (def=0x0) // DMAEN
  • 0x56021010ADC_CFGR2// ADC configuration register 2

    • [29]LFTRIG (def=0x0) // LFTRIG
    • [9]TOVS (def=0x0) // TOVS
    • [5:8]OVSS (def=0x0) // OVSS
    • [2:4]OVSR (def=0x0) // OVSR
    • [0]OVSE (def=0x0) // OVSE
  • 0x56021014ADC_SMPR// ADC sample time register

    • [31]SMPSEL23 (def=0x0) // SMPSEL23
    • [30]SMPSEL22 (def=0x0) // SMPSEL22
    • [29]SMPSEL21 (def=0x0) // SMPSEL21
    • [28]SMPSEL20 (def=0x0) // SMPSEL20
    • [27]SMPSEL19 (def=0x0) // SMPSEL19
    • [26]SMPSEL18 (def=0x0) // SMPSEL18
    • [25]SMPSEL17 (def=0x0) // SMPSEL17
    • [24]SMPSEL16 (def=0x0) // SMPSEL16
    • [23]SMPSEL15 (def=0x0) // SMPSEL15
    • [22]SMPSEL14 (def=0x0) // SMPSEL14
    • [21]SMPSEL13 (def=0x0) // SMPSEL13
    • [20]SMPSEL12 (def=0x0) // SMPSEL12
    • [19]SMPSEL11 (def=0x0) // SMPSEL11
    • [18]SMPSEL10 (def=0x0) // SMPSEL10
    • [17]SMPSEL9 (def=0x0) // SMPSEL9
    • [16]SMPSEL8 (def=0x0) // SMPSEL8
    • [15]SMPSEL7 (def=0x0) // SMPSEL7
    • [14]SMPSEL6 (def=0x0) // SMPSEL6
    • [13]SMPSEL5 (def=0x0) // SMPSEL5
    • [12]SMPSEL4 (def=0x0) // SMPSEL4
    • [11]SMPSEL3 (def=0x0) // SMPSEL3
    • [10]SMPSEL2 (def=0x0) // SMPSEL2
    • [9]SMPSEL1 (def=0x0) // SMPSEL1
    • [8]SMPSEL0 (def=0x0) // SMPSEL0
    • [4:6]SMP2 (def=0x0) // SMP2
    • [0:2]SMP1 (def=0x0) // SMP1
  • 0x56021020ADC_AWD1TR// ADC watchdog threshold register

    • [16:27]HT1 (def=0xFFF) // HT1
    • [0:11]LT1 (def=0x0) // LT1
  • 0x56021024ADC_AWD2TR// ADC watchdog threshold register

    • [16:27]HT2 (def=0xFFF) // HT2
    • [0:11]LT2 (def=0x0) // LT2
  • 0x56021028ADC_CHSELRMOD0// ADC channel selection register [alternate]

    • [0:23]CHSEL (def=0x0) // CHSEL
  • 0x56021028ADC_CHSELRMOD1// ADC channel selection register [alternate]

    • [28:31]SQ8 (def=0x0) // SQ8
    • [24:27]SQ7 (def=0x0) // SQ7
    • [20:23]SQ6 (def=0x0) // SQ6
    • [16:19]SQ5 (def=0x0) // SQ5
    • [12:15]SQ4 (def=0x0) // SQ4
    • [8:11]SQ3 (def=0x0) // SQ3
    • [4:7]SQ2 (def=0x0) // SQ2
    • [0:3]SQ1 (def=0x0) // SQ1
  • 0x5602102CADC_AWD3TR// ADC watchdog threshold register

    • [16:27]HT3 (def=0xFFF) // HT3
    • [0:11]LT3 (def=0x0) // LT3
  • 0x56021040ADC_DR// ADC data register

    • [0:15]DATA (def=0x0) // DATA
  • 0x56021044ADC_PWR// ADC data register

    • [3]VREFSECSMP (def=0x0) // VREFSECSMP
    • [2]VREFPROT (def=0x0) // VREFPROT
    • [1]DPD (def=0x0) // DPD
    • [0]AUTOFF (def=0x0) // AUTOFF
  • 0x560210A0ADC_AWD2CR// ADC Analog Watchdog 2 Configuration register

    • [23]AWD2CH23 (def=0x0) // AWD2CH23
    • [22]AWD2CH22 (def=0x0) // AWD2CH22
    • [21]AWD2CH21 (def=0x0) // AWD2CH21
    • [20]AWD2CH20 (def=0x0) // AWD2CH20
    • [19]AWD2CH19 (def=0x0) // AWD2CH19
    • [18]AWD2CH18 (def=0x0) // AWD2CH18
    • [17]AWD2CH17 (def=0x0) // AWD2CH17
    • [16]AWD2CH16 (def=0x0) // AWD2CH16
    • [15]AWD2CH15 (def=0x0) // AWD2CH15
    • [14]AWD2CH14 (def=0x0) // AWD2CH14
    • [13]AWD2CH13 (def=0x0) // AWD2CH13
    • [12]AWD2CH12 (def=0x0) // AWD2CH12
    • [11]AWD2CH11 (def=0x0) // AWD2CH11
    • [10]AWD2CH10 (def=0x0) // AWD2CH10
    • [9]AWD2CH9 (def=0x0) // AWD2CH9
    • [8]AWD2CH8 (def=0x0) // AWD2CH8
    • [7]AWD2CH7 (def=0x0) // AWD2CH7
    • [6]AWD2CH6 (def=0x0) // AWD2CH6
    • [5]AWD2CH5 (def=0x0) // AWD2CH5
    • [4]AWD2CH4 (def=0x0) // AWD2CH4
    • [3]AWD2CH3 (def=0x0) // AWD2CH3
    • [2]AWD2CH2 (def=0x0) // AWD2CH2
    • [1]AWD2CH1 (def=0x0) // AWD2CH1
    • [0]AWD2CH0 (def=0x0) // AWD2CH0
  • 0x560210A4ADC_AWD3CR// ADC Analog Watchdog 3 Configuration register

    • [23]AWD3CH23 (def=0x0) // AWD3CH23
    • [22]AWD3CH22 (def=0x0) // AWD3CH22
    • [21]AWD3CH21 (def=0x0) // AWD3CH21
    • [20]AWD3CH20 (def=0x0) // AWD3CH20
    • [19]AWD3CH19 (def=0x0) // AWD3CH19
    • [18]AWD3CH18 (def=0x0) // AWD3CH18
    • [17]AWD3CH17 (def=0x0) // AWD3CH17
    • [16]AWD3CH16 (def=0x0) // AWD3CH16
    • [15]AWD3CH15 (def=0x0) // AWD3CH15
    • [14]AWD3CH14 (def=0x0) // AWD3CH14
    • [13]AWD3CH13 (def=0x0) // AWD3CH13
    • [12]AWD3CH12 (def=0x0) // AWD3CH12
    • [11]AWD3CH11 (def=0x0) // AWD3CH11
    • [10]AWD3CH10 (def=0x0) // AWD3CH10
    • [9]AWD3CH9 (def=0x0) // AWD3CH9
    • [8]AWD3CH8 (def=0x0) // AWD3CH8
    • [7]AWD3CH7 (def=0x0) // AWD3CH7
    • [6]AWD3CH6 (def=0x0) // AWD3CH6
    • [5]AWD3CH5 (def=0x0) // AWD3CH5
    • [4]AWD3CH4 (def=0x0) // AWD3CH4
    • [3]AWD3CH3 (def=0x0) // AWD3CH3
    • [2]AWD3CH2 (def=0x0) // AWD3CH2
    • [1]AWD3CH1 (def=0x0) // AWD3CH1
    • [0]AWD3CH0 (def=0x0) // AWD3CH0
  • 0x560210C4ADC_CALFACT// ADC Calibration factor

    • [0:6]CALFACT (def=0x0) // CALFACT
  • 0x560210D0ADC_OR// ADC option register

    • [0]CHN21SEL (def=0x0) // CHN21SEL
  • 0x56021308ADC_CCR// ADC common configuration register

    • [24]VBATEN (def=0x0) // VBATEN
    • [23]VSENSESEL (def=0x0) // VSENSESEL
    • [22]VREFEN (def=0x0) // VREFEN
    • [18:21]PRESC (def=0x0) // PRESC
• 0x42028300ADC12// ADC common registers

  • 0x42028308ADC12_CCR// ADC_CCR system control register

    • [18:21]PRESC (def=0x0) // ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock.
    • [22]VREFEN (def=0x0) // VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note:
    • [23]VSENSESEL (def=0x0) // Temperature sensor voltage selection This bit is set and cleared by software to control the tempera
    • [24]VBATEN (def=0x0) // VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software
• 0x52028300SEC_ADC12//

  • 0x52028308ADC12_CCR// ADC_CCR system control register

    • [18:21]PRESC (def=0x0) // ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock.
    • [22]VREFEN (def=0x0) // VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note:
    • [23]VSENSESEL (def=0x0) // Temperature sensor voltage selection This bit is set and cleared by software to control the tempera
    • [24]VBATEN (def=0x0) // VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software
• 0x420D0400FMC// FMC

  • 0x420D0400BCR1// SRAM/NOR-Flash chip-select control register for bank 1

    • [0]MBKEN (def=0x1) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x2) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x420D0408BCR2// SRAM/NOR-Flash chip-select control register for bank 2

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x420D0410BCR3// SRAM/NOR-Flash chip-select control register for bank 3

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x420D0418BCR4// SRAM/NOR-Flash chip-select control register for bank 4

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x420D0404BTR1// SRAM/NOR-Flash chip-select timing register for bank 1

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D040CBTR2// SRAM/NOR-Flash chip-select timing register for bank 2

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D0414BTR3// SRAM/NOR-Flash chip-select timing register for bank 3

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D041CBTR4// SRAM/NOR-Flash chip-select timing register for bank 4

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D0504BWTR1// SRAM/NOR-Flash write timing registers 1

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D050CBWTR2// SRAM/NOR-Flash write timing registers 2

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D0514BWTR3// SRAM/NOR-Flash write timing registers 3

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D051CBWTR4// SRAM/NOR-Flash write timing registers 4

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x420D0420PCSCNTR// PSRAM chip select counter register

    • [0:15]CSCOUNT (def=0x0) // Chip select counter
    • [16]CNTB1EN (def=0x0) // Counter Bank 1 enable
    • [17]CNTB2EN (def=0x0) // Counter Bank 2 enable
    • [18]CNTB3EN (def=0x0) // Counter Bank 3 enable
    • [19]CNTB4EN (def=0x0) // Counter Bank 4 enable
  • 0x420D0480PCR// NAND Flash control registers

    • [1]PWAITEN (def=0x0) // Wait feature enable bit
    • [2]PBKEN (def=0x0) // NAND Flash memory bank enable bit
    • [3]PTYP (def=0x1) // Memory type
    • [4:5]PWID (def=0x1) // Data bus width
    • [6]ECCEN (def=0x0) // ECC computation logic enable bit
    • [9:12]TCLR (def=0x0) // CLE to RE delay
    • [13:15]TAR (def=0x0) // ALE to RE delay
    • [17:19]ECCPS (def=0x0) // ECC page size
  • 0x420D0484SR// status and interrupt register

    • [0]IRS (def=0x0) // Interrupt rising edge status The flag is set by hardware and reset by software. Note:
    • [1]ILS (def=0x0) // Interrupt high-level status The flag is set by hardware and reset by software.
    • [2]IFS (def=0x0) // Interrupt falling edge status The flag is set by hardware and reset by software. Note
    • [3]IREN (def=0x0) // Interrupt rising edge detection enable bit
    • [4]ILEN (def=0x0) // Interrupt high-level detection enable bit
    • [5]IFEN (def=0x0) // Interrupt falling edge detection enable bit
    • [6]FEMPT (def=0x1) // FIFO empty. Read-only bit that provides the status of the FIFO
  • 0x420D0488PMEM// Common memory space timing register

    • [0:7]MEMSET (def=0xFC) // Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles
    • [8:15]MEMWAIT (def=0xFC) // Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock
    • [16:23]MEMHOLD (def=0xFC) // Common memory hold time These bits define the number of KCK_FMC clock cycles for writ
    • [24:31]MEMHIZ (def=0xFC) // Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycl
  • 0x420D048CPATT// The FMC_PATT read/write register contains the timing information for NAND Flash memory ba

    • [0:7]ATTSET (def=0xFC) // Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles
    • [8:15]ATTWAIT (def=0xFC) // Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clo
    • [16:23]ATTHOLD (def=0xFC) // Attribute memory hold time These bits define the number of KCK_FMC clock cycles durin
    • [24:31]ATTHIZ (def=0xFC) // Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cyc
  • 0x420D0494ECCR// This register contain the current error correction code value computed by the ECC computa

    • [0:31]ECC (def=0x0) // ECC result This field contains the value computed by the ECC computation logic. Table
  interrupts:
  • [75] FMC // FMC global interrupt
• 0x520D0400SEC_FMC//

  • 0x520D0400BCR1// SRAM/NOR-Flash chip-select control register for bank 1

    • [0]MBKEN (def=0x1) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x2) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x520D0408BCR2// SRAM/NOR-Flash chip-select control register for bank 2

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x520D0410BCR3// SRAM/NOR-Flash chip-select control register for bank 3

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x520D0418BCR4// SRAM/NOR-Flash chip-select control register for bank 4

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [20]CCLKEN (def=0x0) // Continuous clock enable
    • [21]WFDIS (def=0x0) // Write FIFO disable
    • [22:23]NBLSET (def=0x0) // Byte lane (NBL) setup
    • [31]FMCEN (def=0x0) // FMC controller enable
  • 0x520D0404BTR1// SRAM/NOR-Flash chip-select timing register for bank 1

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D040CBTR2// SRAM/NOR-Flash chip-select timing register for bank 2

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D0414BTR3// SRAM/NOR-Flash chip-select timing register for bank 3

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D041CBTR4// SRAM/NOR-Flash chip-select timing register for bank 4

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D0504BWTR1// SRAM/NOR-Flash write timing registers 1

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D050CBWTR2// SRAM/NOR-Flash write timing registers 2

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D0514BWTR3// SRAM/NOR-Flash write timing registers 3

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D051CBWTR4// SRAM/NOR-Flash write timing registers 4

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
    • [30:31]DATAHLD (def=0x0) // Data hold phase duration
  • 0x520D0420PCSCNTR// PSRAM chip select counter register

    • [0:15]CSCOUNT (def=0x0) // Chip select counter
    • [16]CNTB1EN (def=0x0) // Counter Bank 1 enable
    • [17]CNTB2EN (def=0x0) // Counter Bank 2 enable
    • [18]CNTB3EN (def=0x0) // Counter Bank 3 enable
    • [19]CNTB4EN (def=0x0) // Counter Bank 4 enable
  • 0x520D0480PCR// NAND Flash control registers

    • [1]PWAITEN (def=0x0) // Wait feature enable bit
    • [2]PBKEN (def=0x0) // NAND Flash memory bank enable bit
    • [3]PTYP (def=0x1) // Memory type
    • [4:5]PWID (def=0x1) // Data bus width
    • [6]ECCEN (def=0x0) // ECC computation logic enable bit
    • [9:12]TCLR (def=0x0) // CLE to RE delay
    • [13:15]TAR (def=0x0) // ALE to RE delay
    • [17:19]ECCPS (def=0x0) // ECC page size
  • 0x520D0484SR// status and interrupt register

    • [0]IRS (def=0x0) // Interrupt rising edge status The flag is set by hardware and reset by software. Note:
    • [1]ILS (def=0x0) // Interrupt high-level status The flag is set by hardware and reset by software.
    • [2]IFS (def=0x0) // Interrupt falling edge status The flag is set by hardware and reset by software. Note
    • [3]IREN (def=0x0) // Interrupt rising edge detection enable bit
    • [4]ILEN (def=0x0) // Interrupt high-level detection enable bit
    • [5]IFEN (def=0x0) // Interrupt falling edge detection enable bit
    • [6]FEMPT (def=0x1) // FIFO empty. Read-only bit that provides the status of the FIFO
  • 0x520D0488PMEM// Common memory space timing register

    • [0:7]MEMSET (def=0xFC) // Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles
    • [8:15]MEMWAIT (def=0xFC) // Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock
    • [16:23]MEMHOLD (def=0xFC) // Common memory hold time These bits define the number of KCK_FMC clock cycles for writ
    • [24:31]MEMHIZ (def=0xFC) // Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycl
  • 0x520D048CPATT// The FMC_PATT read/write register contains the timing information for NAND Flash memory ba

    • [0:7]ATTSET (def=0xFC) // Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles
    • [8:15]ATTWAIT (def=0xFC) // Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clo
    • [16:23]ATTHOLD (def=0xFC) // Attribute memory hold time These bits define the number of KCK_FMC clock cycles durin
    • [24:31]ATTHIZ (def=0xFC) // Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cyc
  • 0x520D0494ECCR// This register contain the current error correction code value computed by the ECC computa

    • [0:31]ECC (def=0x0) // ECC result This field contains the value computed by the ECC computation logic. Table
• 0x420C0800RNG// Random number generator

  • 0x420C0800CR// control register

    • [31]CONFIGLOCK (def=0x0) // RNG Config Lock
    • [30]CONDRST (def=0x0) // Conditioning soft reset
    • [20:25]RNG_CONFIG1 (def=0x0) // RNG configuration 1
    • [16:19]CLKDIV (def=0x0) // Clock divider factor
    • [13:15]RNG_CONFIG2 (def=0x0) // RNG configuration 2
    • [12]NISTC (def=0x0) // Non NIST compliant
    • [8:11]RNG_CONFIG3 (def=0x0) // RNG configuration 3
    • [7]ARDIS (def=0x0) // Auto reset disable
    • [5]CED (def=0x0) // Clock error detection
    • [3]IE (def=0x0) // Interrupt Enable
    • [2]RNGEN (def=0x0) // True random number generator enable
  • 0x420C0804SR// status register

    • [6]SEIS (def=0x0) // Seed error interrupt status
    • [5]CEIS (def=0x0) // Clock error interrupt status
    • [2]SECS (def=0x0) // Seed error current status
    • [1]CECS (def=0x0) // Clock error current status
    • [0]DRDY (def=0x0) // Data ready
  • 0x420C0808DR// data register

    • [0:31]RNDATA (def=0x0) // Random data
  • 0x420C0810HTCR// health test control register

    • [0:31]HTCFG (def=0x6274) // health test configuration
  interrupts:
  • [94] RNG // RNG global interrupt
• 0x520C0800SEC_RNG//

  • 0x520C0800CR// control register

    • [31]CONFIGLOCK (def=0x0) // RNG Config Lock
    • [30]CONDRST (def=0x0) // Conditioning soft reset
    • [20:25]RNG_CONFIG1 (def=0x0) // RNG configuration 1
    • [16:19]CLKDIV (def=0x0) // Clock divider factor
    • [13:15]RNG_CONFIG2 (def=0x0) // RNG configuration 2
    • [12]NISTC (def=0x0) // Non NIST compliant
    • [8:11]RNG_CONFIG3 (def=0x0) // RNG configuration 3
    • [7]ARDIS (def=0x0) // Auto reset disable
    • [5]CED (def=0x0) // Clock error detection
    • [3]IE (def=0x0) // Interrupt Enable
    • [2]RNGEN (def=0x0) // True random number generator enable
  • 0x520C0804SR// status register

    • [6]SEIS (def=0x0) // Seed error interrupt status
    • [5]CEIS (def=0x0) // Clock error interrupt status
    • [2]SECS (def=0x0) // Seed error current status
    • [1]CECS (def=0x0) // Clock error current status
    • [0]DRDY (def=0x0) // Data ready
  • 0x520C0808DR// data register

    • [0:31]RNDATA (def=0x0) // Random data
  • 0x520C0810HTCR// health test control register

    • [0:31]HTCFG (def=0x6274) // health test configuration
• 0x40021400FMAC// Filter Math Accelerator

  • 0x40021400X1BUFCFG// FMAC X1 Buffer Configuration register

    • [0:7]X1_BASE (def=0x0) // Base address of X1 buffer
    • [8:15]X1_BUF_SIZE (def=0x0) // Allocated size of X1 buffer in 16-bit words
    • [24:25]FULL_WM (def=0x0) // Watermark for buffer full flag
  • 0x40021404X2BUFCFG// FMAC X2 Buffer Configuration register

    • [0:7]X2_BASE (def=0x0) // Base address of X2 buffer
    • [8:15]X2_BUF_SIZE (def=0x0) // Size of X2 buffer in 16-bit words
  • 0x40021408YBUFCFG// FMAC Y Buffer Configuration register

    • [0:7]Y_BASE (def=0x0) // Base address of Y buffer
    • [8:15]Y_BUF_SIZE (def=0x0) // Size of Y buffer in 16-bit words
    • [24:25]EMPTY_WM (def=0x0) // Watermark for buffer empty flag
  • 0x4002140CPARAM// FMAC Parameter register

    • [31]START (def=0x0) // Enable execution
    • [24:30]FUNC (def=0x0) // Function
    • [16:23]R (def=0x0) // Input parameter R
    • [8:15]Q (def=0x0) // Input parameter Q
    • [0:7]P (def=0x0) // Input parameter P
  • 0x40021410CR// FMAC Control register

    • [16]RESET (def=0x0) // Reset FMAC unit
    • [15]CLIPEN (def=0x0) // Enable clipping
    • [9]DMAWEN (def=0x0) // Enable DMA write channel requests
    • [8]DMAREN (def=0x0) // Enable DMA read channel requests
    • [4]SATIEN (def=0x0) // Enable saturation error interrupts
    • [3]UNFLIEN (def=0x0) // Enable underflow error interrupts
    • [2]OVFLIEN (def=0x0) // Enable overflow error interrupts
    • [1]WIEN (def=0x0) // Enable write interrupt
    • [0]RIEN (def=0x0) // Enable read interrupt
  • 0x40021414SR// FMAC Status register

    • [0]YEMPTY (def=0x1) // Y buffer empty flag
    • [1]X1FULL (def=0x0) // X1 buffer full flag
    • [8]OVFL (def=0x0) // Overflow error flag
    • [9]UNFL (def=0x0) // Underflow error flag
    • [10]SAT (def=0x0) // Saturation error flag
  • 0x40021418WDATA// FMAC Write Data register

    • [0:15]WDATA (def=0x0) // Write data
  • 0x4002141CRDATA// FMAC Read Data register

    • [0:15]RDATA (def=0x0) // Read data
  interrupts:
  • [124] FMAC // FMAC interrupt
• 0x50021400SEC_FMAC//

  • 0x50021400X1BUFCFG// FMAC X1 Buffer Configuration register

    • [0:7]X1_BASE (def=0x0) // Base address of X1 buffer
    • [8:15]X1_BUF_SIZE (def=0x0) // Allocated size of X1 buffer in 16-bit words
    • [24:25]FULL_WM (def=0x0) // Watermark for buffer full flag
  • 0x50021404X2BUFCFG// FMAC X2 Buffer Configuration register

    • [0:7]X2_BASE (def=0x0) // Base address of X2 buffer
    • [8:15]X2_BUF_SIZE (def=0x0) // Size of X2 buffer in 16-bit words
  • 0x50021408YBUFCFG// FMAC Y Buffer Configuration register

    • [0:7]Y_BASE (def=0x0) // Base address of Y buffer
    • [8:15]Y_BUF_SIZE (def=0x0) // Size of Y buffer in 16-bit words
    • [24:25]EMPTY_WM (def=0x0) // Watermark for buffer empty flag
  • 0x5002140CPARAM// FMAC Parameter register

    • [31]START (def=0x0) // Enable execution
    • [24:30]FUNC (def=0x0) // Function
    • [16:23]R (def=0x0) // Input parameter R
    • [8:15]Q (def=0x0) // Input parameter Q
    • [0:7]P (def=0x0) // Input parameter P
  • 0x50021410CR// FMAC Control register

    • [16]RESET (def=0x0) // Reset FMAC unit
    • [15]CLIPEN (def=0x0) // Enable clipping
    • [9]DMAWEN (def=0x0) // Enable DMA write channel requests
    • [8]DMAREN (def=0x0) // Enable DMA read channel requests
    • [4]SATIEN (def=0x0) // Enable saturation error interrupts
    • [3]UNFLIEN (def=0x0) // Enable underflow error interrupts
    • [2]OVFLIEN (def=0x0) // Enable overflow error interrupts
    • [1]WIEN (def=0x0) // Enable write interrupt
    • [0]RIEN (def=0x0) // Enable read interrupt
  • 0x50021414SR// FMAC Status register

    • [0]YEMPTY (def=0x1) // Y buffer empty flag
    • [1]X1FULL (def=0x0) // X1 buffer full flag
    • [8]OVFL (def=0x0) // Overflow error flag
    • [9]UNFL (def=0x0) // Underflow error flag
    • [10]SAT (def=0x0) // Saturation error flag
  • 0x50021418WDATA// FMAC Write Data register

    • [0:15]WDATA (def=0x0) // Write data
  • 0x5002141CRDATA// FMAC Read Data register

    • [0:15]RDATA (def=0x0) // Read data
• 0x40021000CORDIC// CORDIC Co-processor

  • 0x40021000CSR// CORDIC Control Status register

    • [0:3]FUNC (def=0x0) // Function
    • [4:7]PRECISION (def=0x5) // Precision required (number of iterations)
    • [8:10]SCALE (def=0x0) // Scaling factor
    • [16]IEN (def=0x0) // Enable interrupt
    • [17]DMAREN (def=0x0) // Enable DMA read channel
    • [18]DMAWEN (def=0x0) // Enable DMA write channel
    • [19]NRES (def=0x0) // Number of results in the CORDIC_RDATA register
    • [20]NARGS (def=0x0) // Number of arguments expected by the CORDIC_WDATA register
    • [21]RESSIZE (def=0x0) // Width of output data
    • [22]ARGSIZE (def=0x0) // Width of input data
    • [31]RRDY (def=0x0) // Result ready flag
  • 0x40021004WDATA// FMAC Write Data register

    • [0:31]ARG (def=0x0) // Function input arguments
  • 0x40021008RDATA// FMAC Read Data register

    • [0:31]RES (def=0x0) // Function result
  interrupts:
  • [123] Cordic // Cordic interrupt
• 0x50021000SEC_CORDIC//

  • 0x50021000CSR// CORDIC Control Status register

    • [0:3]FUNC (def=0x0) // Function
    • [4:7]PRECISION (def=0x5) // Precision required (number of iterations)
    • [8:10]SCALE (def=0x0) // Scaling factor
    • [16]IEN (def=0x0) // Enable interrupt
    • [17]DMAREN (def=0x0) // Enable DMA read channel
    • [18]DMAWEN (def=0x0) // Enable DMA write channel
    • [19]NRES (def=0x0) // Number of results in the CORDIC_RDATA register
    • [20]NARGS (def=0x0) // Number of arguments expected by the CORDIC_WDATA register
    • [21]RESSIZE (def=0x0) // Width of output data
    • [22]ARGSIZE (def=0x0) // Width of input data
    • [31]RRDY (def=0x0) // Result ready flag
  • 0x50021004WDATA// FMAC Write Data register

    • [0:31]ARG (def=0x0) // Function input arguments
  • 0x50021008RDATA// FMAC Read Data register

    • [0:31]RES (def=0x0) // Function result
• 0x46021800DAC1// Digital-to-analog converter

  • 0x46021800DAC_CR// DAC control register

    • [0]EN1 (def=0x0) // DAC channel1 enable
    • [1]TEN1 (def=0x0) // DAC channel1 trigger enable
    • [2:5]TSEL1 (def=0x0) // DAC channel1 trigger selection
    • [6:7]WAVE1 (def=0x0) // DAC channel1 noise/triangle wave generation enable
    • [8:11]MAMP1 (def=0x0) // DAC channel1 mask/amplitude selector
    • [12]DMAEN1 (def=0x0) // DAC channel1 DMA enable
    • [13]DMAUDRIE1 (def=0x0) // DAC channel1 DMA Underrun Interrupt enable
    • [14]CEN1 (def=0x0) // DAC channel1 calibration enable
    • [16]EN2 (def=0x0) // DAC channel2 enable
    • [17]TEN2 (def=0x0) // DAC channel2 trigger enable
    • [18:21]TSEL2 (def=0x0) // DAC channel2 trigger selection
    • [22:23]WAVE2 (def=0x0) // DAC channel2 noise/triangle wave generation enable
    • [24:27]MAMP2 (def=0x0) // DAC channel2 mask/amplitude selector
    • [28]DMAEN2 (def=0x0) // DAC channel2 DMA enable
    • [29]DMAUDRIE2 (def=0x0) // DAC channel2 DMA underrun interrupt enable
    • [30]CEN2 (def=0x0) // DAC channel2 calibration enable
  • 0x46021804DAC_SWTRGR// DAC software trigger register

    • [0]SWTRIG1 (def=0x0) // DAC channel1 software trigger
    • [1]SWTRIG2 (def=0x0) // DAC channel2 software trigger
  • 0x46021808DAC_DHR12R1// DAC channel1 12-bit right-aligned data holding register

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC1DHRB (def=0x0) // DAC channel1 12-bit right-aligned data B
  • 0x4602180CDAC_DHR12L1// DAC channel1 12-bit left aligned data holding register

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC1DHRB (def=0x0) // DAC channel1 12-bit left-aligned data B
  • 0x46021810DAC_DHR8R1// DAC channel1 8-bit right aligned data holding register

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC1DHRB (def=0x0) // DAC channel1 8-bit right-aligned Sdata
  • 0x46021814DAC_DHR12R2// DAC channel2 12-bit right aligned data holding register

    • [0:11]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
    • [16:27]DACC2DHRB (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x46021818DAC_DHR12L2// DAC channel2 12-bit left aligned data holding register

    • [4:15]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
    • [20:31]DACC2DHRB (def=0x0) // DAC channel2 12-bit left-aligned data B
  • 0x4602181CDAC_DHR8R2// DAC channel2 8-bit right-aligned data holding register

    • [0:7]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
    • [8:15]DACC2DHRB (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x46021820DAC_DHR12RD// Dual DAC 12-bit right-aligned data holding register

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x46021824DAC_DHR12LD// DUAL DAC 12-bit left aligned data holding register

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
  • 0x46021828DAC_DHR8RD// DUAL DAC 8-bit right aligned data holding register

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x4602182CDAC_DOR1// DAC channel1 data output register

    • [0:11]DACC1DOR (def=0x0) // DAC channel1 data output
    • [16:27]DACC1DORB (def=0x0) // DAC channel1 data output
  • 0x46021830DAC_DOR2// DAC channel2 data output register

    • [0:11]DACC2DOR (def=0x0) // DAC channel2 data output
    • [16:27]DACC2DORB (def=0x0) // DAC channel2 data output
  • 0x46021834DAC_SR// DAC status register

    • [11]DAC1RDY (def=0x0) // DAC channel1 ready status bit
    • [12]DORSTAT1 (def=0x0) // DAC channel1 output register status bit
    • [13]DMAUDR1 (def=0x0) // DAC channel1 DMA underrun flag
    • [14]CAL_FLAG1 (def=0x0) // DAC Channel 1 calibration offset status
    • [15]BWST1 (def=0x0) // DAC Channel 1 busy writing sample time flag
    • [27]DAC2RDY (def=0x0) // DAC channel 2 ready status bit
    • [28]DORSTAT2 (def=0x0) // DAC channel 2 output register status bit
    • [29]DMAUDR2 (def=0x0) // DAC channel2 DMA underrun flag
    • [30]CAL_FLAG2 (def=0x0) // DAC Channel 2 calibration offset status
    • [31]BWST2 (def=0x0) // DAC Channel 2 busy writing sample time flag
  • 0x46021838DAC_CCR// DAC calibration control register

    • [0:4]OTRIM1 (def=0x0) // DAC Channel 1 offset trimming value
    • [16:20]OTRIM2 (def=0x0) // DAC Channel 2 offset trimming value
  • 0x4602183CDAC_MCR// DAC mode control register

    • [0:2]MODE1 (def=0x0) // DAC Channel 1 mode
    • [8]DMADOUBLE1 (def=0x0) // DAC Channel1 DMA double data mode
    • [9]SINFORMAT1 (def=0x0) // Enable signed format for DAC channel1
    • [14:15]HFSEL (def=0x0) // High frequency interface mode selection
    • [16:18]MODE2 (def=0x0) // DAC Channel 2 mode
    • [24]DMADOUBLE2 (def=0x0) // DAC Channel2 DMA double data mode
    • [25]SINFORMAT2 (def=0x0) // Enable signed format for DAC channel2
  • 0x46021840DAC_SHSR1// DAC Sample and Hold sample time register 1

    • [0:9]TSAMPLE1 (def=0x0) // DAC Channel 1 sample Time (only valid in sample & hold mode)
  • 0x46021844DAC_SHSR2// DAC channel2 sample and hold sample time register

    • [0:9]TSAMPLE2 (def=0x0) // DAC Channel 2 sample Time (only valid in sample and hold mode)
  • 0x46021848DAC_SHHR// DAC Sample and Hold hold time register

    • [0:9]THOLD1 (def=0x1) // DAC Channel 1 hold Time (only valid in sample and hold mode)
    • [16:25]THOLD2 (def=0x1) // DAC Channel 2 hold time (only valid in sample and hold mode)
  • 0x4602184CDAC_SHRR// DAC Sample and Hold refresh time register

    • [0:7]TREFRESH1 (def=0x1) // DAC Channel 1 refresh Time (only valid in sample and hold mode)
    • [16:23]TREFRESH2 (def=0x1) // DAC Channel 2 refresh Time (only valid in sample and hold mode)
  • 0x46021854DAC_AUTOCR// Autonomous mode control register

    • [22]AUTOMODE (def=0x0) // DAC Autonomous mode
  interrupts:
  • [38] DAC1 // DAC1 global interrupt
• 0x56021800SEC_DAC1//

  • 0x56021800DAC_CR// DAC control register

    • [0]EN1 (def=0x0) // DAC channel1 enable
    • [1]TEN1 (def=0x0) // DAC channel1 trigger enable
    • [2:5]TSEL1 (def=0x0) // DAC channel1 trigger selection
    • [6:7]WAVE1 (def=0x0) // DAC channel1 noise/triangle wave generation enable
    • [8:11]MAMP1 (def=0x0) // DAC channel1 mask/amplitude selector
    • [12]DMAEN1 (def=0x0) // DAC channel1 DMA enable
    • [13]DMAUDRIE1 (def=0x0) // DAC channel1 DMA Underrun Interrupt enable
    • [14]CEN1 (def=0x0) // DAC channel1 calibration enable
    • [16]EN2 (def=0x0) // DAC channel2 enable
    • [17]TEN2 (def=0x0) // DAC channel2 trigger enable
    • [18:21]TSEL2 (def=0x0) // DAC channel2 trigger selection
    • [22:23]WAVE2 (def=0x0) // DAC channel2 noise/triangle wave generation enable
    • [24:27]MAMP2 (def=0x0) // DAC channel2 mask/amplitude selector
    • [28]DMAEN2 (def=0x0) // DAC channel2 DMA enable
    • [29]DMAUDRIE2 (def=0x0) // DAC channel2 DMA underrun interrupt enable
    • [30]CEN2 (def=0x0) // DAC channel2 calibration enable
  • 0x56021804DAC_SWTRGR// DAC software trigger register

    • [0]SWTRIG1 (def=0x0) // DAC channel1 software trigger
    • [1]SWTRIG2 (def=0x0) // DAC channel2 software trigger
  • 0x56021808DAC_DHR12R1// DAC channel1 12-bit right-aligned data holding register

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC1DHRB (def=0x0) // DAC channel1 12-bit right-aligned data B
  • 0x5602180CDAC_DHR12L1// DAC channel1 12-bit left aligned data holding register

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC1DHRB (def=0x0) // DAC channel1 12-bit left-aligned data B
  • 0x56021810DAC_DHR8R1// DAC channel1 8-bit right aligned data holding register

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC1DHRB (def=0x0) // DAC channel1 8-bit right-aligned Sdata
  • 0x56021814DAC_DHR12R2// DAC channel2 12-bit right aligned data holding register

    • [0:11]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
    • [16:27]DACC2DHRB (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x56021818DAC_DHR12L2// DAC channel2 12-bit left aligned data holding register

    • [4:15]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
    • [20:31]DACC2DHRB (def=0x0) // DAC channel2 12-bit left-aligned data B
  • 0x5602181CDAC_DHR8R2// DAC channel2 8-bit right-aligned data holding register

    • [0:7]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
    • [8:15]DACC2DHRB (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x56021820DAC_DHR12RD// Dual DAC 12-bit right-aligned data holding register

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x56021824DAC_DHR12LD// DUAL DAC 12-bit left aligned data holding register

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
  • 0x56021828DAC_DHR8RD// DUAL DAC 8-bit right aligned data holding register

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x5602182CDAC_DOR1// DAC channel1 data output register

    • [0:11]DACC1DOR (def=0x0) // DAC channel1 data output
    • [16:27]DACC1DORB (def=0x0) // DAC channel1 data output
  • 0x56021830DAC_DOR2// DAC channel2 data output register

    • [0:11]DACC2DOR (def=0x0) // DAC channel2 data output
    • [16:27]DACC2DORB (def=0x0) // DAC channel2 data output
  • 0x56021834DAC_SR// DAC status register

    • [11]DAC1RDY (def=0x0) // DAC channel1 ready status bit
    • [12]DORSTAT1 (def=0x0) // DAC channel1 output register status bit
    • [13]DMAUDR1 (def=0x0) // DAC channel1 DMA underrun flag
    • [14]CAL_FLAG1 (def=0x0) // DAC Channel 1 calibration offset status
    • [15]BWST1 (def=0x0) // DAC Channel 1 busy writing sample time flag
    • [27]DAC2RDY (def=0x0) // DAC channel 2 ready status bit
    • [28]DORSTAT2 (def=0x0) // DAC channel 2 output register status bit
    • [29]DMAUDR2 (def=0x0) // DAC channel2 DMA underrun flag
    • [30]CAL_FLAG2 (def=0x0) // DAC Channel 2 calibration offset status
    • [31]BWST2 (def=0x0) // DAC Channel 2 busy writing sample time flag
  • 0x56021838DAC_CCR// DAC calibration control register

    • [0:4]OTRIM1 (def=0x0) // DAC Channel 1 offset trimming value
    • [16:20]OTRIM2 (def=0x0) // DAC Channel 2 offset trimming value
  • 0x5602183CDAC_MCR// DAC mode control register

    • [0:2]MODE1 (def=0x0) // DAC Channel 1 mode
    • [8]DMADOUBLE1 (def=0x0) // DAC Channel1 DMA double data mode
    • [9]SINFORMAT1 (def=0x0) // Enable signed format for DAC channel1
    • [14:15]HFSEL (def=0x0) // High frequency interface mode selection
    • [16:18]MODE2 (def=0x0) // DAC Channel 2 mode
    • [24]DMADOUBLE2 (def=0x0) // DAC Channel2 DMA double data mode
    • [25]SINFORMAT2 (def=0x0) // Enable signed format for DAC channel2
  • 0x56021840DAC_SHSR1// DAC Sample and Hold sample time register 1

    • [0:9]TSAMPLE1 (def=0x0) // DAC Channel 1 sample Time (only valid in sample & hold mode)
  • 0x56021844DAC_SHSR2// DAC channel2 sample and hold sample time register

    • [0:9]TSAMPLE2 (def=0x0) // DAC Channel 2 sample Time (only valid in sample and hold mode)
  • 0x56021848DAC_SHHR// DAC Sample and Hold hold time register

    • [0:9]THOLD1 (def=0x1) // DAC Channel 1 hold Time (only valid in sample and hold mode)
    • [16:25]THOLD2 (def=0x1) // DAC Channel 2 hold time (only valid in sample and hold mode)
  • 0x5602184CDAC_SHRR// DAC Sample and Hold refresh time register

    • [0:7]TREFRESH1 (def=0x1) // DAC Channel 1 refresh Time (only valid in sample and hold mode)
    • [16:23]TREFRESH2 (def=0x1) // DAC Channel 2 refresh Time (only valid in sample and hold mode)
  • 0x56021854DAC_AUTOCR// Autonomous mode control register

    • [22]AUTOMODE (def=0x0) // DAC Autonomous mode
• 0x420C8000SDMMC1// Secure digital input/output MultiMediaCard interface

  • 0x420C8000POWER// power control register

    • [0:1]PWRCTRL (def=0x0) // SDMMC state control bits
    • [2]VSWITCH (def=0x0) // Voltage switch sequence start
    • [3]VSWITCHEN (def=0x0) // Voltage switch procedure enable
    • [4]DIRPOL (def=0x0) // Data and command direction signals polarity selection
  • 0x420C8004CLKCR// clock control register

    • [20:21]SELCLKRX (def=0x0) // Receive clock selection
    • [19]BUSSPEED (def=0x0) // Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
    • [18]DDR (def=0x0) // Data rate signaling selection
    • [17]HWFC_EN (def=0x0) // HW Flow Control enable
    • [16]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14:15]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [12]PWRSAV (def=0x0) // Power saving configuration bit
    • [0:9]CLKDIV (def=0x0) // Clock divide factor
  • 0x420C8008ARGR// argument register

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x420C800CCMDR// command register

    • [16]CMDSUSPEND (def=0x0) // The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
    • [15]BOOTEN (def=0x0) // Enable boot mode procedure
    • [14]BOOTMODE (def=0x0) // Select the boot mode procedure to be used
    • [13]DTHOLD (def=0x0) // Hold new data block transmission and reception in the DPSM
    • [12]CPSMEN (def=0x0) // Command path state machine (CPSM) Enable bit
    • [11]WAITPEND (def=0x0) // CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
    • [10]WAITINT (def=0x0) // CPSM waits for interrupt request
    • [8:9]WAITRESP (def=0x0) // Wait for response bits
    • [7]CMDSTOP (def=0x0) // The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
    • [6]CMDTRANS (def=0x0) // The CPSM treats the command as a data transfer command, stops the interrupt period, and signals Dat
    • [0:5]CMDINDEX (def=0x0) // Command index
  • 0x420C8010RESPCMDR// command response register

    • [0:5]RESPCMD (def=0x0) // Response command index
  • 0x420C8014RESP1// response 1 register

    • [0:31]CARDSTATUS1 (def=0x0) // CARDSTATUS1
  • 0x420C8018RESP2// response 2 register

    • [0:31]CARDSTATUS2 (def=0x0) // CARDSTATUS2
  • 0x420C801CRESP3// response 3 register

    • [0:31]CARDSTATUS3 (def=0x0) // CARDSTATUS3
  • 0x420C8020RESP4// response 4 register

    • [0:31]CARDSTATUS4 (def=0x0) // CARDSTATUS4
  • 0x420C8024DTIMER// data timer register

    • [0:31]DATATIME (def=0x0) // Data and R1b busy timeout period
  • 0x420C8028DLENR// data length register

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x420C802CDCTRL// data control register

    • [13]FIFORST (def=0x0) // FIFO reset, will flush any remaining data
    • [12]BOOTACKEN (def=0x0) // Enable the reception of the boot acknowledgment
    • [11]SDIOEN (def=0x0) // SD I/O enable functions
    • [10]RWMOD (def=0x0) // Read wait mode
    • [9]RWSTOP (def=0x0) // Read wait stop
    • [8]RWSTART (def=0x0) // Read wait start
    • [4:7]DBLOCKSIZE (def=0x0) // Data block size
    • [2:3]DTMODE (def=0x0) // Data transfer mode selection
    • [1]DTDIR (def=0x0) // Data transfer direction selection
    • [0]DTEN (def=0x0) // DTEN
  • 0x420C8030DCNTR// data counter register

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x420C8034STAR// status register

    • [28]IDMABTC (def=0x0) // IDMA buffer transfer complete
    • [27]IDMATE (def=0x0) // IDMA transfer error
    • [26]CKSTOP (def=0x0) // SDMMC_CK stopped in Voltage switch procedure
    • [25]VSWEND (def=0x0) // Voltage switch critical timing section completion
    • [24]ACKTIMEOUT (def=0x0) // Boot acknowledgment timeout
    • [23]ACKFAIL (def=0x0) // Boot acknowledgment received (boot acknowledgment check fail)
    • [22]SDIOIT (def=0x0) // SDIO interrupt received
    • [21]BUSYD0END (def=0x0) // end of SDMMC_D0 Busy following a CMD response detected
    • [20]BUSYD0 (def=0x0) // Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SD
    • [19]RXFIFOE (def=0x0) // Receive FIFO empty
    • [18]TXFIFOE (def=0x0) // Transmit FIFO empty
    • [17]RXFIFOF (def=0x0) // Receive FIFO full
    • [16]TXFIFOF (def=0x0) // Transmit FIFO full
    • [15]RXFIFOHF (def=0x0) // Receive FIFO half full
    • [14]TXFIFOHE (def=0x0) // Transmit FIFO half empty
    • [13]CPSMACT (def=0x0) // Command path state machine active, i.e. not in Idle state
    • [12]DPSMACT (def=0x0) // Data path state machine active, i.e. not in Idle state
    • [11]DABORT (def=0x0) // Data transfer aborted by CMD12
    • [10]DBCKEND (def=0x0) // Data block sent/received
    • [9]DHOLD (def=0x0) // Data transfer Hold
    • [8]DATAEND (def=0x0) // Data transfer ended correctly
    • [7]CMDSENT (def=0x0) // Command sent (no response required)
    • [6]CMDREND (def=0x0) // Command response received (CRC check passed, or no CRC)
    • [5]RXOVERR (def=0x0) // Received FIFO overrun error (masked by hardware when IDMA is enabled)
    • [4]TXUNDERR (def=0x0) // Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
    • [3]DTIMEOUT (def=0x0) // Data timeout
    • [2]CTIMEOUT (def=0x0) // Command response timeout
    • [1]DCRCFAIL (def=0x0) // Data block sent/received (CRC check failed)
    • [0]CCRCFAIL (def=0x0) // Command response received (CRC check failed)
  • 0x420C8038ICR// interrupt clear register

    • [28]IDMABTCC (def=0x0) // IDMA buffer transfer complete clear bit
    • [27]IDMATEC (def=0x0) // IDMA transfer error clear bit
    • [26]CKSTOPC (def=0x0) // CKSTOP flag clear bit
    • [25]VSWENDC (def=0x0) // VSWEND flag clear bit
    • [24]ACKTIMEOUTC (def=0x0) // ACKTIMEOUT flag clear bit
    • [23]ACKFAILC (def=0x0) // ACKFAIL flag clear bit
    • [22]SDIOITC (def=0x0) // SDIOIT flag clear bit
    • [21]BUSYD0ENDC (def=0x0) // BUSYD0END flag clear bit
    • [11]DABORTC (def=0x0) // DABORT flag clear bit
    • [10]DBCKENDC (def=0x0) // DBCKEND flag clear bit
    • [9]DHOLDC (def=0x0) // DHOLD flag clear bit
    • [8]DATAENDC (def=0x0) // DATAEND flag clear bit
    • [7]CMDSENTC (def=0x0) // CMDSENT flag clear bit
    • [6]CMDRENDC (def=0x0) // CMDREND flag clear bit
    • [5]RXOVERRC (def=0x0) // RXOVERR flag clear bit
    • [4]TXUNDERRC (def=0x0) // TXUNDERR flag clear bit
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUT flag clear bit
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUT flag clear bit
    • [1]DCRCFAILC (def=0x0) // DCRCFAIL flag clear bit
    • [0]CCRCFAILC (def=0x0) // CCRCFAIL flag clear bit
  • 0x420C803CMASKR// mask register

    • [28]IDMABTCIE (def=0x0) // IDMA buffer transfer complete interrupt enable
    • [26]CKSTOPIE (def=0x0) // Voltage Switch clock stopped interrupt enable
    • [25]VSWENDIE (def=0x0) // Voltage switch critical timing section completion interrupt enable
    • [24]ACKTIMEOUTIE (def=0x0) // Acknowledgment timeout interrupt enable
    • [23]ACKFAILIE (def=0x0) // Acknowledgment Fail interrupt enable
    • [22]SDIOITIE (def=0x0) // SDIO mode interrupt received interrupt enable
    • [21]BUSYD0ENDIE (def=0x0) // BUSYD0END interrupt enable
    • [18]TXFIFOEIE (def=0x0) // Tx FIFO empty interrupt enable
    • [17]RXFIFOFIE (def=0x0) // Rx FIFO full interrupt enable
    • [15]RXFIFOHFIE (def=0x0) // Rx FIFO half full interrupt enable
    • [14]TXFIFOHEIE (def=0x0) // Tx FIFO half empty interrupt enable
    • [11]DABORTIE (def=0x0) // Data transfer aborted interrupt enable
    • [10]DBCKENDIE (def=0x0) // Data block end interrupt enable
    • [9]DHOLDIE (def=0x0) // Data hold interrupt enable
    • [8]DATAENDIE (def=0x0) // Data end interrupt enable
    • [7]CMDSENTIE (def=0x0) // Command sent interrupt enable
    • [6]CMDRENDIE (def=0x0) // Command response received interrupt enable
    • [5]RXOVERRIE (def=0x0) // Rx FIFO overrun error interrupt enable
    • [4]TXUNDERRIE (def=0x0) // Tx FIFO underrun error interrupt enable
    • [3]DTIMEOUTIE (def=0x0) // Data timeout interrupt enable
    • [2]CTIMEOUTIE (def=0x0) // Command timeout interrupt enable
    • [1]DCRCFAILIE (def=0x0) // Data CRC fail interrupt enable
    • [0]CCRCFAILIE (def=0x0) // Command CRC fail interrupt enable
  • 0x420C8040ACKTIMER// acknowledgment timer register

    • [0:24]ACKTIME (def=0x0) // Boot acknowledgment timeout period
  • 0x420C8080FIFOR0// data FIFO register 0

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8084FIFOR1// data FIFO register 1

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8088FIFOR2// data FIFO register 2

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C808CFIFOR3// data FIFO register 3

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8090FIFOR4// data FIFO register 4

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8094FIFOR5// data FIFO register 5

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8098FIFOR6// data FIFO register 6

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C809CFIFOR7// data FIFO register 7

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80A0FIFOR8// data FIFO register 8

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80A4FIFOR9// data FIFO register 9

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80A8FIFOR10// data FIFO register 10

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80ACFIFOR11// data FIFO register 11

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80B0FIFOR12// data FIFO register 12

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80B4FIFOR13// data FIFO register 13

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80B8FIFOR14// data FIFO register 14

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C80BCFIFOR15// data FIFO register 15

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8050SDMMC_IDMACTRLR// DMA control register

    • [0]IDMAEN (def=0x0) // IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
    • [1]IDMABMODE (def=0x0) // Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)
  • 0x420C8054SDMMC_IDMABSIZER// buffer size register

    • [5:16]IDMABNDT (def=0x0) // Number of bytes per buffer
  • 0x420C8058SDMMC_IDMABASER// buffer base address register

    • [0:31]IDMABASE (def=0x0) // Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only
  • 0x420C8064SDMMC_IDMALAR// linked list address register

    • [31]ULA (def=0x0) // Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select li
    • [30]ULS (def=0x0) // Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMOD
    • [29]ABR (def=0x0) // Acknowledge linked list buffer ready
    • [2:15]IDMALA (def=0x0) // Acknowledge linked list buffer ready
  • 0x420C8068SDMMC_IDMABAR// linked list memory base register

    • [2:31]IDMABA (def=0x0) // Word aligned Linked list memory base address
  interrupts:
  • [78] SDMMC1 // SDMMC1 global interrupt
• 0x520C8000SEC_SDMMC1//

  • 0x520C8000POWER// power control register

    • [0:1]PWRCTRL (def=0x0) // SDMMC state control bits
    • [2]VSWITCH (def=0x0) // Voltage switch sequence start
    • [3]VSWITCHEN (def=0x0) // Voltage switch procedure enable
    • [4]DIRPOL (def=0x0) // Data and command direction signals polarity selection
  • 0x520C8004CLKCR// clock control register

    • [20:21]SELCLKRX (def=0x0) // Receive clock selection
    • [19]BUSSPEED (def=0x0) // Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
    • [18]DDR (def=0x0) // Data rate signaling selection
    • [17]HWFC_EN (def=0x0) // HW Flow Control enable
    • [16]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14:15]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [12]PWRSAV (def=0x0) // Power saving configuration bit
    • [0:9]CLKDIV (def=0x0) // Clock divide factor
  • 0x520C8008ARGR// argument register

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x520C800CCMDR// command register

    • [16]CMDSUSPEND (def=0x0) // The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
    • [15]BOOTEN (def=0x0) // Enable boot mode procedure
    • [14]BOOTMODE (def=0x0) // Select the boot mode procedure to be used
    • [13]DTHOLD (def=0x0) // Hold new data block transmission and reception in the DPSM
    • [12]CPSMEN (def=0x0) // Command path state machine (CPSM) Enable bit
    • [11]WAITPEND (def=0x0) // CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
    • [10]WAITINT (def=0x0) // CPSM waits for interrupt request
    • [8:9]WAITRESP (def=0x0) // Wait for response bits
    • [7]CMDSTOP (def=0x0) // The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
    • [6]CMDTRANS (def=0x0) // The CPSM treats the command as a data transfer command, stops the interrupt period, and signals Dat
    • [0:5]CMDINDEX (def=0x0) // Command index
  • 0x520C8010RESPCMDR// command response register

    • [0:5]RESPCMD (def=0x0) // Response command index
  • 0x520C8014RESP1// response 1 register

    • [0:31]CARDSTATUS1 (def=0x0) // CARDSTATUS1
  • 0x520C8018RESP2// response 2 register

    • [0:31]CARDSTATUS2 (def=0x0) // CARDSTATUS2
  • 0x520C801CRESP3// response 3 register

    • [0:31]CARDSTATUS3 (def=0x0) // CARDSTATUS3
  • 0x520C8020RESP4// response 4 register

    • [0:31]CARDSTATUS4 (def=0x0) // CARDSTATUS4
  • 0x520C8024DTIMER// data timer register

    • [0:31]DATATIME (def=0x0) // Data and R1b busy timeout period
  • 0x520C8028DLENR// data length register

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x520C802CDCTRL// data control register

    • [13]FIFORST (def=0x0) // FIFO reset, will flush any remaining data
    • [12]BOOTACKEN (def=0x0) // Enable the reception of the boot acknowledgment
    • [11]SDIOEN (def=0x0) // SD I/O enable functions
    • [10]RWMOD (def=0x0) // Read wait mode
    • [9]RWSTOP (def=0x0) // Read wait stop
    • [8]RWSTART (def=0x0) // Read wait start
    • [4:7]DBLOCKSIZE (def=0x0) // Data block size
    • [2:3]DTMODE (def=0x0) // Data transfer mode selection
    • [1]DTDIR (def=0x0) // Data transfer direction selection
    • [0]DTEN (def=0x0) // DTEN
  • 0x520C8030DCNTR// data counter register

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x520C8034STAR// status register

    • [28]IDMABTC (def=0x0) // IDMA buffer transfer complete
    • [27]IDMATE (def=0x0) // IDMA transfer error
    • [26]CKSTOP (def=0x0) // SDMMC_CK stopped in Voltage switch procedure
    • [25]VSWEND (def=0x0) // Voltage switch critical timing section completion
    • [24]ACKTIMEOUT (def=0x0) // Boot acknowledgment timeout
    • [23]ACKFAIL (def=0x0) // Boot acknowledgment received (boot acknowledgment check fail)
    • [22]SDIOIT (def=0x0) // SDIO interrupt received
    • [21]BUSYD0END (def=0x0) // end of SDMMC_D0 Busy following a CMD response detected
    • [20]BUSYD0 (def=0x0) // Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SD
    • [19]RXFIFOE (def=0x0) // Receive FIFO empty
    • [18]TXFIFOE (def=0x0) // Transmit FIFO empty
    • [17]RXFIFOF (def=0x0) // Receive FIFO full
    • [16]TXFIFOF (def=0x0) // Transmit FIFO full
    • [15]RXFIFOHF (def=0x0) // Receive FIFO half full
    • [14]TXFIFOHE (def=0x0) // Transmit FIFO half empty
    • [13]CPSMACT (def=0x0) // Command path state machine active, i.e. not in Idle state
    • [12]DPSMACT (def=0x0) // Data path state machine active, i.e. not in Idle state
    • [11]DABORT (def=0x0) // Data transfer aborted by CMD12
    • [10]DBCKEND (def=0x0) // Data block sent/received
    • [9]DHOLD (def=0x0) // Data transfer Hold
    • [8]DATAEND (def=0x0) // Data transfer ended correctly
    • [7]CMDSENT (def=0x0) // Command sent (no response required)
    • [6]CMDREND (def=0x0) // Command response received (CRC check passed, or no CRC)
    • [5]RXOVERR (def=0x0) // Received FIFO overrun error (masked by hardware when IDMA is enabled)
    • [4]TXUNDERR (def=0x0) // Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
    • [3]DTIMEOUT (def=0x0) // Data timeout
    • [2]CTIMEOUT (def=0x0) // Command response timeout
    • [1]DCRCFAIL (def=0x0) // Data block sent/received (CRC check failed)
    • [0]CCRCFAIL (def=0x0) // Command response received (CRC check failed)
  • 0x520C8038ICR// interrupt clear register

    • [28]IDMABTCC (def=0x0) // IDMA buffer transfer complete clear bit
    • [27]IDMATEC (def=0x0) // IDMA transfer error clear bit
    • [26]CKSTOPC (def=0x0) // CKSTOP flag clear bit
    • [25]VSWENDC (def=0x0) // VSWEND flag clear bit
    • [24]ACKTIMEOUTC (def=0x0) // ACKTIMEOUT flag clear bit
    • [23]ACKFAILC (def=0x0) // ACKFAIL flag clear bit
    • [22]SDIOITC (def=0x0) // SDIOIT flag clear bit
    • [21]BUSYD0ENDC (def=0x0) // BUSYD0END flag clear bit
    • [11]DABORTC (def=0x0) // DABORT flag clear bit
    • [10]DBCKENDC (def=0x0) // DBCKEND flag clear bit
    • [9]DHOLDC (def=0x0) // DHOLD flag clear bit
    • [8]DATAENDC (def=0x0) // DATAEND flag clear bit
    • [7]CMDSENTC (def=0x0) // CMDSENT flag clear bit
    • [6]CMDRENDC (def=0x0) // CMDREND flag clear bit
    • [5]RXOVERRC (def=0x0) // RXOVERR flag clear bit
    • [4]TXUNDERRC (def=0x0) // TXUNDERR flag clear bit
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUT flag clear bit
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUT flag clear bit
    • [1]DCRCFAILC (def=0x0) // DCRCFAIL flag clear bit
    • [0]CCRCFAILC (def=0x0) // CCRCFAIL flag clear bit
  • 0x520C803CMASKR// mask register

    • [28]IDMABTCIE (def=0x0) // IDMA buffer transfer complete interrupt enable
    • [26]CKSTOPIE (def=0x0) // Voltage Switch clock stopped interrupt enable
    • [25]VSWENDIE (def=0x0) // Voltage switch critical timing section completion interrupt enable
    • [24]ACKTIMEOUTIE (def=0x0) // Acknowledgment timeout interrupt enable
    • [23]ACKFAILIE (def=0x0) // Acknowledgment Fail interrupt enable
    • [22]SDIOITIE (def=0x0) // SDIO mode interrupt received interrupt enable
    • [21]BUSYD0ENDIE (def=0x0) // BUSYD0END interrupt enable
    • [18]TXFIFOEIE (def=0x0) // Tx FIFO empty interrupt enable
    • [17]RXFIFOFIE (def=0x0) // Rx FIFO full interrupt enable
    • [15]RXFIFOHFIE (def=0x0) // Rx FIFO half full interrupt enable
    • [14]TXFIFOHEIE (def=0x0) // Tx FIFO half empty interrupt enable
    • [11]DABORTIE (def=0x0) // Data transfer aborted interrupt enable
    • [10]DBCKENDIE (def=0x0) // Data block end interrupt enable
    • [9]DHOLDIE (def=0x0) // Data hold interrupt enable
    • [8]DATAENDIE (def=0x0) // Data end interrupt enable
    • [7]CMDSENTIE (def=0x0) // Command sent interrupt enable
    • [6]CMDRENDIE (def=0x0) // Command response received interrupt enable
    • [5]RXOVERRIE (def=0x0) // Rx FIFO overrun error interrupt enable
    • [4]TXUNDERRIE (def=0x0) // Tx FIFO underrun error interrupt enable
    • [3]DTIMEOUTIE (def=0x0) // Data timeout interrupt enable
    • [2]CTIMEOUTIE (def=0x0) // Command timeout interrupt enable
    • [1]DCRCFAILIE (def=0x0) // Data CRC fail interrupt enable
    • [0]CCRCFAILIE (def=0x0) // Command CRC fail interrupt enable
  • 0x520C8040ACKTIMER// acknowledgment timer register

    • [0:24]ACKTIME (def=0x0) // Boot acknowledgment timeout period
  • 0x520C8080FIFOR0// data FIFO register 0

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8084FIFOR1// data FIFO register 1

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8088FIFOR2// data FIFO register 2

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C808CFIFOR3// data FIFO register 3

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8090FIFOR4// data FIFO register 4

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8094FIFOR5// data FIFO register 5

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8098FIFOR6// data FIFO register 6

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C809CFIFOR7// data FIFO register 7

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80A0FIFOR8// data FIFO register 8

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80A4FIFOR9// data FIFO register 9

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80A8FIFOR10// data FIFO register 10

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80ACFIFOR11// data FIFO register 11

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80B0FIFOR12// data FIFO register 12

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80B4FIFOR13// data FIFO register 13

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80B8FIFOR14// data FIFO register 14

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C80BCFIFOR15// data FIFO register 15

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8050SDMMC_IDMACTRLR// DMA control register

    • [0]IDMAEN (def=0x0) // IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
    • [1]IDMABMODE (def=0x0) // Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)
  • 0x520C8054SDMMC_IDMABSIZER// buffer size register

    • [5:16]IDMABNDT (def=0x0) // Number of bytes per buffer
  • 0x520C8058SDMMC_IDMABASER// buffer base address register

    • [0:31]IDMABASE (def=0x0) // Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only
  • 0x520C8064SDMMC_IDMALAR// linked list address register

    • [31]ULA (def=0x0) // Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select li
    • [30]ULS (def=0x0) // Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMOD
    • [29]ABR (def=0x0) // Acknowledge linked list buffer ready
    • [2:15]IDMALA (def=0x0) // Acknowledge linked list buffer ready
  • 0x520C8068SDMMC_IDMABAR// linked list memory base register

    • [2:31]IDMABA (def=0x0) // Word aligned Linked list memory base address
• 0x420C8C00SDMMC2//

  • 0x420C8C00POWER// power control register

    • [0:1]PWRCTRL (def=0x0) // SDMMC state control bits
    • [2]VSWITCH (def=0x0) // Voltage switch sequence start
    • [3]VSWITCHEN (def=0x0) // Voltage switch procedure enable
    • [4]DIRPOL (def=0x0) // Data and command direction signals polarity selection
  • 0x420C8C04CLKCR// clock control register

    • [20:21]SELCLKRX (def=0x0) // Receive clock selection
    • [19]BUSSPEED (def=0x0) // Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
    • [18]DDR (def=0x0) // Data rate signaling selection
    • [17]HWFC_EN (def=0x0) // HW Flow Control enable
    • [16]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14:15]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [12]PWRSAV (def=0x0) // Power saving configuration bit
    • [0:9]CLKDIV (def=0x0) // Clock divide factor
  • 0x420C8C08ARGR// argument register

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x420C8C0CCMDR// command register

    • [16]CMDSUSPEND (def=0x0) // The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
    • [15]BOOTEN (def=0x0) // Enable boot mode procedure
    • [14]BOOTMODE (def=0x0) // Select the boot mode procedure to be used
    • [13]DTHOLD (def=0x0) // Hold new data block transmission and reception in the DPSM
    • [12]CPSMEN (def=0x0) // Command path state machine (CPSM) Enable bit
    • [11]WAITPEND (def=0x0) // CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
    • [10]WAITINT (def=0x0) // CPSM waits for interrupt request
    • [8:9]WAITRESP (def=0x0) // Wait for response bits
    • [7]CMDSTOP (def=0x0) // The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
    • [6]CMDTRANS (def=0x0) // The CPSM treats the command as a data transfer command, stops the interrupt period, and signals Dat
    • [0:5]CMDINDEX (def=0x0) // Command index
  • 0x420C8C10RESPCMDR// command response register

    • [0:5]RESPCMD (def=0x0) // Response command index
  • 0x420C8C14RESP1// response 1 register

    • [0:31]CARDSTATUS1 (def=0x0) // CARDSTATUS1
  • 0x420C8C18RESP2// response 2 register

    • [0:31]CARDSTATUS2 (def=0x0) // CARDSTATUS2
  • 0x420C8C1CRESP3// response 3 register

    • [0:31]CARDSTATUS3 (def=0x0) // CARDSTATUS3
  • 0x420C8C20RESP4// response 4 register

    • [0:31]CARDSTATUS4 (def=0x0) // CARDSTATUS4
  • 0x420C8C24DTIMER// data timer register

    • [0:31]DATATIME (def=0x0) // Data and R1b busy timeout period
  • 0x420C8C28DLENR// data length register

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x420C8C2CDCTRL// data control register

    • [13]FIFORST (def=0x0) // FIFO reset, will flush any remaining data
    • [12]BOOTACKEN (def=0x0) // Enable the reception of the boot acknowledgment
    • [11]SDIOEN (def=0x0) // SD I/O enable functions
    • [10]RWMOD (def=0x0) // Read wait mode
    • [9]RWSTOP (def=0x0) // Read wait stop
    • [8]RWSTART (def=0x0) // Read wait start
    • [4:7]DBLOCKSIZE (def=0x0) // Data block size
    • [2:3]DTMODE (def=0x0) // Data transfer mode selection
    • [1]DTDIR (def=0x0) // Data transfer direction selection
    • [0]DTEN (def=0x0) // DTEN
  • 0x420C8C30DCNTR// data counter register

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x420C8C34STAR// status register

    • [28]IDMABTC (def=0x0) // IDMA buffer transfer complete
    • [27]IDMATE (def=0x0) // IDMA transfer error
    • [26]CKSTOP (def=0x0) // SDMMC_CK stopped in Voltage switch procedure
    • [25]VSWEND (def=0x0) // Voltage switch critical timing section completion
    • [24]ACKTIMEOUT (def=0x0) // Boot acknowledgment timeout
    • [23]ACKFAIL (def=0x0) // Boot acknowledgment received (boot acknowledgment check fail)
    • [22]SDIOIT (def=0x0) // SDIO interrupt received
    • [21]BUSYD0END (def=0x0) // end of SDMMC_D0 Busy following a CMD response detected
    • [20]BUSYD0 (def=0x0) // Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SD
    • [19]RXFIFOE (def=0x0) // Receive FIFO empty
    • [18]TXFIFOE (def=0x0) // Transmit FIFO empty
    • [17]RXFIFOF (def=0x0) // Receive FIFO full
    • [16]TXFIFOF (def=0x0) // Transmit FIFO full
    • [15]RXFIFOHF (def=0x0) // Receive FIFO half full
    • [14]TXFIFOHE (def=0x0) // Transmit FIFO half empty
    • [13]CPSMACT (def=0x0) // Command path state machine active, i.e. not in Idle state
    • [12]DPSMACT (def=0x0) // Data path state machine active, i.e. not in Idle state
    • [11]DABORT (def=0x0) // Data transfer aborted by CMD12
    • [10]DBCKEND (def=0x0) // Data block sent/received
    • [9]DHOLD (def=0x0) // Data transfer Hold
    • [8]DATAEND (def=0x0) // Data transfer ended correctly
    • [7]CMDSENT (def=0x0) // Command sent (no response required)
    • [6]CMDREND (def=0x0) // Command response received (CRC check passed, or no CRC)
    • [5]RXOVERR (def=0x0) // Received FIFO overrun error (masked by hardware when IDMA is enabled)
    • [4]TXUNDERR (def=0x0) // Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
    • [3]DTIMEOUT (def=0x0) // Data timeout
    • [2]CTIMEOUT (def=0x0) // Command response timeout
    • [1]DCRCFAIL (def=0x0) // Data block sent/received (CRC check failed)
    • [0]CCRCFAIL (def=0x0) // Command response received (CRC check failed)
  • 0x420C8C38ICR// interrupt clear register

    • [28]IDMABTCC (def=0x0) // IDMA buffer transfer complete clear bit
    • [27]IDMATEC (def=0x0) // IDMA transfer error clear bit
    • [26]CKSTOPC (def=0x0) // CKSTOP flag clear bit
    • [25]VSWENDC (def=0x0) // VSWEND flag clear bit
    • [24]ACKTIMEOUTC (def=0x0) // ACKTIMEOUT flag clear bit
    • [23]ACKFAILC (def=0x0) // ACKFAIL flag clear bit
    • [22]SDIOITC (def=0x0) // SDIOIT flag clear bit
    • [21]BUSYD0ENDC (def=0x0) // BUSYD0END flag clear bit
    • [11]DABORTC (def=0x0) // DABORT flag clear bit
    • [10]DBCKENDC (def=0x0) // DBCKEND flag clear bit
    • [9]DHOLDC (def=0x0) // DHOLD flag clear bit
    • [8]DATAENDC (def=0x0) // DATAEND flag clear bit
    • [7]CMDSENTC (def=0x0) // CMDSENT flag clear bit
    • [6]CMDRENDC (def=0x0) // CMDREND flag clear bit
    • [5]RXOVERRC (def=0x0) // RXOVERR flag clear bit
    • [4]TXUNDERRC (def=0x0) // TXUNDERR flag clear bit
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUT flag clear bit
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUT flag clear bit
    • [1]DCRCFAILC (def=0x0) // DCRCFAIL flag clear bit
    • [0]CCRCFAILC (def=0x0) // CCRCFAIL flag clear bit
  • 0x420C8C3CMASKR// mask register

    • [28]IDMABTCIE (def=0x0) // IDMA buffer transfer complete interrupt enable
    • [26]CKSTOPIE (def=0x0) // Voltage Switch clock stopped interrupt enable
    • [25]VSWENDIE (def=0x0) // Voltage switch critical timing section completion interrupt enable
    • [24]ACKTIMEOUTIE (def=0x0) // Acknowledgment timeout interrupt enable
    • [23]ACKFAILIE (def=0x0) // Acknowledgment Fail interrupt enable
    • [22]SDIOITIE (def=0x0) // SDIO mode interrupt received interrupt enable
    • [21]BUSYD0ENDIE (def=0x0) // BUSYD0END interrupt enable
    • [18]TXFIFOEIE (def=0x0) // Tx FIFO empty interrupt enable
    • [17]RXFIFOFIE (def=0x0) // Rx FIFO full interrupt enable
    • [15]RXFIFOHFIE (def=0x0) // Rx FIFO half full interrupt enable
    • [14]TXFIFOHEIE (def=0x0) // Tx FIFO half empty interrupt enable
    • [11]DABORTIE (def=0x0) // Data transfer aborted interrupt enable
    • [10]DBCKENDIE (def=0x0) // Data block end interrupt enable
    • [9]DHOLDIE (def=0x0) // Data hold interrupt enable
    • [8]DATAENDIE (def=0x0) // Data end interrupt enable
    • [7]CMDSENTIE (def=0x0) // Command sent interrupt enable
    • [6]CMDRENDIE (def=0x0) // Command response received interrupt enable
    • [5]RXOVERRIE (def=0x0) // Rx FIFO overrun error interrupt enable
    • [4]TXUNDERRIE (def=0x0) // Tx FIFO underrun error interrupt enable
    • [3]DTIMEOUTIE (def=0x0) // Data timeout interrupt enable
    • [2]CTIMEOUTIE (def=0x0) // Command timeout interrupt enable
    • [1]DCRCFAILIE (def=0x0) // Data CRC fail interrupt enable
    • [0]CCRCFAILIE (def=0x0) // Command CRC fail interrupt enable
  • 0x420C8C40ACKTIMER// acknowledgment timer register

    • [0:24]ACKTIME (def=0x0) // Boot acknowledgment timeout period
  • 0x420C8C80FIFOR0// data FIFO register 0

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C84FIFOR1// data FIFO register 1

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C88FIFOR2// data FIFO register 2

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C8CFIFOR3// data FIFO register 3

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C90FIFOR4// data FIFO register 4

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C94FIFOR5// data FIFO register 5

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C98FIFOR6// data FIFO register 6

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C9CFIFOR7// data FIFO register 7

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CA0FIFOR8// data FIFO register 8

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CA4FIFOR9// data FIFO register 9

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CA8FIFOR10// data FIFO register 10

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CACFIFOR11// data FIFO register 11

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CB0FIFOR12// data FIFO register 12

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CB4FIFOR13// data FIFO register 13

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CB8FIFOR14// data FIFO register 14

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8CBCFIFOR15// data FIFO register 15

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x420C8C50SDMMC_IDMACTRLR// DMA control register

    • [0]IDMAEN (def=0x0) // IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
    • [1]IDMABMODE (def=0x0) // Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)
  • 0x420C8C54SDMMC_IDMABSIZER// buffer size register

    • [5:16]IDMABNDT (def=0x0) // Number of bytes per buffer
  • 0x420C8C58SDMMC_IDMABASER// buffer base address register

    • [0:31]IDMABASE (def=0x0) // Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only
  • 0x420C8C64SDMMC_IDMALAR// linked list address register

    • [31]ULA (def=0x0) // Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select li
    • [30]ULS (def=0x0) // Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMOD
    • [29]ABR (def=0x0) // Acknowledge linked list buffer ready
    • [2:15]IDMALA (def=0x0) // Acknowledge linked list buffer ready
  • 0x420C8C68SDMMC_IDMABAR// linked list memory base register

    • [2:31]IDMABA (def=0x0) // Word aligned Linked list memory base address
  interrupts:
  • [79] SDMMC2 // SDMMC2 global interrupt
• 0x520C8C00SEC_SDMMC2//

  • 0x520C8C00POWER// power control register

    • [0:1]PWRCTRL (def=0x0) // SDMMC state control bits
    • [2]VSWITCH (def=0x0) // Voltage switch sequence start
    • [3]VSWITCHEN (def=0x0) // Voltage switch procedure enable
    • [4]DIRPOL (def=0x0) // Data and command direction signals polarity selection
  • 0x520C8C04CLKCR// clock control register

    • [20:21]SELCLKRX (def=0x0) // Receive clock selection
    • [19]BUSSPEED (def=0x0) // Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
    • [18]DDR (def=0x0) // Data rate signaling selection
    • [17]HWFC_EN (def=0x0) // HW Flow Control enable
    • [16]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14:15]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [12]PWRSAV (def=0x0) // Power saving configuration bit
    • [0:9]CLKDIV (def=0x0) // Clock divide factor
  • 0x520C8C08ARGR// argument register

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x520C8C0CCMDR// command register

    • [16]CMDSUSPEND (def=0x0) // The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
    • [15]BOOTEN (def=0x0) // Enable boot mode procedure
    • [14]BOOTMODE (def=0x0) // Select the boot mode procedure to be used
    • [13]DTHOLD (def=0x0) // Hold new data block transmission and reception in the DPSM
    • [12]CPSMEN (def=0x0) // Command path state machine (CPSM) Enable bit
    • [11]WAITPEND (def=0x0) // CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
    • [10]WAITINT (def=0x0) // CPSM waits for interrupt request
    • [8:9]WAITRESP (def=0x0) // Wait for response bits
    • [7]CMDSTOP (def=0x0) // The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
    • [6]CMDTRANS (def=0x0) // The CPSM treats the command as a data transfer command, stops the interrupt period, and signals Dat
    • [0:5]CMDINDEX (def=0x0) // Command index
  • 0x520C8C10RESPCMDR// command response register

    • [0:5]RESPCMD (def=0x0) // Response command index
  • 0x520C8C14RESP1// response 1 register

    • [0:31]CARDSTATUS1 (def=0x0) // CARDSTATUS1
  • 0x520C8C18RESP2// response 2 register

    • [0:31]CARDSTATUS2 (def=0x0) // CARDSTATUS2
  • 0x520C8C1CRESP3// response 3 register

    • [0:31]CARDSTATUS3 (def=0x0) // CARDSTATUS3
  • 0x520C8C20RESP4// response 4 register

    • [0:31]CARDSTATUS4 (def=0x0) // CARDSTATUS4
  • 0x520C8C24DTIMER// data timer register

    • [0:31]DATATIME (def=0x0) // Data and R1b busy timeout period
  • 0x520C8C28DLENR// data length register

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x520C8C2CDCTRL// data control register

    • [13]FIFORST (def=0x0) // FIFO reset, will flush any remaining data
    • [12]BOOTACKEN (def=0x0) // Enable the reception of the boot acknowledgment
    • [11]SDIOEN (def=0x0) // SD I/O enable functions
    • [10]RWMOD (def=0x0) // Read wait mode
    • [9]RWSTOP (def=0x0) // Read wait stop
    • [8]RWSTART (def=0x0) // Read wait start
    • [4:7]DBLOCKSIZE (def=0x0) // Data block size
    • [2:3]DTMODE (def=0x0) // Data transfer mode selection
    • [1]DTDIR (def=0x0) // Data transfer direction selection
    • [0]DTEN (def=0x0) // DTEN
  • 0x520C8C30DCNTR// data counter register

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x520C8C34STAR// status register

    • [28]IDMABTC (def=0x0) // IDMA buffer transfer complete
    • [27]IDMATE (def=0x0) // IDMA transfer error
    • [26]CKSTOP (def=0x0) // SDMMC_CK stopped in Voltage switch procedure
    • [25]VSWEND (def=0x0) // Voltage switch critical timing section completion
    • [24]ACKTIMEOUT (def=0x0) // Boot acknowledgment timeout
    • [23]ACKFAIL (def=0x0) // Boot acknowledgment received (boot acknowledgment check fail)
    • [22]SDIOIT (def=0x0) // SDIO interrupt received
    • [21]BUSYD0END (def=0x0) // end of SDMMC_D0 Busy following a CMD response detected
    • [20]BUSYD0 (def=0x0) // Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SD
    • [19]RXFIFOE (def=0x0) // Receive FIFO empty
    • [18]TXFIFOE (def=0x0) // Transmit FIFO empty
    • [17]RXFIFOF (def=0x0) // Receive FIFO full
    • [16]TXFIFOF (def=0x0) // Transmit FIFO full
    • [15]RXFIFOHF (def=0x0) // Receive FIFO half full
    • [14]TXFIFOHE (def=0x0) // Transmit FIFO half empty
    • [13]CPSMACT (def=0x0) // Command path state machine active, i.e. not in Idle state
    • [12]DPSMACT (def=0x0) // Data path state machine active, i.e. not in Idle state
    • [11]DABORT (def=0x0) // Data transfer aborted by CMD12
    • [10]DBCKEND (def=0x0) // Data block sent/received
    • [9]DHOLD (def=0x0) // Data transfer Hold
    • [8]DATAEND (def=0x0) // Data transfer ended correctly
    • [7]CMDSENT (def=0x0) // Command sent (no response required)
    • [6]CMDREND (def=0x0) // Command response received (CRC check passed, or no CRC)
    • [5]RXOVERR (def=0x0) // Received FIFO overrun error (masked by hardware when IDMA is enabled)
    • [4]TXUNDERR (def=0x0) // Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
    • [3]DTIMEOUT (def=0x0) // Data timeout
    • [2]CTIMEOUT (def=0x0) // Command response timeout
    • [1]DCRCFAIL (def=0x0) // Data block sent/received (CRC check failed)
    • [0]CCRCFAIL (def=0x0) // Command response received (CRC check failed)
  • 0x520C8C38ICR// interrupt clear register

    • [28]IDMABTCC (def=0x0) // IDMA buffer transfer complete clear bit
    • [27]IDMATEC (def=0x0) // IDMA transfer error clear bit
    • [26]CKSTOPC (def=0x0) // CKSTOP flag clear bit
    • [25]VSWENDC (def=0x0) // VSWEND flag clear bit
    • [24]ACKTIMEOUTC (def=0x0) // ACKTIMEOUT flag clear bit
    • [23]ACKFAILC (def=0x0) // ACKFAIL flag clear bit
    • [22]SDIOITC (def=0x0) // SDIOIT flag clear bit
    • [21]BUSYD0ENDC (def=0x0) // BUSYD0END flag clear bit
    • [11]DABORTC (def=0x0) // DABORT flag clear bit
    • [10]DBCKENDC (def=0x0) // DBCKEND flag clear bit
    • [9]DHOLDC (def=0x0) // DHOLD flag clear bit
    • [8]DATAENDC (def=0x0) // DATAEND flag clear bit
    • [7]CMDSENTC (def=0x0) // CMDSENT flag clear bit
    • [6]CMDRENDC (def=0x0) // CMDREND flag clear bit
    • [5]RXOVERRC (def=0x0) // RXOVERR flag clear bit
    • [4]TXUNDERRC (def=0x0) // TXUNDERR flag clear bit
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUT flag clear bit
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUT flag clear bit
    • [1]DCRCFAILC (def=0x0) // DCRCFAIL flag clear bit
    • [0]CCRCFAILC (def=0x0) // CCRCFAIL flag clear bit
  • 0x520C8C3CMASKR// mask register

    • [28]IDMABTCIE (def=0x0) // IDMA buffer transfer complete interrupt enable
    • [26]CKSTOPIE (def=0x0) // Voltage Switch clock stopped interrupt enable
    • [25]VSWENDIE (def=0x0) // Voltage switch critical timing section completion interrupt enable
    • [24]ACKTIMEOUTIE (def=0x0) // Acknowledgment timeout interrupt enable
    • [23]ACKFAILIE (def=0x0) // Acknowledgment Fail interrupt enable
    • [22]SDIOITIE (def=0x0) // SDIO mode interrupt received interrupt enable
    • [21]BUSYD0ENDIE (def=0x0) // BUSYD0END interrupt enable
    • [18]TXFIFOEIE (def=0x0) // Tx FIFO empty interrupt enable
    • [17]RXFIFOFIE (def=0x0) // Rx FIFO full interrupt enable
    • [15]RXFIFOHFIE (def=0x0) // Rx FIFO half full interrupt enable
    • [14]TXFIFOHEIE (def=0x0) // Tx FIFO half empty interrupt enable
    • [11]DABORTIE (def=0x0) // Data transfer aborted interrupt enable
    • [10]DBCKENDIE (def=0x0) // Data block end interrupt enable
    • [9]DHOLDIE (def=0x0) // Data hold interrupt enable
    • [8]DATAENDIE (def=0x0) // Data end interrupt enable
    • [7]CMDSENTIE (def=0x0) // Command sent interrupt enable
    • [6]CMDRENDIE (def=0x0) // Command response received interrupt enable
    • [5]RXOVERRIE (def=0x0) // Rx FIFO overrun error interrupt enable
    • [4]TXUNDERRIE (def=0x0) // Tx FIFO underrun error interrupt enable
    • [3]DTIMEOUTIE (def=0x0) // Data timeout interrupt enable
    • [2]CTIMEOUTIE (def=0x0) // Command timeout interrupt enable
    • [1]DCRCFAILIE (def=0x0) // Data CRC fail interrupt enable
    • [0]CCRCFAILIE (def=0x0) // Command CRC fail interrupt enable
  • 0x520C8C40ACKTIMER// acknowledgment timer register

    • [0:24]ACKTIME (def=0x0) // Boot acknowledgment timeout period
  • 0x520C8C80FIFOR0// data FIFO register 0

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C84FIFOR1// data FIFO register 1

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C88FIFOR2// data FIFO register 2

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C8CFIFOR3// data FIFO register 3

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C90FIFOR4// data FIFO register 4

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C94FIFOR5// data FIFO register 5

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C98FIFOR6// data FIFO register 6

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C9CFIFOR7// data FIFO register 7

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CA0FIFOR8// data FIFO register 8

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CA4FIFOR9// data FIFO register 9

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CA8FIFOR10// data FIFO register 10

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CACFIFOR11// data FIFO register 11

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CB0FIFOR12// data FIFO register 12

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CB4FIFOR13// data FIFO register 13

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CB8FIFOR14// data FIFO register 14

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8CBCFIFOR15// data FIFO register 15

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  • 0x520C8C50SDMMC_IDMACTRLR// DMA control register

    • [0]IDMAEN (def=0x0) // IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
    • [1]IDMABMODE (def=0x0) // Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)
  • 0x520C8C54SDMMC_IDMABSIZER// buffer size register

    • [5:16]IDMABNDT (def=0x0) // Number of bytes per buffer
  • 0x520C8C58SDMMC_IDMABASER// buffer base address register

    • [0:31]IDMABASE (def=0x0) // Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only
  • 0x520C8C64SDMMC_IDMALAR// linked list address register

    • [31]ULA (def=0x0) // Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select li
    • [30]ULS (def=0x0) // Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMOD
    • [29]ABR (def=0x0) // Acknowledge linked list buffer ready
    • [2:15]IDMALA (def=0x0) // Acknowledge linked list buffer ready
  • 0x520C8C68SDMMC_IDMABAR// linked list memory base register

    • [2:31]IDMABA (def=0x0) // Word aligned Linked list memory base address
• 0x46005000OPAMP// Operational amplifiers

  • 0x46005000OPAMP1_CSR// OPAMP1 control/status register

    • [0]OPAEN (def=0x0) // OPAMP enable
    • [1]OPALPM (def=0x0) // OPAMP low-power mode The OPAMP must be disabled to change this configuration.
    • [2:3]OPAMODE (def=0x0) // OPAMP PGA mode 00 and 01: internal PGA disabled
    • [4:5]PGA_GAIN (def=0x0) // OPAMP programmable amplifier gain value
    • [8:9]VM_SEL (def=0x0) // Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input
    • [10]VP_SEL (def=0x0) // Non-inverted input selection
    • [12]CALON (def=0x0) // Calibration mode enable
    • [13]CALSEL (def=0x0) // Calibration selection
    • [14]USERTRIM (def=0x0) // ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-p
    • [15]CALOUT (def=0x0) // OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggle
    • [30]OPAHSM (def=0x0) // OPAMP high-speed mode This bit is effective for both normal and low-power modes.
    • [31]OPA_RANGE (def=0x0) // OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP i
  • 0x46005004OPAMP1_OTR// OPAMP1 offset trimming register in normal mode

    • [0:4]TRIMOFFSETN (def=0x0) // Trim for NMOS differential pairs
    • [8:12]TRIMOFFSETP (def=0x0) // Trim for PMOS differential pairs
  • 0x46005008OPAMP1_LPOTR// OPAMP1 offset trimming register in low-power mode

    • [0:4]TRIMLPOFFSETN (def=0x0) // Low-power mode trim for NMOS differential pairs
    • [8:12]TRIMLPOFFSETP (def=0x0) // Low-power mode trim for PMOS differential pairs
  • 0x46005010OPAMP2_CRS// OPAMP2 control/status register

    • [0]OPAEN (def=0x0) // OPAMP enable
    • [1]OPALPM (def=0x0) // OPAMP low-power mode The OPAMP must be disabled to change this configuration.
    • [2:3]OPAMODE (def=0x0) // OPAMP PGA mode 00 and 01: internal PGA disabled
    • [4:5]PGA_GAIN (def=0x0) // OPAMP programmable amplifier gain value
    • [8:9]VM_SEL (def=0x0) // Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for fil
    • [10]VP_SEL (def=0x0) // Non inverted input selection
    • [12]CALON (def=0x0) // Calibration mode enable
    • [13]CALSEL (def=0x0) // Calibration selection
    • [14]USERTRIM (def=0x0) // ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-p
    • [15]CALOUT (def=0x0) // OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles.
    • [30]OPAHSM (def=0x0) // OPAMP high-speed mode This bit is effective for both normal and high-speed modes.
  • 0x46005014OPAMP2_OTR// OPAMP2 offset trimming register in normal mode

    • [0:4]TRIMOFFSETN (def=0x0) // Trim for NMOS differential pairs
    • [8:12]TRIMOFFSETP (def=0x0) // Trim for PMOS differential pairs
  • 0x46005018OPAMP2_LPOTR// OPAMP2 offset trimming register in low-power mode

    • [0:4]TRIMLPOFFSETN (def=0x0) // Low-power mode trim for NMOS differential pairs
    • [8:12]TRIMLPOFFSETP (def=0x0) // Low-power mode trim for PMOS differential pairs
• 0x56005000SEC_OPAMP//

  • 0x56005000OPAMP1_CSR// OPAMP1 control/status register

    • [0]OPAEN (def=0x0) // OPAMP enable
    • [1]OPALPM (def=0x0) // OPAMP low-power mode The OPAMP must be disabled to change this configuration.
    • [2:3]OPAMODE (def=0x0) // OPAMP PGA mode 00 and 01: internal PGA disabled
    • [4:5]PGA_GAIN (def=0x0) // OPAMP programmable amplifier gain value
    • [8:9]VM_SEL (def=0x0) // Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input
    • [10]VP_SEL (def=0x0) // Non-inverted input selection
    • [12]CALON (def=0x0) // Calibration mode enable
    • [13]CALSEL (def=0x0) // Calibration selection
    • [14]USERTRIM (def=0x0) // ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-p
    • [15]CALOUT (def=0x0) // OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggle
    • [30]OPAHSM (def=0x0) // OPAMP high-speed mode This bit is effective for both normal and low-power modes.
    • [31]OPA_RANGE (def=0x0) // OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP i
  • 0x56005004OPAMP1_OTR// OPAMP1 offset trimming register in normal mode

    • [0:4]TRIMOFFSETN (def=0x0) // Trim for NMOS differential pairs
    • [8:12]TRIMOFFSETP (def=0x0) // Trim for PMOS differential pairs
  • 0x56005008OPAMP1_LPOTR// OPAMP1 offset trimming register in low-power mode

    • [0:4]TRIMLPOFFSETN (def=0x0) // Low-power mode trim for NMOS differential pairs
    • [8:12]TRIMLPOFFSETP (def=0x0) // Low-power mode trim for PMOS differential pairs
  • 0x56005010OPAMP2_CRS// OPAMP2 control/status register

    • [0]OPAEN (def=0x0) // OPAMP enable
    • [1]OPALPM (def=0x0) // OPAMP low-power mode The OPAMP must be disabled to change this configuration.
    • [2:3]OPAMODE (def=0x0) // OPAMP PGA mode 00 and 01: internal PGA disabled
    • [4:5]PGA_GAIN (def=0x0) // OPAMP programmable amplifier gain value
    • [8:9]VM_SEL (def=0x0) // Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for fil
    • [10]VP_SEL (def=0x0) // Non inverted input selection
    • [12]CALON (def=0x0) // Calibration mode enable
    • [13]CALSEL (def=0x0) // Calibration selection
    • [14]USERTRIM (def=0x0) // ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-p
    • [15]CALOUT (def=0x0) // OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles.
    • [30]OPAHSM (def=0x0) // OPAMP high-speed mode This bit is effective for both normal and high-speed modes.
  • 0x56005014OPAMP2_OTR// OPAMP2 offset trimming register in normal mode

    • [0:4]TRIMOFFSETN (def=0x0) // Trim for NMOS differential pairs
    • [8:12]TRIMOFFSETP (def=0x0) // Trim for PMOS differential pairs
  • 0x56005018OPAMP2_LPOTR// OPAMP2 offset trimming register in low-power mode

    • [0:4]TRIMLPOFFSETN (def=0x0) // Low-power mode trim for NMOS differential pairs
    • [8:12]TRIMLPOFFSETP (def=0x0) // Low-power mode trim for PMOS differential pairs
• 0x420CF000DLYBOS1// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock

  • 0x420CF000DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x420CF004DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x520CF000SEC_DLYBOS1//

  • 0x520CF000DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x520CF004DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x420CF400DLYBOS2//

  • 0x420CF400DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x420CF404DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x520CF400SEC_DLYBOS2//

  • 0x520CF400DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x520CF404DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x420C8400DLYBSD1//

  • 0x420C8400DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x420C8404DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x520C8400SEC_DLYBSD1//

  • 0x520C8400DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x520C8404DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x420C8800DLYBSD2//

  • 0x420C8800DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x420C8804DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x520C8800SEC_DLYBSD2//

  • 0x520C8800DLYB_CR// control register

    • [0]DEN (def=0x0) // Operational amplifier Enable
    • [1]SEN (def=0x0) // OPALPM
  • 0x520C8804DLYB_CFGR// configuration register

    • [0:3]SEL (def=0x0) // SEL
    • [8:14]UNIT (def=0x0) // UNIT
    • [16:27]LNG (def=0x0) // LNG
    • [31]LNGF (def=0x0) // LNGF
• 0x420C0C00SAES// Secure AES coprocessor

  • 0x420C0C00CR// control register

    • [31]IPRST (def=0x0) // IPRST
    • [28:30]KEYSEL (def=0x0) // KEYSEL
    • [26:27]KSHAREID (def=0x0) // KSHAREID
    • [24:25]KMOD (def=0x0) // KMOD
    • [19]KEYPROT (def=0x0) // KEYPROT
    • [18]KEYSIZE (def=0x0) // KEYSIZE
    • [12]DMAOUTEN (def=0x0) // DMAOUTEN
    • [11]DMAINEN (def=0x0) // DMAINEN
    • [5:6]CHMOD (def=0x0) // CHMOD
    • [3:4]MODE (def=0x0) // MODE
    • [1:2]DATATYPE (def=0x0) // DATATYPE
    • [0]EN (def=0x0) // SAES enable
  • 0x420C0C04SR// status register

    • [7]KEYVALID (def=0x0) // Key Valid flag
    • [3]BUSY (def=0x0) // BUSY
    • [2]WRERR (def=0x0) // Write error flag
    • [1]RDERR (def=0x0) // Read error flag
    • [0]CCF (def=0x0) // Computation complete flag
  • 0x420C0C08DINR// data input register

    • [0:31]DIN (def=0x0) // Input data word
  • 0x420C0C0CDOUTR// data output register

    • [0:31]DOUT (def=0x0) // Output data word
  • 0x420C0C10KEYR0// key register 0

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [31:0]
  • 0x420C0C14KEYR1// key register 1

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [63:32]
  • 0x420C0C18KEYR2// key register 2

    • [0:31]KEYR (def=0x0) // Cryptographic key, bits [95:64]
  • 0x420C0C1CKEYR3// key register 3

    • [0:31]SAES_KEYR3 (def=0x0) // Cryptographic key, bits [127:96]
  • 0x420C0C20IVR0// initialization vector register 0

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [31:0]
  • 0x420C0C24IVR1// initialization vector register 1

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [63:32]
  • 0x420C0C28IVR2// initialization vector register 2

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [95:64]
  • 0x420C0C2CIVR3// initialization vector register 3

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [127:96]
  • 0x420C0C30KEYR4// key register 4

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [159:128]
  • 0x420C0C34KEYR5// key register 5

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [191:160]
  • 0x420C0C38KEYR6// key register 6

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [223:192]
  • 0x420C0C3CKEYR7// key register 7

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [255:224]
  • 0x420C0D00DPACFGR// configuration register

    • [31]CONFIGLOCK (def=0x0) // CONFIGLOCK
    • [3:4]TRIMCFG (def=0x1) // TRIMCFG
    • [2]RESEED (def=0x0) // RESEED
    • [1]REDCFG (def=0x0) // REDCFG
  • 0x420C0F00IER// interrupt enable register

    • [3]RNGEIE (def=0x0) // RNGEIE
    • [2]KEIE (def=0x0) // Key error interrupt enable
    • [1]RWEIE (def=0x0) // Read or write error interrupt enable
    • [0]CCFIE (def=0x0) // Computation complete flag interrupt enable
  • 0x420C0F04ISR// interrupt status register

    • [3]RNGEIF (def=0x0) // RNGEIF
    • [2]KEIF (def=0x0) // Key error interrupt flag
    • [1]RWEIF (def=0x0) // Read or write error interrupt flag
    • [0]CCF (def=0x0) // Computation complete flag
  • 0x420C0F08ICR// interrupt clear register

    • [3]RNGEIF (def=0x0) // RNGEIF
    • [2]KEIF (def=0x0) // Key error interrupt flag clear
    • [1]RWEIF (def=0x0) // Read or write error interrupt flag clear
    • [0]CCF (def=0x0) // Computation complete flag clear
  interrupts:
  • [28] SAES // SAES global interrupt
• 0x520C0C00SEC_SAES//

  • 0x520C0C00CR// control register

    • [31]IPRST (def=0x0) // IPRST
    • [28:30]KEYSEL (def=0x0) // KEYSEL
    • [26:27]KSHAREID (def=0x0) // KSHAREID
    • [24:25]KMOD (def=0x0) // KMOD
    • [19]KEYPROT (def=0x0) // KEYPROT
    • [18]KEYSIZE (def=0x0) // KEYSIZE
    • [12]DMAOUTEN (def=0x0) // DMAOUTEN
    • [11]DMAINEN (def=0x0) // DMAINEN
    • [5:6]CHMOD (def=0x0) // CHMOD
    • [3:4]MODE (def=0x0) // MODE
    • [1:2]DATATYPE (def=0x0) // DATATYPE
    • [0]EN (def=0x0) // SAES enable
  • 0x520C0C04SR// status register

    • [7]KEYVALID (def=0x0) // Key Valid flag
    • [3]BUSY (def=0x0) // BUSY
    • [2]WRERR (def=0x0) // Write error flag
    • [1]RDERR (def=0x0) // Read error flag
    • [0]CCF (def=0x0) // Computation complete flag
  • 0x520C0C08DINR// data input register

    • [0:31]DIN (def=0x0) // Input data word
  • 0x520C0C0CDOUTR// data output register

    • [0:31]DOUT (def=0x0) // Output data word
  • 0x520C0C10KEYR0// key register 0

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [31:0]
  • 0x520C0C14KEYR1// key register 1

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [63:32]
  • 0x520C0C18KEYR2// key register 2

    • [0:31]KEYR (def=0x0) // Cryptographic key, bits [95:64]
  • 0x520C0C1CKEYR3// key register 3

    • [0:31]SAES_KEYR3 (def=0x0) // Cryptographic key, bits [127:96]
  • 0x520C0C20IVR0// initialization vector register 0

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [31:0]
  • 0x520C0C24IVR1// initialization vector register 1

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [63:32]
  • 0x520C0C28IVR2// initialization vector register 2

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [95:64]
  • 0x520C0C2CIVR3// initialization vector register 3

    • [0:31]IVI (def=0x0) // Initialization vector input, bits [127:96]
  • 0x520C0C30KEYR4// key register 4

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [159:128]
  • 0x520C0C34KEYR5// key register 5

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [191:160]
  • 0x520C0C38KEYR6// key register 6

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [223:192]
  • 0x520C0C3CKEYR7// key register 7

    • [0:31]KEY (def=0x0) // Cryptographic key, bits [255:224]
  • 0x520C0D00DPACFGR// configuration register

    • [31]CONFIGLOCK (def=0x0) // CONFIGLOCK
    • [3:4]TRIMCFG (def=0x1) // TRIMCFG
    • [2]RESEED (def=0x0) // RESEED
    • [1]REDCFG (def=0x0) // REDCFG
  • 0x520C0F00IER// interrupt enable register

    • [3]RNGEIE (def=0x0) // RNGEIE
    • [2]KEIE (def=0x0) // Key error interrupt enable
    • [1]RWEIE (def=0x0) // Read or write error interrupt enable
    • [0]CCFIE (def=0x0) // Computation complete flag interrupt enable
  • 0x520C0F04ISR// interrupt status register

    • [3]RNGEIF (def=0x0) // RNGEIF
    • [2]KEIF (def=0x0) // Key error interrupt flag
    • [1]RWEIF (def=0x0) // Read or write error interrupt flag
    • [0]CCF (def=0x0) // Computation complete flag
  • 0x520C0F08ICR// interrupt clear register

    • [3]RNGEIF (def=0x0) // RNGEIF
    • [2]KEIF (def=0x0) // Key error interrupt flag clear
    • [1]RWEIF (def=0x0) // Read or write error interrupt flag clear
    • [0]CCF (def=0x0) // Computation complete flag clear
• 0x42040000OTG_FS// OTG_FS

  • 0x42040000GOTGCTL// The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.

    • [0]SRQSCS (def=0x0) // SRQSCS
    • [1]SRQ (def=0x0) // SRQ
    • [2]VBVALOEN (def=0x0) // VBVALOEN
    • [3]VBVALOVAL (def=0x0) // VBVALOVAL
    • [4]AVALOEN (def=0x0) // AVALOEN
    • [5]AVALOVAL (def=0x0) // AVALOVAL
    • [6]BVALOEN (def=0x0) // BVALOEN
    • [7]BVALOVAL (def=0x0) // BVALOVAL
    • [8]HNGSCS (def=0x0) // HNGSCS
    • [9]HNPRQ (def=0x0) // HNPRQ
    • [10]HSHNPEN (def=0x0) // HSHNPEN
    • [11]DHNPEN (def=0x0) // DHNPEN
    • [12]EHEN (def=0x0) // EHEN
    • [16]CIDSTS (def=0x1) // CIDSTS
    • [17]DBCT (def=0x0) // DBCT
    • [18]ASVLD (def=0x0) // ASVLD
    • [19]BSVLD (def=0x0) // BSVLD
    • [20]OTGVER (def=0x0) // OTGVER
    • [21]CURMOD (def=0x0) // CURMOD
  • 0x42040004GOTGINT// The application reads this register whenever there is an OTG interrupt and clears the bits in this

    • [2]SEDET (def=0x0) // SEDET
    • [8]SRSSCHG (def=0x0) // SRSSCHG
    • [9]HNSSCHG (def=0x0) // HNSSCHG
    • [17]HNGDET (def=0x0) // HNGDET
    • [18]ADTOCHG (def=0x0) // ADTOCHG
    • [19]DBCDNE (def=0x0) // DBCDNE
  • 0x42040008GAHBCFG// This register can be used to configure the core after power-on or a change in mode. This register m

    • [0]GINTMSK (def=0x0) // GINTMSK
    • [7]TXFELVL (def=0x0) // TXFELVL
    • [8]PTXFELVL (def=0x0) // PTXFELVL
  • 0x4204000CGUSBCFG// This register can be used to configure the core after power-on or a changing to host mode or device

    • [0:2]TOCAL (def=0x0) // TOCAL
    • [6]PHYSEL (def=0x1) // PHYSEL
    • [8]SRPCAP (def=0x0) // SRPCAP
    • [9]HNPCAP (def=0x0) // HNPCAP
    • [10:13]TRDT (def=0x5) // TRDT
    • [29]FHMOD (def=0x0) // FHMOD
    • [30]FDMOD (def=0x0) // FDMOD
  • 0x42040010GRSTCTL// The application uses this register to reset various hardware features inside the core.

    • [0]CSRST (def=0x0) // CSRST
    • [1]PSRST (def=0x0) // PSRST
    • [2]FSRST (def=0x0) // FSRST
    • [4]RXFFLSH (def=0x0) // RXFFLSH
    • [5]TXFFLSH (def=0x0) // TXFFLSH
    • [6:10]TXFNUM (def=0x0) // TXFNUM
    • [31]AHBIDL (def=0x1) // AHBIDL
  • 0x42040014GINTSTS// This register interrupts the application for system-level events in the current mode (device mode o

    • [0]CMOD (def=0x0) // CMOD
    • [1]MMIS (def=0x0) // MMIS
    • [2]OTGINT (def=0x0) // OTGINT
    • [3]SOF (def=0x0) // SOF
    • [4]RXFLVL (def=0x0) // RXFLVL
    • [5]NPTXFE (def=0x1) // NPTXFE
    • [6]GINAKEFF (def=0x0) // GINAKEFF
    • [7]GONAKEFF (def=0x0) // GONAKEFF
    • [10]ESUSP (def=0x0) // ESUSP
    • [11]USBSUSP (def=0x0) // USBSUSP
    • [12]USBRST (def=0x0) // USBRST
    • [13]ENUMDNE (def=0x0) // ENUMDNE
    • [14]ISOODRP (def=0x0) // ISOODRP
    • [15]EOPF (def=0x0) // EOPF
    • [18]IEPINT (def=0x0) // IEPINT
    • [19]OEPINT (def=0x0) // OEPINT
    • [20]IISOIXFR (def=0x0) // IISOIXFR
    • [21]IPXFR (def=0x0) // IPXFR
    • [23]RSTDET (def=0x0) // RSTDET
    • [24]HPRTINT (def=0x0) // HPRTINT
    • [25]HCINT (def=0x0) // HCINT
    • [26]PTXFE (def=0x1) // PTXFE
    • [27]LPMINT (def=0x0) // LPMINT
    • [28]CIDSCHG (def=0x0) // CIDSCHG
    • [29]DISCINT (def=0x0) // DISCINT
    • [30]SRQINT (def=0x0) // SRQINT
    • [31]WKUPINT (def=0x0) // WKUPINT
  • 0x42040018GINTMSK// This register works with the core interrupt register to interrupt the application. When an interrup

    • [1]MMISM (def=0x0) // MMISM
    • [2]OTGINT (def=0x0) // OTGINT
    • [3]SOFM (def=0x0) // SOFM
    • [4]RXFLVLM (def=0x0) // RXFLVLM
    • [5]NPTXFEM (def=0x0) // NPTXFEM
    • [6]GINAKEFFM (def=0x0) // GINAKEFFM
    • [7]GONAKEFFM (def=0x0) // GONAKEFFM
    • [10]ESUSPM (def=0x0) // ESUSPM
    • [11]USBSUSPM (def=0x0) // USBSUSPM
    • [12]USBRST (def=0x0) // USBRST
    • [13]ENUMDNEM (def=0x0) // ENUMDNEM
    • [14]ISOODRPM (def=0x0) // ISOODRPM
    • [15]EOPFM (def=0x0) // EOPFM
    • [18]IEPINT (def=0x0) // IEPINT
    • [19]OEPINT (def=0x0) // OEPINT
    • [20]IISOIXFRM (def=0x0) // IISOIXFRM
    • [21]IPXFRM (def=0x0) // IPXFRM
    • [23]RSTDETM (def=0x0) // RSTDETM
    • [24]PRTIM (def=0x0) // PRTIM
    • [25]HCIM (def=0x0) // HCIM
    • [26]PTXFEM (def=0x0) // PTXFEM
    • [27]LPMINTM (def=0x0) // LPMINTM
    • [28]CIDSCHGM (def=0x0) // CIDSCHGM
    • [29]DISCINT (def=0x0) // DISCINT
    • [30]SRQIM (def=0x0) // SRQIM
    • [31]WUIM (def=0x0) // WUIM
  • 0x4204001CGRXSTSR_DEVICE// This description is for register GRXSTSR in Device mode. A read to the receive status debug read re

    • [0:3]EPNUM (def=0x0) // EPNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
    • [21:24]FRMNUM (def=0x0) // FRMNUM
    • [27]STSPHST (def=0x0) // STSPHST
  • 0x4204001CGRXSTSR_HOST// This description is for register GRXSTSR in Host mode

    • [0:3]CHNUM (def=0x0) // CHNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
  • 0x42040020GRXSTSP_DEVICE// This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug

    • [0:3]EPNUM (def=0x0) // EPNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
    • [21:24]FRMNUM (def=0x0) // FRMNUM
    • [27]STSPHST (def=0x0) // STSPHST
  • 0x42040020GRXSTSP_HOST// This description is for register GRXSTSP in HOST mode

    • [0:3]CHNUM (def=0x0) // CHNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
  • 0x42040024GRXFSIZ// The application can program the RAM size that must be allocated to the Rx FIFO.

    • [0:15]RXFD (def=0x200) // RXFD
  • 0x42040028HNPTXFSIZ// Host mode

    • [0:15]NPTXFSA (def=0x200) // NPTXFSA
    • [16:31]NPTXFD (def=0x200) // NPTXFD
  • 0x4204002CHNPTXSTS// In device mode, this register is not valid. This read-only register contains the free space informa

    • [0:15]NPTXFSAV (def=0x200) // NPTXFSAV
    • [16:23]NPTQXSAV (def=0x8) // NPTQXSAV
    • [24:30]NPTXQTOP (def=0x0) // NPTXQTOP
  • 0x42040038GCCFG// OTG general core configuration register

    • [0]DCDET (def=0x0) // DCDET
    • [1]PDET (def=0x0) // PDET
    • [2]SDET (def=0x0) // SDET
    • [3]PS2DET (def=0x0) // PS2DET
    • [16]PWRDWN (def=0x0) // PWRDWN
    • [17]BCDEN (def=0x0) // BCDEN
    • [18]DCDEN (def=0x0) // DCDEN
    • [19]PDEN (def=0x0) // PDEN
    • [20]SDEN (def=0x0) // SDEN
    • [21]VBDEN (def=0x0) // VBDEN
  • 0x4204003CCID// This is a register containing the Product ID as reset value.

    • [0:31]PRODUCT_ID (def=0x3000) // PRODUCT_ID
  • 0x42040054GLPMCFG// OTG core LPM configuration register

    • [0]LPMEN (def=0x0) // LPMEN
    • [1]LPMACK (def=0x0) // LPMACK
    • [2:5]BESL (def=0x0) // BESL
    • [6]REMWAKE (def=0x0) // REMWAKE
    • [7]L1SSEN (def=0x0) // L1SSEN
    • [8:11]BESLTHRS (def=0x0) // BESLTHRS
    • [12]L1DSEN (def=0x0) // L1DSEN
    • [13:14]LPMRSP (def=0x0) // LPMRSP
    • [15]SLPSTS (def=0x0) // SLPSTS
    • [16]L1RSMOK (def=0x0) // L1RSMOK
    • [17:20]LPMCHIDX (def=0x0) // LPMCHIDX
    • [21:23]LPMRCNT (def=0x0) // LPMRCNT
    • [24]SNDLPM (def=0x0) // SNDLPM
    • [25:27]LPMRCNTSTS (def=0x0) // LPMRCNTSTS
    • [28]ENBESL (def=0x0) // ENBESL
  • 0x42040100HPTXFSIZ// OTG host periodic transmit FIFO size register

    • [0:15]PTXSA (def=0x400) // PTXSA
    • [16:31]PTXFSIZ (def=0x200) // PTXFSIZ
  • 0x42040104DIEPTXF1// OTG device IN endpoint transmit FIFO 1 size register

    • [0:15]INEPTXSA (def=0x400) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x42040108DIEPTXF2// OTG device IN endpoint transmit FIFO 2 size register

    • [0:15]INEPTXSA (def=0x600) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x4204010CDIEPTXF3// OTG device IN endpoint transmit FIFO 3 size register

    • [0:15]INEPTXSA (def=0x800) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x42040110DIEPTXF4// OTG device IN endpoint transmit FIFO 4 size register

    • [0:15]INEPTXSA (def=0xA00) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x42040114DIEPTXF5// OTG device IN endpoint transmit FIFO 5 size register

    • [0:15]INEPTXSA (def=0xC00) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x42040400HCFG// This register configures the core after power-on. Do not make changes to this register after initia

    • [0:1]FSLSPCS (def=0x0) // FSLSPCS
    • [2]FSLSS (def=0x0) // FSLSS
  • 0x42040404HFIR// This register stores the frame interval information for the current speed to which the OTG controll

    • [0:15]FRIVL (def=0xEA60) // FRIVL
    • [16]RLDCTRL (def=0x0) // RLDCTRL
  • 0x42040408HFNUM// This register indicates the current frame number. It also indicates the time remaining (in terms of

    • [0:15]FRNUM (def=0x3FFF) // FRNUM
    • [16:31]FTREM (def=0x0) // FTREM
  • 0x42040410HPTXSTS// This read-only register contains the free space information for the periodic Tx FIFO and the period

    • [0:15]PTXFSAVL (def=0x100) // PTXFSAVL
    • [16:23]PTXQSAV (def=0x8) // PTXQSAV
    • [24:31]PTXQTOP (def=0x0) // PTXQTOP
  • 0x42040414HAINT// When a significant event occurs on a channel, the host all channels interrupt register interrupts t

    • [0:15]HAINT (def=0x0) // HAINT
  • 0x42040418HAINTMSK// The host all channel interrupt mask register works with the host all channel interrupt register to

    • [0:15]HAINTM (def=0x0) // HAINTM
  • 0x42040440HPRT// This register is available only in host mode. Currently, the OTG host supports only one port. A sin

    • [0]PCSTS (def=0x0) // PCSTS
    • [1]PCDET (def=0x0) // PCDET
    • [2]PENA (def=0x0) // PENA
    • [3]PENCHNG (def=0x0) // PENCHNG
    • [4]POCA (def=0x0) // POCA
    • [5]POCCHNG (def=0x0) // POCCHNG
    • [6]PRES (def=0x0) // PRES
    • [7]PSUSP (def=0x0) // PSUSP
    • [8]PRST (def=0x0) // PRST
    • [10:11]PLSTS (def=0x0) // PLSTS
    • [12]PPWR (def=0x0) // PPWR
    • [13:16]PTCTL (def=0x0) // PTCTL
    • [17:18]PSPD (def=0x0) // PSPD
  • 0x42040500HCCHAR0// OTG host channel 0 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040508HCINT0// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204050CHCINTMSK0// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040510HCTSIZ0// OTG host channel 0 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040520HCCHAR1// OTG host channel 1 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040528HCINT1// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204052CHCINTMSK1// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040530HCTSIZ1// OTG host channel 1 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040540HCCHAR2// OTG host channel 2 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040548HCINT2// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204054CHCINTMSK2// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040550HCTSIZ2// OTG host channel 2 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040560HCCHAR3// OTG host channel 3 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040568HCINT3// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204056CHCINTMSK3// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040570HCTSIZ3// OTG host channel 3 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040580HCCHAR4// OTG host channel 4 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040588HCINT4// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204058CHCINTMSK4// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040590HCTSIZ4// OTG host channel 4 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x420405A0HCCHAR5// OTG host channel 5 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x420405A8HCINT5// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x420405ACHCINTMSK5// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x420405B0HCTSIZ5// OTG host channel 5 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x420405C0HCCHAR6// OTG host channel 6 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x420405C8HCINT6// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x420405CCHCINTMSK6// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x420405D0HCTSIZ6// OTG host channel 6 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x420405E0HCCHAR7// OTG host channel 7 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x420405E8HCINT7// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x420405ECHCINTMSK7// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x420405F0HCTSIZ7// OTG host channel 7 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040600HCCHAR8// OTG host channel 8 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040608HCINT8// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204060CHCINTMSK8// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040610HCTSIZ8// OTG host channel 8 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040620HCCHAR9// OTG host channel 9 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040628HCINT9// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204062CHCINTMSK9// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040630HCTSIZ9// OTG host channel 9 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040640HCCHAR10// OTG host channel 10 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040648HCINT10// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204064CHCINTMSK10// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040650HCTSIZ10// OTG host channel 10 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040660HCCHAR11// OTG host channel 11 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x42040668HCINT11// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x4204066CHCINTMSK11// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x42040670HCTSIZ11// OTG host channel 11 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x42040800DCFG// This register configures the core in device mode after power-on or after certain control commands o

    • [0:1]DSPD (def=0x0) // DSPD
    • [2]NZLSOHSK (def=0x0) // NZLSOHSK
    • [4:10]DAD (def=0x0) // DAD
    • [11:12]PFIVL (def=0x0) // PFIVL
    • [15]ERRATIM (def=0x0) // ERRATIM
  • 0x42040804DCTL// OTG device control register

    • [0]RWUSIG (def=0x0) // RWUSIG
    • [1]SDIS (def=0x1) // SDIS
    • [2]GINSTS (def=0x0) // GINSTS
    • [3]GONSTS (def=0x0) // GONSTS
    • [4:6]TCTL (def=0x0) // TCTL
    • [7]SGINAK (def=0x0) // SGINAK
    • [8]CGINAK (def=0x0) // CGINAK
    • [9]SGONAK (def=0x0) // SGONAK
    • [10]CGONAK (def=0x0) // CGONAK
    • [11]POPRGDNE (def=0x0) // POPRGDNE
    • [18]DSBESLRJCT (def=0x0) // DSBESLRJCT
  • 0x42040808DSTS// This register indicates the status of the core with respect to USB-related events. It must be read

    • [0]SUSPSTS (def=0x0) // SUSPSTS
    • [1:2]ENUMSPD (def=0x0) // ENUMSPD
    • [3]EERR (def=0x0) // EERR
    • [8:21]FNSOF (def=0x0) // FNSOF
    • [22:23]DEVLNSTS (def=0x0) // DEVLNSTS
  • 0x42040810DIEPMSK// This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]EPDM (def=0x0) // EPDM
    • [3]TOM (def=0x0) // TOM
    • [4]ITTXFEMSK (def=0x0) // ITTXFEMSK
    • [5]INEPNMM (def=0x0) // INEPNMM
    • [6]INEPNEM (def=0x0) // INEPNEM
    • [13]NAKM (def=0x0) // NAKM
  • 0x42040814DOEPMSK// This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]EPDM (def=0x0) // EPDM
    • [3]STUPM (def=0x0) // STUPM
    • [4]OTEPDM (def=0x0) // OTEPDM
    • [5]STSPHSRXM (def=0x0) // STSPHSRXM
    • [8]OUTPKTERRM (def=0x0) // OUTPKTERRM
    • [12]BERRM (def=0x0) // BERRM
    • [13]NAKMSK (def=0x0) // NAKMSK
  • 0x42040818DAINT// When a significant event occurs on an endpoint, a DAINT register interrupts the application using t

    • [0:15]IEPINT (def=0x0) // IEPINT
    • [16:31]OEPINT (def=0x0) // OEPINT
  • 0x4204081CDAINTMSK// The DAINTMSK register works with the device endpoint interrupt register to interrupt the applicatio

    • [0:15]IEPM (def=0x0) // IEPM
    • [16:31]OEPM (def=0x0) // OEPM
  • 0x42040828DVBUSDIS// This register specifies the VBUS discharge time after VBUS pulsing during SRP.

    • [0:15]VBUSDT (def=0x17D7) // VBUSDT
  • 0x4204082CDVBUSPULSE// This register specifies the VBUS pulsing time during SRP.

    • [0:15]DVBUSP (def=0x5B8) // DVBUSP
  • 0x42040834DIEPEMPMSK// This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).

    • [0:15]INEPTXFEM (def=0x0) // INEPTXFEM
  • 0x42040900DIEPCTL0// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:1]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040908DIEPINT0// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x42040910DIEPTSIZ0// The application must modify this register before enabling endpoint 0.

    • [0:6]XFRSIZ (def=0x0) // XFRSIZ
    • [19:20]PKTCNT (def=0x0) // PKTCNT
  • 0x42040918DTXFSTS0// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x42040920DIEPCTL1// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040928DIEPINT1// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x42040930DIEPTSIZ1// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x42040938DTXFSTS1// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x42040940DIEPCTL2// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040948DIEPINT2// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x42040950DIEPTSIZ2// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x42040958DTXFSTS2// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x42040960DIEPCTL3// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040968DIEPINT3// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x42040970DIEPTSIZ3// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x42040978DTXFSTS3// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x42040980DIEPCTL4// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040988DIEPINT4// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x42040990DIEPTSIZ4// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x42040998DTXFSTS4// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x420409A0DIEPCTL5// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x420409A8DIEPINT5// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x420409B0DIEPTSIZ5// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x420409B8DTXFSTS5// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x42040B00DOEPCTL0// This section describes the DOEPCTL0 register.

    • [0:1]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x1) // USBAEP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040B08DOEPINT0// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040B10DOEPTSIZ0// The application must modify this register before enabling endpoint 0.

    • [0:6]XFRSIZ (def=0x0) // XFRSIZ
    • [19]PKTCNT (def=0x0) // PKTCNT
    • [29:30]STUPCNT (def=0x0) // STUPCNT
  • 0x42040B20DOEPCTL1// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040B28DOEPINT1// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040B30DOEPTSIZ1// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x42040B40DOEPCTL2// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040B48DOEPINT2// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040B50DOEPTSIZ2// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x42040B60DOEPCTL3// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040B68DOEPINT3// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040B70DOEPTSIZ3// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x42040B80DOEPCTL4// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040B88DOEPINT4// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040B90DOEPTSIZ4// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x42040BA0DOEPCTL5// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x42040BA8DOEPINT5// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x42040BB0DOEPTSIZ5// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x42040E00PCGCCTL// This register is available in host and device modes.

    • [0]STPPCLK (def=0x0) // STPPCLK
    • [1]GATEHCLK (def=0x0) // GATEHCLK
    • [4]PHYSUSP (def=0x0) // PHYSUSP
    • [5]ENL1GTG (def=0x0) // ENL1GTG
    • [6]PHYSLEEP (def=0x0) // PHYSLEEP
    • [7]SUSP (def=0x0) // SUSP
  interrupts:
  • [59] OTG_FS // USB OTG FS global interrupt
• 0x52040000SEC_OTG_FS//

  • 0x52040000GOTGCTL// The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.

    • [0]SRQSCS (def=0x0) // SRQSCS
    • [1]SRQ (def=0x0) // SRQ
    • [2]VBVALOEN (def=0x0) // VBVALOEN
    • [3]VBVALOVAL (def=0x0) // VBVALOVAL
    • [4]AVALOEN (def=0x0) // AVALOEN
    • [5]AVALOVAL (def=0x0) // AVALOVAL
    • [6]BVALOEN (def=0x0) // BVALOEN
    • [7]BVALOVAL (def=0x0) // BVALOVAL
    • [8]HNGSCS (def=0x0) // HNGSCS
    • [9]HNPRQ (def=0x0) // HNPRQ
    • [10]HSHNPEN (def=0x0) // HSHNPEN
    • [11]DHNPEN (def=0x0) // DHNPEN
    • [12]EHEN (def=0x0) // EHEN
    • [16]CIDSTS (def=0x1) // CIDSTS
    • [17]DBCT (def=0x0) // DBCT
    • [18]ASVLD (def=0x0) // ASVLD
    • [19]BSVLD (def=0x0) // BSVLD
    • [20]OTGVER (def=0x0) // OTGVER
    • [21]CURMOD (def=0x0) // CURMOD
  • 0x52040004GOTGINT// The application reads this register whenever there is an OTG interrupt and clears the bits in this

    • [2]SEDET (def=0x0) // SEDET
    • [8]SRSSCHG (def=0x0) // SRSSCHG
    • [9]HNSSCHG (def=0x0) // HNSSCHG
    • [17]HNGDET (def=0x0) // HNGDET
    • [18]ADTOCHG (def=0x0) // ADTOCHG
    • [19]DBCDNE (def=0x0) // DBCDNE
  • 0x52040008GAHBCFG// This register can be used to configure the core after power-on or a change in mode. This register m

    • [0]GINTMSK (def=0x0) // GINTMSK
    • [7]TXFELVL (def=0x0) // TXFELVL
    • [8]PTXFELVL (def=0x0) // PTXFELVL
  • 0x5204000CGUSBCFG// This register can be used to configure the core after power-on or a changing to host mode or device

    • [0:2]TOCAL (def=0x0) // TOCAL
    • [6]PHYSEL (def=0x1) // PHYSEL
    • [8]SRPCAP (def=0x0) // SRPCAP
    • [9]HNPCAP (def=0x0) // HNPCAP
    • [10:13]TRDT (def=0x5) // TRDT
    • [29]FHMOD (def=0x0) // FHMOD
    • [30]FDMOD (def=0x0) // FDMOD
  • 0x52040010GRSTCTL// The application uses this register to reset various hardware features inside the core.

    • [0]CSRST (def=0x0) // CSRST
    • [1]PSRST (def=0x0) // PSRST
    • [2]FSRST (def=0x0) // FSRST
    • [4]RXFFLSH (def=0x0) // RXFFLSH
    • [5]TXFFLSH (def=0x0) // TXFFLSH
    • [6:10]TXFNUM (def=0x0) // TXFNUM
    • [31]AHBIDL (def=0x1) // AHBIDL
  • 0x52040014GINTSTS// This register interrupts the application for system-level events in the current mode (device mode o

    • [0]CMOD (def=0x0) // CMOD
    • [1]MMIS (def=0x0) // MMIS
    • [2]OTGINT (def=0x0) // OTGINT
    • [3]SOF (def=0x0) // SOF
    • [4]RXFLVL (def=0x0) // RXFLVL
    • [5]NPTXFE (def=0x1) // NPTXFE
    • [6]GINAKEFF (def=0x0) // GINAKEFF
    • [7]GONAKEFF (def=0x0) // GONAKEFF
    • [10]ESUSP (def=0x0) // ESUSP
    • [11]USBSUSP (def=0x0) // USBSUSP
    • [12]USBRST (def=0x0) // USBRST
    • [13]ENUMDNE (def=0x0) // ENUMDNE
    • [14]ISOODRP (def=0x0) // ISOODRP
    • [15]EOPF (def=0x0) // EOPF
    • [18]IEPINT (def=0x0) // IEPINT
    • [19]OEPINT (def=0x0) // OEPINT
    • [20]IISOIXFR (def=0x0) // IISOIXFR
    • [21]IPXFR (def=0x0) // IPXFR
    • [23]RSTDET (def=0x0) // RSTDET
    • [24]HPRTINT (def=0x0) // HPRTINT
    • [25]HCINT (def=0x0) // HCINT
    • [26]PTXFE (def=0x1) // PTXFE
    • [27]LPMINT (def=0x0) // LPMINT
    • [28]CIDSCHG (def=0x0) // CIDSCHG
    • [29]DISCINT (def=0x0) // DISCINT
    • [30]SRQINT (def=0x0) // SRQINT
    • [31]WKUPINT (def=0x0) // WKUPINT
  • 0x52040018GINTMSK// This register works with the core interrupt register to interrupt the application. When an interrup

    • [1]MMISM (def=0x0) // MMISM
    • [2]OTGINT (def=0x0) // OTGINT
    • [3]SOFM (def=0x0) // SOFM
    • [4]RXFLVLM (def=0x0) // RXFLVLM
    • [5]NPTXFEM (def=0x0) // NPTXFEM
    • [6]GINAKEFFM (def=0x0) // GINAKEFFM
    • [7]GONAKEFFM (def=0x0) // GONAKEFFM
    • [10]ESUSPM (def=0x0) // ESUSPM
    • [11]USBSUSPM (def=0x0) // USBSUSPM
    • [12]USBRST (def=0x0) // USBRST
    • [13]ENUMDNEM (def=0x0) // ENUMDNEM
    • [14]ISOODRPM (def=0x0) // ISOODRPM
    • [15]EOPFM (def=0x0) // EOPFM
    • [18]IEPINT (def=0x0) // IEPINT
    • [19]OEPINT (def=0x0) // OEPINT
    • [20]IISOIXFRM (def=0x0) // IISOIXFRM
    • [21]IPXFRM (def=0x0) // IPXFRM
    • [23]RSTDETM (def=0x0) // RSTDETM
    • [24]PRTIM (def=0x0) // PRTIM
    • [25]HCIM (def=0x0) // HCIM
    • [26]PTXFEM (def=0x0) // PTXFEM
    • [27]LPMINTM (def=0x0) // LPMINTM
    • [28]CIDSCHGM (def=0x0) // CIDSCHGM
    • [29]DISCINT (def=0x0) // DISCINT
    • [30]SRQIM (def=0x0) // SRQIM
    • [31]WUIM (def=0x0) // WUIM
  • 0x5204001CGRXSTSR_DEVICE// This description is for register GRXSTSR in Device mode. A read to the receive status debug read re

    • [0:3]EPNUM (def=0x0) // EPNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
    • [21:24]FRMNUM (def=0x0) // FRMNUM
    • [27]STSPHST (def=0x0) // STSPHST
  • 0x5204001CGRXSTSR_HOST// This description is for register GRXSTSR in Host mode

    • [0:3]CHNUM (def=0x0) // CHNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
  • 0x52040020GRXSTSP_DEVICE// This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug

    • [0:3]EPNUM (def=0x0) // EPNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
    • [21:24]FRMNUM (def=0x0) // FRMNUM
    • [27]STSPHST (def=0x0) // STSPHST
  • 0x52040020GRXSTSP_HOST// This description is for register GRXSTSP in HOST mode

    • [0:3]CHNUM (def=0x0) // CHNUM
    • [4:14]BCNT (def=0x0) // BCNT
    • [15:16]DPID (def=0x0) // DPID
    • [17:20]PKTSTS (def=0x0) // PKTSTS
  • 0x52040024GRXFSIZ// The application can program the RAM size that must be allocated to the Rx FIFO.

    • [0:15]RXFD (def=0x200) // RXFD
  • 0x52040028HNPTXFSIZ// Host mode

    • [0:15]NPTXFSA (def=0x200) // NPTXFSA
    • [16:31]NPTXFD (def=0x200) // NPTXFD
  • 0x5204002CHNPTXSTS// In device mode, this register is not valid. This read-only register contains the free space informa

    • [0:15]NPTXFSAV (def=0x200) // NPTXFSAV
    • [16:23]NPTQXSAV (def=0x8) // NPTQXSAV
    • [24:30]NPTXQTOP (def=0x0) // NPTXQTOP
  • 0x52040038GCCFG// OTG general core configuration register

    • [0]DCDET (def=0x0) // DCDET
    • [1]PDET (def=0x0) // PDET
    • [2]SDET (def=0x0) // SDET
    • [3]PS2DET (def=0x0) // PS2DET
    • [16]PWRDWN (def=0x0) // PWRDWN
    • [17]BCDEN (def=0x0) // BCDEN
    • [18]DCDEN (def=0x0) // DCDEN
    • [19]PDEN (def=0x0) // PDEN
    • [20]SDEN (def=0x0) // SDEN
    • [21]VBDEN (def=0x0) // VBDEN
  • 0x5204003CCID// This is a register containing the Product ID as reset value.

    • [0:31]PRODUCT_ID (def=0x3000) // PRODUCT_ID
  • 0x52040054GLPMCFG// OTG core LPM configuration register

    • [0]LPMEN (def=0x0) // LPMEN
    • [1]LPMACK (def=0x0) // LPMACK
    • [2:5]BESL (def=0x0) // BESL
    • [6]REMWAKE (def=0x0) // REMWAKE
    • [7]L1SSEN (def=0x0) // L1SSEN
    • [8:11]BESLTHRS (def=0x0) // BESLTHRS
    • [12]L1DSEN (def=0x0) // L1DSEN
    • [13:14]LPMRSP (def=0x0) // LPMRSP
    • [15]SLPSTS (def=0x0) // SLPSTS
    • [16]L1RSMOK (def=0x0) // L1RSMOK
    • [17:20]LPMCHIDX (def=0x0) // LPMCHIDX
    • [21:23]LPMRCNT (def=0x0) // LPMRCNT
    • [24]SNDLPM (def=0x0) // SNDLPM
    • [25:27]LPMRCNTSTS (def=0x0) // LPMRCNTSTS
    • [28]ENBESL (def=0x0) // ENBESL
  • 0x52040100HPTXFSIZ// OTG host periodic transmit FIFO size register

    • [0:15]PTXSA (def=0x400) // PTXSA
    • [16:31]PTXFSIZ (def=0x200) // PTXFSIZ
  • 0x52040104DIEPTXF1// OTG device IN endpoint transmit FIFO 1 size register

    • [0:15]INEPTXSA (def=0x400) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x52040108DIEPTXF2// OTG device IN endpoint transmit FIFO 2 size register

    • [0:15]INEPTXSA (def=0x600) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x5204010CDIEPTXF3// OTG device IN endpoint transmit FIFO 3 size register

    • [0:15]INEPTXSA (def=0x800) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x52040110DIEPTXF4// OTG device IN endpoint transmit FIFO 4 size register

    • [0:15]INEPTXSA (def=0xA00) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x52040114DIEPTXF5// OTG device IN endpoint transmit FIFO 5 size register

    • [0:15]INEPTXSA (def=0xC00) // INEPTXSA
    • [16:31]INEPTXFD (def=0x200) // INEPTXFD
  • 0x52040400HCFG// This register configures the core after power-on. Do not make changes to this register after initia

    • [0:1]FSLSPCS (def=0x0) // FSLSPCS
    • [2]FSLSS (def=0x0) // FSLSS
  • 0x52040404HFIR// This register stores the frame interval information for the current speed to which the OTG controll

    • [0:15]FRIVL (def=0xEA60) // FRIVL
    • [16]RLDCTRL (def=0x0) // RLDCTRL
  • 0x52040408HFNUM// This register indicates the current frame number. It also indicates the time remaining (in terms of

    • [0:15]FRNUM (def=0x3FFF) // FRNUM
    • [16:31]FTREM (def=0x0) // FTREM
  • 0x52040410HPTXSTS// This read-only register contains the free space information for the periodic Tx FIFO and the period

    • [0:15]PTXFSAVL (def=0x100) // PTXFSAVL
    • [16:23]PTXQSAV (def=0x8) // PTXQSAV
    • [24:31]PTXQTOP (def=0x0) // PTXQTOP
  • 0x52040414HAINT// When a significant event occurs on a channel, the host all channels interrupt register interrupts t

    • [0:15]HAINT (def=0x0) // HAINT
  • 0x52040418HAINTMSK// The host all channel interrupt mask register works with the host all channel interrupt register to

    • [0:15]HAINTM (def=0x0) // HAINTM
  • 0x52040440HPRT// This register is available only in host mode. Currently, the OTG host supports only one port. A sin

    • [0]PCSTS (def=0x0) // PCSTS
    • [1]PCDET (def=0x0) // PCDET
    • [2]PENA (def=0x0) // PENA
    • [3]PENCHNG (def=0x0) // PENCHNG
    • [4]POCA (def=0x0) // POCA
    • [5]POCCHNG (def=0x0) // POCCHNG
    • [6]PRES (def=0x0) // PRES
    • [7]PSUSP (def=0x0) // PSUSP
    • [8]PRST (def=0x0) // PRST
    • [10:11]PLSTS (def=0x0) // PLSTS
    • [12]PPWR (def=0x0) // PPWR
    • [13:16]PTCTL (def=0x0) // PTCTL
    • [17:18]PSPD (def=0x0) // PSPD
  • 0x52040500HCCHAR0// OTG host channel 0 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040508HCINT0// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204050CHCINTMSK0// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040510HCTSIZ0// OTG host channel 0 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040520HCCHAR1// OTG host channel 1 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040528HCINT1// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204052CHCINTMSK1// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040530HCTSIZ1// OTG host channel 1 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040540HCCHAR2// OTG host channel 2 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040548HCINT2// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204054CHCINTMSK2// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040550HCTSIZ2// OTG host channel 2 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040560HCCHAR3// OTG host channel 3 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040568HCINT3// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204056CHCINTMSK3// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040570HCTSIZ3// OTG host channel 3 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040580HCCHAR4// OTG host channel 4 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040588HCINT4// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204058CHCINTMSK4// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040590HCTSIZ4// OTG host channel 4 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x520405A0HCCHAR5// OTG host channel 5 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x520405A8HCINT5// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x520405ACHCINTMSK5// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x520405B0HCTSIZ5// OTG host channel 5 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x520405C0HCCHAR6// OTG host channel 6 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x520405C8HCINT6// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x520405CCHCINTMSK6// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x520405D0HCTSIZ6// OTG host channel 6 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x520405E0HCCHAR7// OTG host channel 7 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x520405E8HCINT7// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x520405ECHCINTMSK7// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x520405F0HCTSIZ7// OTG host channel 7 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040600HCCHAR8// OTG host channel 8 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040608HCINT8// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204060CHCINTMSK8// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040610HCTSIZ8// OTG host channel 8 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040620HCCHAR9// OTG host channel 9 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040628HCINT9// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204062CHCINTMSK9// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040630HCTSIZ9// OTG host channel 9 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040640HCCHAR10// OTG host channel 10 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040648HCINT10// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204064CHCINTMSK10// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040650HCTSIZ10// OTG host channel 10 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040660HCCHAR11// OTG host channel 11 characteristics register

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [11:14]EPNUM (def=0x0) // EPNUM
    • [15]EPDIR (def=0x0) // EPDIR
    • [17]LSDEV (def=0x0) // LSDEV
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20:21]MCNT (def=0x0) // MCNT
    • [22:28]DAD (def=0x0) // DAD
    • [29]ODDFRM (def=0x0) // ODDFRM
    • [30]CHDIS (def=0x0) // CHDIS
    • [31]CHENA (def=0x0) // CHENA
  • 0x52040668HCINT11// This register indicates the status of a channel with respect to USB- and AHB-related events. It is

    • [0]XFRC (def=0x0) // XFRC
    • [1]CHH (def=0x0) // CHH
    • [3]STALL (def=0x0) // STALL
    • [4]NAK (def=0x0) // NAK
    • [5]ACK (def=0x0) // ACK
    • [7]TXERR (def=0x0) // TXERR
    • [8]BBERR (def=0x0) // BBERR
    • [9]FRMOR (def=0x0) // FRMOR
    • [10]DTERR (def=0x0) // DTERR
  • 0x5204066CHCINTMSK11// This register reflects the mask for each channel status described in the previous section.

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]CHHM (def=0x0) // CHHM
    • [3]STALLM (def=0x0) // STALLM
    • [4]NAKM (def=0x0) // NAKM
    • [5]ACKM (def=0x0) // ACKM
    • [7]TXERRM (def=0x0) // TXERRM
    • [8]BBERRM (def=0x0) // BBERRM
    • [9]FRMORM (def=0x0) // FRMORM
    • [10]DTERRM (def=0x0) // DTERRM
  • 0x52040670HCTSIZ11// OTG host channel 11 transfer size register

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]DPID (def=0x0) // DPID
    • [31]DOPNG (def=0x0) // DOPNG
  • 0x52040800DCFG// This register configures the core in device mode after power-on or after certain control commands o

    • [0:1]DSPD (def=0x0) // DSPD
    • [2]NZLSOHSK (def=0x0) // NZLSOHSK
    • [4:10]DAD (def=0x0) // DAD
    • [11:12]PFIVL (def=0x0) // PFIVL
    • [15]ERRATIM (def=0x0) // ERRATIM
  • 0x52040804DCTL// OTG device control register

    • [0]RWUSIG (def=0x0) // RWUSIG
    • [1]SDIS (def=0x1) // SDIS
    • [2]GINSTS (def=0x0) // GINSTS
    • [3]GONSTS (def=0x0) // GONSTS
    • [4:6]TCTL (def=0x0) // TCTL
    • [7]SGINAK (def=0x0) // SGINAK
    • [8]CGINAK (def=0x0) // CGINAK
    • [9]SGONAK (def=0x0) // SGONAK
    • [10]CGONAK (def=0x0) // CGONAK
    • [11]POPRGDNE (def=0x0) // POPRGDNE
    • [18]DSBESLRJCT (def=0x0) // DSBESLRJCT
  • 0x52040808DSTS// This register indicates the status of the core with respect to USB-related events. It must be read

    • [0]SUSPSTS (def=0x0) // SUSPSTS
    • [1:2]ENUMSPD (def=0x0) // ENUMSPD
    • [3]EERR (def=0x0) // EERR
    • [8:21]FNSOF (def=0x0) // FNSOF
    • [22:23]DEVLNSTS (def=0x0) // DEVLNSTS
  • 0x52040810DIEPMSK// This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]EPDM (def=0x0) // EPDM
    • [3]TOM (def=0x0) // TOM
    • [4]ITTXFEMSK (def=0x0) // ITTXFEMSK
    • [5]INEPNMM (def=0x0) // INEPNMM
    • [6]INEPNEM (def=0x0) // INEPNEM
    • [13]NAKM (def=0x0) // NAKM
  • 0x52040814DOEPMSK// This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt

    • [0]XFRCM (def=0x0) // XFRCM
    • [1]EPDM (def=0x0) // EPDM
    • [3]STUPM (def=0x0) // STUPM
    • [4]OTEPDM (def=0x0) // OTEPDM
    • [5]STSPHSRXM (def=0x0) // STSPHSRXM
    • [8]OUTPKTERRM (def=0x0) // OUTPKTERRM
    • [12]BERRM (def=0x0) // BERRM
    • [13]NAKMSK (def=0x0) // NAKMSK
  • 0x52040818DAINT// When a significant event occurs on an endpoint, a DAINT register interrupts the application using t

    • [0:15]IEPINT (def=0x0) // IEPINT
    • [16:31]OEPINT (def=0x0) // OEPINT
  • 0x5204081CDAINTMSK// The DAINTMSK register works with the device endpoint interrupt register to interrupt the applicatio

    • [0:15]IEPM (def=0x0) // IEPM
    • [16:31]OEPM (def=0x0) // OEPM
  • 0x52040828DVBUSDIS// This register specifies the VBUS discharge time after VBUS pulsing during SRP.

    • [0:15]VBUSDT (def=0x17D7) // VBUSDT
  • 0x5204082CDVBUSPULSE// This register specifies the VBUS pulsing time during SRP.

    • [0:15]DVBUSP (def=0x5B8) // DVBUSP
  • 0x52040834DIEPEMPMSK// This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).

    • [0:15]INEPTXFEM (def=0x0) // INEPTXFEM
  • 0x52040900DIEPCTL0// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:1]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040908DIEPINT0// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x52040910DIEPTSIZ0// The application must modify this register before enabling endpoint 0.

    • [0:6]XFRSIZ (def=0x0) // XFRSIZ
    • [19:20]PKTCNT (def=0x0) // PKTCNT
  • 0x52040918DTXFSTS0// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x52040920DIEPCTL1// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040928DIEPINT1// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x52040930DIEPTSIZ1// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x52040938DTXFSTS1// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x52040940DIEPCTL2// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040948DIEPINT2// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x52040950DIEPTSIZ2// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x52040958DTXFSTS2// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x52040960DIEPCTL3// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040968DIEPINT3// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x52040970DIEPTSIZ3// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x52040978DTXFSTS3// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x52040980DIEPCTL4// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040988DIEPINT4// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x52040990DIEPTSIZ4// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x52040998DTXFSTS4// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x520409A0DIEPCTL5// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [21]STALL (def=0x0) // STALL
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x520409A8DIEPINT5// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [3]TOC (def=0x0) // TOC
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [5]INEPNM (def=0x0) // INEPNM
    • [6]INEPNE (def=0x0) // INEPNE
    • [7]TXFE (def=0x1) // TXFE
    • [11]PKTDRPSTS (def=0x0) // PKTDRPSTS
    • [13]NAK (def=0x0) // NAK
  • 0x520409B0DIEPTSIZ5// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]MCNT (def=0x0) // MCNT
  • 0x520409B8DTXFSTS5// This read-only register contains the free space information for the device IN endpoint Tx FIFO.

    • [0:15]INEPTFSAV (def=0x200) // INEPTFSAV
  • 0x52040B00DOEPCTL0// This section describes the DOEPCTL0 register.

    • [0:1]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x1) // USBAEP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040B08DOEPINT0// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040B10DOEPTSIZ0// The application must modify this register before enabling endpoint 0.

    • [0:6]XFRSIZ (def=0x0) // XFRSIZ
    • [19]PKTCNT (def=0x0) // PKTCNT
    • [29:30]STUPCNT (def=0x0) // STUPCNT
  • 0x52040B20DOEPCTL1// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040B28DOEPINT1// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040B30DOEPTSIZ1// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x52040B40DOEPCTL2// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040B48DOEPINT2// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040B50DOEPTSIZ2// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x52040B60DOEPCTL3// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040B68DOEPINT3// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040B70DOEPTSIZ3// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x52040B80DOEPCTL4// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040B88DOEPINT4// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040B90DOEPTSIZ4// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x52040BA0DOEPCTL5// The application uses this register to control the behavior of each logical endpoint other than endp

    • [0:10]MPSIZ (def=0x0) // MPSIZ
    • [15]USBAEP (def=0x0) // USBAEP
    • [16]EONUM_DPIP (def=0x0) // EONUM_DPIP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [20]SNPM (def=0x0) // SNPM
    • [21]STALL (def=0x0) // STALL
    • [26]CNAK (def=0x0) // CNAK
    • [27]SNAK (def=0x0) // SNAK
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID_SEVNFRM
    • [29]SD1PID_SODDFRM (def=0x0) // SD1PID_SODDFRM
    • [30]EPDIS (def=0x0) // EPDIS
    • [31]EPENA (def=0x0) // EPENA
  • 0x52040BA8DOEPINT5// This register indicates the status of an endpoint with respect to USB- and AHB-related events. It i

    • [0]XFRC (def=0x0) // XFRC
    • [1]EPDISD (def=0x0) // EPDISD
    • [2]AHBERR (def=0x0) // AHBERR
    • [3]STUP (def=0x0) // STUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [5]STSPHSRX (def=0x0) // STSPHSRX
    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [8]OUTPKTERR (def=0x0) // OUTPKTERR
    • [9]BNA (def=0x0) // BNA
    • [12]BERR (def=0x0) // BERR
    • [13]NAK (def=0x0) // NAK
    • [14]NYET (def=0x0) // NYET
    • [15]STPKTRX (def=0x0) // STPKTRX
  • 0x52040BB0DOEPTSIZ5// The application must modify this register before enabling the endpoint. Once the endpoint is enable

    • [0:18]XFRSIZ (def=0x0) // XFRSIZ
    • [19:28]PKTCNT (def=0x0) // PKTCNT
    • [29:30]RXDPID_STUPCNT (def=0x0) // RXDPID_STUPCNT
  • 0x52040E00PCGCCTL// This register is available in host and device modes.

    • [0]STPPCLK (def=0x0) // STPPCLK
    • [1]GATEHCLK (def=0x0) // GATEHCLK
    • [4]PHYSUSP (def=0x0) // PHYSUSP
    • [5]ENL1GTG (def=0x0) // ENL1GTG
    • [6]PHYSLEEP (def=0x0) // PHYSLEEP
    • [7]SUSP (def=0x0) // SUSP
• 0x4202C400PSSI// PSSI

  • 0x4202C400CR// PSSI control register

    • [5]CKPOL (def=0x0) // Parallel data clock polarity This bit configures the capture edge of the parallel clock or the ed
    • [6]DEPOL (def=0x0) // Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are
    • [8]RDYPOL (def=0x0) // Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not
    • [10:11]EDM (def=0x0) // Extended data mode
    • [14]ENABLE (def=0x0) // PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE
    • [18:20]DERDYCFG (def=0x0) // Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (sett
    • [30]DMAEN (def=0x1) // DMA enable bit
    • [31]OUTEN (def=0x0) // Data direction selection bit
  • 0x4202C404SR// PSSI status register

    • [2]RTT4B (def=0x0) // RTT4B
    • [3]RTT1B (def=0x0) // RTT1B
  • 0x4202C408RIS// PSSI raw interrupt status register

    • [1]OVR_RIS (def=0x0) // OVR_RIS
  • 0x4202C40CIER// PSSI interrupt enable register

    • [1]OVR_IE (def=0x0) // OVR_IE
  • 0x4202C410MIS// PSSI masked interrupt status register

    • [1]OVR_MIS (def=0x0) // OVR_MIS
  • 0x4202C414ICR// PSSI interrupt clear register

    • [1]OVR_ISC (def=0x0) // OVR_ISC
  • 0x4202C428DR// PSSI data register

    • [0:7]BYTE0 (def=0x0) // Data byte 0
    • [8:15]BYTE1 (def=0x0) // Data byte 1
    • [16:23]BYTE2 (def=0x0) // Data byte 2
    • [24:31]BYTE3 (def=0xC0) // Data byte 3
• 0x5202C400SEC_PSSI//

  • 0x5202C400CR// PSSI control register

    • [5]CKPOL (def=0x0) // Parallel data clock polarity This bit configures the capture edge of the parallel clock or the ed
    • [6]DEPOL (def=0x0) // Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are
    • [8]RDYPOL (def=0x0) // Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not
    • [10:11]EDM (def=0x0) // Extended data mode
    • [14]ENABLE (def=0x0) // PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE
    • [18:20]DERDYCFG (def=0x0) // Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (sett
    • [30]DMAEN (def=0x1) // DMA enable bit
    • [31]OUTEN (def=0x0) // Data direction selection bit
  • 0x5202C404SR// PSSI status register

    • [2]RTT4B (def=0x0) // RTT4B
    • [3]RTT1B (def=0x0) // RTT1B
  • 0x5202C408RIS// PSSI raw interrupt status register

    • [1]OVR_RIS (def=0x0) // OVR_RIS
  • 0x5202C40CIER// PSSI interrupt enable register

    • [1]OVR_IE (def=0x0) // OVR_IE
  • 0x5202C410MIS// PSSI masked interrupt status register

    • [1]OVR_MIS (def=0x0) // OVR_MIS
  • 0x5202C414ICR// PSSI interrupt clear register

    • [1]OVR_ISC (def=0x0) // OVR_ISC
  • 0x5202C428DR// PSSI data register

    • [0:7]BYTE0 (def=0x0) // Data byte 0
    • [8:15]BYTE1 (def=0x0) // Data byte 1
    • [16:23]BYTE2 (def=0x0) // Data byte 2
    • [24:31]BYTE3 (def=0xC0) // Data byte 3
• 0x420C5000OTFDEC1// On-The-Fly Decryption engine

  • 0x420C5000CR// OTFDEC control register

    • [0]ENC (def=0x0) // Encryption mode bit
  • 0x420C5010PRIVCFGR// OTFDEC privileged access control configuration register

    • [0]PRIV (def=0x0) // Encryption mode bit
  • 0x420C5020R1CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5050R2CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5080R3CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C50B0R4CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5024R1STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5054R2STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5084R3STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C50B4R4STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5028R1ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C5058R2ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C5088R3ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C508CR4ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C502CR1NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C505CR2NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C508CR3NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C50BCR4NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C5030R1NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce
  • 0x420C5060R2NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce, bits [63:32]REGx_NONCE[63:32]
  • 0x420C5090R3NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C50C0R4NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C5034R1KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5064R2KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5094R3KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C50C4R4KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5038R1KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5068R2KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5098R3KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C50C8R4KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C503CR1KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C506CR2KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY_ (def=0x0) // REGx_KEY
  • 0x420C509CR3KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C50CCR4KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5040R1KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5070R2KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C50A0R3KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C50D0R4KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5300ISR// OTFDEC interrupt status register

    • [0]SEIF (def=0x0) // Security Error Interrupt Flag status
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag status
    • [2]KEIF (def=0x0) // Key Error Interrupt Flag status
  • 0x420C5304ICR// OTFDEC interrupt clear register

    • [0]SEIF (def=0x0) // SEIF
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag clear
    • [2]KEIF (def=0x0) // KEIF
  • 0x420C5308IER// OTFDEC interrupt enable register

    • [0]SEIE (def=0x0) // Security Error Interrupt Enable
    • [1]XONEIE (def=0x0) // XONEIE
    • [2]KEIE (def=0x0) // KEIE
  interrupts:
  • [108] OTFDEC1 // OTFDEC1 interrupt
• 0x520C5000SEC_OTFDEC1//

  • 0x520C5000CR// OTFDEC control register

    • [0]ENC (def=0x0) // Encryption mode bit
  • 0x520C5010PRIVCFGR// OTFDEC privileged access control configuration register

    • [0]PRIV (def=0x0) // Encryption mode bit
  • 0x520C5020R1CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5050R2CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5080R3CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C50B0R4CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5024R1STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5054R2STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5084R3STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C50B4R4STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5028R1ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C5058R2ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C5088R3ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C508CR4ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C502CR1NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C505CR2NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C508CR3NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C50BCR4NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C5030R1NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce
  • 0x520C5060R2NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce, bits [63:32]REGx_NONCE[63:32]
  • 0x520C5090R3NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C50C0R4NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C5034R1KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5064R2KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5094R3KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C50C4R4KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5038R1KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5068R2KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5098R3KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C50C8R4KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C503CR1KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C506CR2KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY_ (def=0x0) // REGx_KEY
  • 0x520C509CR3KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C50CCR4KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5040R1KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5070R2KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C50A0R3KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C50D0R4KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5300ISR// OTFDEC interrupt status register

    • [0]SEIF (def=0x0) // Security Error Interrupt Flag status
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag status
    • [2]KEIF (def=0x0) // Key Error Interrupt Flag status
  • 0x520C5304ICR// OTFDEC interrupt clear register

    • [0]SEIF (def=0x0) // SEIF
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag clear
    • [2]KEIF (def=0x0) // KEIF
  • 0x520C5308IER// OTFDEC interrupt enable register

    • [0]SEIE (def=0x0) // Security Error Interrupt Enable
    • [1]XONEIE (def=0x0) // XONEIE
    • [2]KEIE (def=0x0) // KEIE
• 0x420C5400OTFDEC2//

  • 0x420C5400CR// OTFDEC control register

    • [0]ENC (def=0x0) // Encryption mode bit
  • 0x420C5410PRIVCFGR// OTFDEC privileged access control configuration register

    • [0]PRIV (def=0x0) // Encryption mode bit
  • 0x420C5420R1CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5450R2CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5480R3CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C54B0R4CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x420C5424R1STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5454R2STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5484R3STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C54B4R4STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x420C5428R1ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C5458R2ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C5488R3ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C548CR4ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x420C542CR1NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C545CR2NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C548CR3NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C54BCR4NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C5430R1NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce
  • 0x420C5460R2NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce, bits [63:32]REGx_NONCE[63:32]
  • 0x420C5490R3NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C54C0R4NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x420C5434R1KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5464R2KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5494R3KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C54C4R4KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5438R1KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5468R2KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5498R3KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C54C8R4KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C543CR1KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C546CR2KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY_ (def=0x0) // REGx_KEY
  • 0x420C549CR3KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C54CCR4KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5440R1KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5470R2KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C54A0R3KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C54D0R4KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x420C5700ISR// OTFDEC interrupt status register

    • [0]SEIF (def=0x0) // Security Error Interrupt Flag status
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag status
    • [2]KEIF (def=0x0) // Key Error Interrupt Flag status
  • 0x420C5704ICR// OTFDEC interrupt clear register

    • [0]SEIF (def=0x0) // SEIF
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag clear
    • [2]KEIF (def=0x0) // KEIF
  • 0x420C5708IER// OTFDEC interrupt enable register

    • [0]SEIE (def=0x0) // Security Error Interrupt Enable
    • [1]XONEIE (def=0x0) // XONEIE
    • [2]KEIE (def=0x0) // KEIE
  interrupts:
  • [109] OTFDEC2 // OTFDEC2 interrupt
• 0x520C5400SEC_OTFDEC2//

  • 0x520C5400CR// OTFDEC control register

    • [0]ENC (def=0x0) // Encryption mode bit
  • 0x520C5410PRIVCFGR// OTFDEC privileged access control configuration register

    • [0]PRIV (def=0x0) // Encryption mode bit
  • 0x520C5420R1CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5450R2CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5480R3CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C54B0R4CFGR// OTFDEC region x configuration register

    • [0]REG_EN (def=0x0) // region on-the-fly decryption enable
    • [1]CONFIGLOCK (def=0x0) // region config lock
    • [2]KEYLOCK (def=0x0) // region key lock
    • [4:5]MODE (def=0x0) // operating mode
    • [8:15]KEYCRC (def=0x0) // region key 8-bit CRC
    • [16:31]REGx_VERSION (def=0x0) // region firmware version
  • 0x520C5424R1STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5454R2STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5484R3STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C54B4R4STARTADDR// OTFDEC region x start address register

    • [0:31]REGx_START_ADDR (def=0x0) // Region AXI start address
  • 0x520C5428R1ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C5458R2ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C5488R3ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C548CR4ENDADDR// OTFDEC region x end address register

    • [0:31]REGx_END_ADDR (def=0xFFF) // Region AXI end address
  • 0x520C542CR1NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C545CR2NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C548CR3NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C54BCR4NONCER0// OTFDEC region x nonce register 0

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C5430R1NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce
  • 0x520C5460R2NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // Region nonce, bits [63:32]REGx_NONCE[63:32]
  • 0x520C5490R3NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C54C0R4NONCER1// OTFDEC region x nonce register 1

    • [0:31]REGx_NONCE (def=0x0) // REGx_NONCE
  • 0x520C5434R1KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5464R2KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5494R3KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C54C4R4KEYR0// OTFDEC region x key register 0

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5438R1KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5468R2KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5498R3KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C54C8R4KEYR1// OTFDEC region x key register 1

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C543CR1KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C546CR2KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY_ (def=0x0) // REGx_KEY
  • 0x520C549CR3KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C54CCR4KEYR2// OTFDEC region x key register 2

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5440R1KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5470R2KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C54A0R3KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C54D0R4KEYR3// OTFDEC region x key register 3

    • [0:31]REGx_KEY (def=0x0) // REGx_KEY
  • 0x520C5700ISR// OTFDEC interrupt status register

    • [0]SEIF (def=0x0) // Security Error Interrupt Flag status
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag status
    • [2]KEIF (def=0x0) // Key Error Interrupt Flag status
  • 0x520C5704ICR// OTFDEC interrupt clear register

    • [0]SEIF (def=0x0) // SEIF
    • [1]XONEIF (def=0x0) // Execute-only execute-Never Error Interrupt Flag clear
    • [2]KEIF (def=0x0) // KEIF
  • 0x520C5708IER// OTFDEC interrupt enable register

    • [0]SEIE (def=0x0) // Security Error Interrupt Enable
    • [1]XONEIE (def=0x0) // XONEIE
    • [2]KEIE (def=0x0) // KEIE
• 0x4002B000DMA2D// DMA2D controller

  • 0x4002B000CR// control register

    • [16:17]MODE (def=0x0) // DMA2D mode
    • [13]CEIE (def=0x0) // Configuration Error Interrupt Enable
    • [12]CTCIE (def=0x0) // CLUT transfer complete interrupt enable
    • [11]CAEIE (def=0x0) // CLUT access error interrupt enable
    • [10]TWIE (def=0x0) // Transfer watermark interrupt enable
    • [9]TCIE (def=0x0) // Transfer complete interrupt enable
    • [8]TEIE (def=0x0) // Transfer error interrupt enable
    • [6]LOM (def=0x0) // Line Offset Mode
    • [2]ABORT (def=0x0) // Abort
    • [1]SUSP (def=0x0) // Suspend
    • [0]START (def=0x0) // Start
  • 0x4002B004ISR// Interrupt Status Register

    • [5]CEIF (def=0x0) // Configuration error interrupt flag
    • [4]CTCIF (def=0x0) // CLUT transfer complete interrupt flag
    • [3]CAEIF (def=0x0) // CLUT access error interrupt flag
    • [2]TWIF (def=0x0) // Transfer watermark interrupt flag
    • [1]TCIF (def=0x0) // Transfer complete interrupt flag
    • [0]TEIF (def=0x0) // Transfer error interrupt flag
  • 0x4002B008IFCR// interrupt flag clear register

    • [5]CCEIF (def=0x0) // Clear configuration error interrupt flag
    • [4]CCTCIF (def=0x0) // Clear CLUT transfer complete interrupt flag
    • [3]CAECIF (def=0x0) // Clear CLUT access error interrupt flag
    • [2]CTWIF (def=0x0) // Clear transfer watermark interrupt flag
    • [1]CTCIF (def=0x0) // Clear transfer complete interrupt flag
    • [0]CTEIF (def=0x0) // Clear Transfer error interrupt flag
  • 0x4002B00CFGMAR// foreground memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002B010FGOR// foreground offset register

    • [0:15]LO (def=0x0) // Line offset
  • 0x4002B014BGMAR// background memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002B018BGOR// background offset register

    • [0:15]LO (def=0x0) // Line offset
  • 0x4002B01CFGPFCCR// foreground PFC control register

    • [24:31]ALPHA (def=0x0) // Alpha value
    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [16:17]AM (def=0x0) // Alpha mode
    • [8:15]CS (def=0x0) // CLUT size
    • [5]START (def=0x0) // Start
    • [4]CCM (def=0x0) // CLUT color mode
    • [0:3]CM (def=0x0) // Color mode
  • 0x4002B020FGCOLR// foreground color register

    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x4002B024BGPFCCR// background PFC control register

    • [24:31]ALPHA (def=0x0) // Alpha value
    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [16:17]AM (def=0x0) // Alpha mode
    • [8:15]CS (def=0x0) // CLUT size
    • [5]START (def=0x0) // Start
    • [4]CCM (def=0x0) // CLUT Color mode
    • [0:3]CM (def=0x0) // Color mode
  • 0x4002B028BGCOLR// background color register

    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x4002B02CFGCMAR// foreground CLUT memory address register

    • [0:31]MA (def=0x0) // Memory Address
  • 0x4002B030BGCMAR// background CLUT memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002B034OPFCCR// output PFC control register

    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [9]SB (def=0x0) // Swap Bytes
    • [0:2]CM (def=0x0) // Color mode
  • 0x4002B038OCOLR_RGB888// output color register

    • [24:31]APLHA (def=0x0) // Alpha Channel Value
    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x4002B038OCOLR_RGB565// output color register

    • [11:15]RED (def=0x0) // Red value in RGB565 mode
    • [5:10]GREEN (def=0x0) // Green value in RGB565 mode
    • [0:4]BLUE (def=0x0) // Blue value in RGB565 mode
  • 0x4002B038OCOLR_ARGB1555// output color register

    • [15]A (def=0x0) // Alpha channel value in ARGB1555 mode
    • [10:14]RED (def=0x0) // Red value in ARGB1555 mode
    • [5:9]GREEN (def=0x0) // Green value in ARGB1555 mode
    • [0:4]BLUE (def=0x0) // Blue value in ARGB1555 mode
  • 0x4002B038OCOLR_ARGB4444// output color register

    • [12:15]ALPHA (def=0x0) // Alpha channel value in ARGB4444
    • [8:11]RED (def=0x0) // Red value in ARGB4444 mode
    • [4:7]GREEN (def=0x0) // Green value in ARGB4444 mode
    • [0:3]BLUE (def=0x0) // Blue value in ARGB4444 mode
  • 0x4002B03COMAR// output memory address register

    • [0:31]MA (def=0x0) // Memory Address
  • 0x4002B040OOR// output offset register

    • [0:15]LO (def=0x0) // Line Offset
  • 0x4002B044NLR// number of line register

    • [16:29]PL (def=0x0) // Pixel per lines
    • [0:15]NL (def=0x0) // Number of lines
  • 0x4002B048LWR// line watermark register

    • [0:15]LW (def=0x0) // Line watermark
  • 0x4002B04CAMTCR// AHB master timer configuration register

    • [8:15]DT (def=0x0) // Dead Time
    • [0]EN (def=0x0) // Enable
  • 0x4002B400FGCLUT// FGCLUT

    • [24:31]APLHA (def=0x0) // APLHA
    • [16:23]RED (def=0x0) // RED
    • [8:15]GREEN (def=0x0) // GREEN
    • [0:7]BLUE (def=0x0) // BLUE
  • 0x4002B800BGCLUT// BGCLUT

    • [24:31]APLHA (def=0x0) // APLHA
    • [16:23]RED (def=0x0) // RED
    • [8:15]GREEN (def=0x0) // GREEN
    • [0:7]BLUE (def=0x0) // BLUE
  interrupts:
  • [118] DMA2D // DMA2D global interrupt
• 0x5002B000SEC_DMA2D//

  • 0x5002B000CR// control register

    • [16:17]MODE (def=0x0) // DMA2D mode
    • [13]CEIE (def=0x0) // Configuration Error Interrupt Enable
    • [12]CTCIE (def=0x0) // CLUT transfer complete interrupt enable
    • [11]CAEIE (def=0x0) // CLUT access error interrupt enable
    • [10]TWIE (def=0x0) // Transfer watermark interrupt enable
    • [9]TCIE (def=0x0) // Transfer complete interrupt enable
    • [8]TEIE (def=0x0) // Transfer error interrupt enable
    • [6]LOM (def=0x0) // Line Offset Mode
    • [2]ABORT (def=0x0) // Abort
    • [1]SUSP (def=0x0) // Suspend
    • [0]START (def=0x0) // Start
  • 0x5002B004ISR// Interrupt Status Register

    • [5]CEIF (def=0x0) // Configuration error interrupt flag
    • [4]CTCIF (def=0x0) // CLUT transfer complete interrupt flag
    • [3]CAEIF (def=0x0) // CLUT access error interrupt flag
    • [2]TWIF (def=0x0) // Transfer watermark interrupt flag
    • [1]TCIF (def=0x0) // Transfer complete interrupt flag
    • [0]TEIF (def=0x0) // Transfer error interrupt flag
  • 0x5002B008IFCR// interrupt flag clear register

    • [5]CCEIF (def=0x0) // Clear configuration error interrupt flag
    • [4]CCTCIF (def=0x0) // Clear CLUT transfer complete interrupt flag
    • [3]CAECIF (def=0x0) // Clear CLUT access error interrupt flag
    • [2]CTWIF (def=0x0) // Clear transfer watermark interrupt flag
    • [1]CTCIF (def=0x0) // Clear transfer complete interrupt flag
    • [0]CTEIF (def=0x0) // Clear Transfer error interrupt flag
  • 0x5002B00CFGMAR// foreground memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x5002B010FGOR// foreground offset register

    • [0:15]LO (def=0x0) // Line offset
  • 0x5002B014BGMAR// background memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x5002B018BGOR// background offset register

    • [0:15]LO (def=0x0) // Line offset
  • 0x5002B01CFGPFCCR// foreground PFC control register

    • [24:31]ALPHA (def=0x0) // Alpha value
    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [16:17]AM (def=0x0) // Alpha mode
    • [8:15]CS (def=0x0) // CLUT size
    • [5]START (def=0x0) // Start
    • [4]CCM (def=0x0) // CLUT color mode
    • [0:3]CM (def=0x0) // Color mode
  • 0x5002B020FGCOLR// foreground color register

    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x5002B024BGPFCCR// background PFC control register

    • [24:31]ALPHA (def=0x0) // Alpha value
    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [16:17]AM (def=0x0) // Alpha mode
    • [8:15]CS (def=0x0) // CLUT size
    • [5]START (def=0x0) // Start
    • [4]CCM (def=0x0) // CLUT Color mode
    • [0:3]CM (def=0x0) // Color mode
  • 0x5002B028BGCOLR// background color register

    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x5002B02CFGCMAR// foreground CLUT memory address register

    • [0:31]MA (def=0x0) // Memory Address
  • 0x5002B030BGCMAR// background CLUT memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x5002B034OPFCCR// output PFC control register

    • [21]RBS (def=0x0) // Red Blue Swap
    • [20]AI (def=0x0) // Alpha Inverted
    • [9]SB (def=0x0) // Swap Bytes
    • [0:2]CM (def=0x0) // Color mode
  • 0x5002B038OCOLR_RGB888// output color register

    • [24:31]APLHA (def=0x0) // Alpha Channel Value
    • [16:23]RED (def=0x0) // Red Value
    • [8:15]GREEN (def=0x0) // Green Value
    • [0:7]BLUE (def=0x0) // Blue Value
  • 0x5002B038OCOLR_RGB565// output color register

    • [11:15]RED (def=0x0) // Red value in RGB565 mode
    • [5:10]GREEN (def=0x0) // Green value in RGB565 mode
    • [0:4]BLUE (def=0x0) // Blue value in RGB565 mode
  • 0x5002B038OCOLR_ARGB1555// output color register

    • [15]A (def=0x0) // Alpha channel value in ARGB1555 mode
    • [10:14]RED (def=0x0) // Red value in ARGB1555 mode
    • [5:9]GREEN (def=0x0) // Green value in ARGB1555 mode
    • [0:4]BLUE (def=0x0) // Blue value in ARGB1555 mode
  • 0x5002B038OCOLR_ARGB4444// output color register

    • [12:15]ALPHA (def=0x0) // Alpha channel value in ARGB4444
    • [8:11]RED (def=0x0) // Red value in ARGB4444 mode
    • [4:7]GREEN (def=0x0) // Green value in ARGB4444 mode
    • [0:3]BLUE (def=0x0) // Blue value in ARGB4444 mode
  • 0x5002B03COMAR// output memory address register

    • [0:31]MA (def=0x0) // Memory Address
  • 0x5002B040OOR// output offset register

    • [0:15]LO (def=0x0) // Line Offset
  • 0x5002B044NLR// number of line register

    • [16:29]PL (def=0x0) // Pixel per lines
    • [0:15]NL (def=0x0) // Number of lines
  • 0x5002B048LWR// line watermark register

    • [0:15]LW (def=0x0) // Line watermark
  • 0x5002B04CAMTCR// AHB master timer configuration register

    • [8:15]DT (def=0x0) // Dead Time
    • [0]EN (def=0x0) // Enable
  • 0x5002B400FGCLUT// FGCLUT

    • [24:31]APLHA (def=0x0) // APLHA
    • [16:23]RED (def=0x0) // RED
    • [8:15]GREEN (def=0x0) // GREEN
    • [0:7]BLUE (def=0x0) // BLUE
  • 0x5002B800BGCLUT// BGCLUT

    • [24:31]APLHA (def=0x0) // APLHA
    • [16:23]RED (def=0x0) // RED
    • [8:15]GREEN (def=0x0) // GREEN
    • [0:7]BLUE (def=0x0) // BLUE
• 0x40026000RAMCFG// RAMCFG

  • 0x40026000RAM1CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x40026008RAM1ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x40026028RAM1ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x40026040RAM2CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x40026044RAM2IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x40026048RAM2ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x4002604CRAM2SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x40026050RAM2DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x40026054RAM2ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
  • 0x40026058RAM2WPR1// RAMCFG SRAM2 write protection register 1

    • [0]P0WP (def=0x0) // P0WP
    • [1]P1WP (def=0x0) // P1WP
    • [2]P2WP (def=0x0) // P2WP
    • [3]P3WP (def=0x0) // P3WP
    • [4]P4WP (def=0x0) // P4WP
    • [5]P5WP (def=0x0) // P5WP
    • [6]P6WP (def=0x0) // P6WP
    • [7]P7WP (def=0x0) // P7WP
    • [8]P8WP (def=0x0) // P8WP
    • [9]P9WP (def=0x0) // P9WP
    • [10]P10WP (def=0x0) // P10WP
    • [11]P11WP (def=0x0) // P11WP
    • [12]P12WP (def=0x0) // P12WP
    • [13]P13WP (def=0x0) // P13WP
    • [14]P14WP (def=0x0) // P14WP
    • [15]P15WP (def=0x0) // P15WP
    • [16]P16WP (def=0x0) // P16WP
    • [17]P17WP (def=0x0) // P17WP
    • [18]P18WP (def=0x0) // P18WP
    • [19]P19WP (def=0x0) // P19WP
    • [20]P20WP (def=0x0) // P20WP
    • [21]P21WP (def=0x0) // P21WP
    • [22]P22WP (def=0x0) // P22WP
    • [23]P23WP (def=0x0) // P23WP
    • [24]P24WP (def=0x0) // P24WP
    • [25]P25WP (def=0x0) // P25WP
    • [26]P26WP (def=0x0) // P26WP
    • [27]P27WP (def=0x0) // P27WP
    • [28]P28WP (def=0x0) // P28WP
    • [29]P29WP (def=0x0) // P29WP
    • [30]P30WP (def=0x0) // P30WP
    • [31]P31WP (def=0x0) // P31WP
  • 0x4002605CRAM2WPR2// RAMCFG SRAM2 write protection register 2

    • [0]P32WP (def=0x0) // P32WP
    • [1]P33WP (def=0x0) // P33WP
    • [2]P34WP (def=0x0) // P34WP
    • [3]P35WP (def=0x0) // P35WP
    • [4]P36WP (def=0x0) // P36WP
    • [5]P37WP (def=0x0) // P37WP
    • [6]P38WP (def=0x0) // P38WP
    • [7]P39WP (def=0x0) // P39WP
    • [8]P40WP (def=0x0) // P40WP
    • [9]P41WP (def=0x0) // P41WP
    • [10]P42WP (def=0x0) // P42WP
    • [11]P43WP (def=0x0) // P43WP
    • [12]P44WP (def=0x0) // P44WP
    • [13]P45WP (def=0x0) // P45WP
    • [14]P46WP (def=0x0) // P46WP
    • [15]P47WP (def=0x0) // P47WP
    • [16]P48WP (def=0x0) // P48WP
    • [17]P49WP (def=0x0) // P49WP
    • [18]P50WP (def=0x0) // P50WP
    • [19]P51WP (def=0x0) // P51WP
    • [20]P52WP (def=0x0) // P52WP
    • [21]P53WP (def=0x0) // P53WP
    • [22]P54WP (def=0x0) // P54WP
    • [23]P55WP (def=0x0) // P55WP
    • [24]P56WP (def=0x0) // P56WP
    • [25]P57WP (def=0x0) // P57WP
    • [26]P58WP (def=0x0) // P58WP
    • [27]P59WP (def=0x0) // P59WP
    • [28]P60WP (def=0x0) // P60WP
    • [29]P61WP (def=0x0) // P61WP
    • [30]P62WP (def=0x0) // P62WP
    • [31]P63WP (def=0x0) // P63WP
  • 0x40026064RAM2ECCKEYR// RAMCFG SRAM x ECC key register

    • [0:7]ECCKEY (def=0x0) // ECCKEY
  • 0x40026068RAM2ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x40026080RAM3CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x40026084RAM3IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x40026088RAM3ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x4002608CRAM3SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x40026090RAM3DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x40026094RAM3ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
  • 0x400260A4RAM3ECCKEYR// RAMCFG SRAM x ECC key register

    • [0:7]ECCKEY (def=0x0) // ECCKEY
  • 0x400260A8RAM3ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x400260C0RAM4CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x400260C8RAM4ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x400260E8RAM4ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x40026100RAM5CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x40026104RAM5IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x40026108RAM5ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x4002610CRAM5SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x40026110RAM5DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x40026114RAM5ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
  interrupts:
  • [5] RAMCFG // RAM configuration global interrupt
• 0x50026000SEC_RAMCFG//

  • 0x50026000RAM1CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x50026008RAM1ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x50026028RAM1ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x50026040RAM2CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x50026044RAM2IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x50026048RAM2ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x5002604CRAM2SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x50026050RAM2DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x50026054RAM2ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
  • 0x50026058RAM2WPR1// RAMCFG SRAM2 write protection register 1

    • [0]P0WP (def=0x0) // P0WP
    • [1]P1WP (def=0x0) // P1WP
    • [2]P2WP (def=0x0) // P2WP
    • [3]P3WP (def=0x0) // P3WP
    • [4]P4WP (def=0x0) // P4WP
    • [5]P5WP (def=0x0) // P5WP
    • [6]P6WP (def=0x0) // P6WP
    • [7]P7WP (def=0x0) // P7WP
    • [8]P8WP (def=0x0) // P8WP
    • [9]P9WP (def=0x0) // P9WP
    • [10]P10WP (def=0x0) // P10WP
    • [11]P11WP (def=0x0) // P11WP
    • [12]P12WP (def=0x0) // P12WP
    • [13]P13WP (def=0x0) // P13WP
    • [14]P14WP (def=0x0) // P14WP
    • [15]P15WP (def=0x0) // P15WP
    • [16]P16WP (def=0x0) // P16WP
    • [17]P17WP (def=0x0) // P17WP
    • [18]P18WP (def=0x0) // P18WP
    • [19]P19WP (def=0x0) // P19WP
    • [20]P20WP (def=0x0) // P20WP
    • [21]P21WP (def=0x0) // P21WP
    • [22]P22WP (def=0x0) // P22WP
    • [23]P23WP (def=0x0) // P23WP
    • [24]P24WP (def=0x0) // P24WP
    • [25]P25WP (def=0x0) // P25WP
    • [26]P26WP (def=0x0) // P26WP
    • [27]P27WP (def=0x0) // P27WP
    • [28]P28WP (def=0x0) // P28WP
    • [29]P29WP (def=0x0) // P29WP
    • [30]P30WP (def=0x0) // P30WP
    • [31]P31WP (def=0x0) // P31WP
  • 0x5002605CRAM2WPR2// RAMCFG SRAM2 write protection register 2

    • [0]P32WP (def=0x0) // P32WP
    • [1]P33WP (def=0x0) // P33WP
    • [2]P34WP (def=0x0) // P34WP
    • [3]P35WP (def=0x0) // P35WP
    • [4]P36WP (def=0x0) // P36WP
    • [5]P37WP (def=0x0) // P37WP
    • [6]P38WP (def=0x0) // P38WP
    • [7]P39WP (def=0x0) // P39WP
    • [8]P40WP (def=0x0) // P40WP
    • [9]P41WP (def=0x0) // P41WP
    • [10]P42WP (def=0x0) // P42WP
    • [11]P43WP (def=0x0) // P43WP
    • [12]P44WP (def=0x0) // P44WP
    • [13]P45WP (def=0x0) // P45WP
    • [14]P46WP (def=0x0) // P46WP
    • [15]P47WP (def=0x0) // P47WP
    • [16]P48WP (def=0x0) // P48WP
    • [17]P49WP (def=0x0) // P49WP
    • [18]P50WP (def=0x0) // P50WP
    • [19]P51WP (def=0x0) // P51WP
    • [20]P52WP (def=0x0) // P52WP
    • [21]P53WP (def=0x0) // P53WP
    • [22]P54WP (def=0x0) // P54WP
    • [23]P55WP (def=0x0) // P55WP
    • [24]P56WP (def=0x0) // P56WP
    • [25]P57WP (def=0x0) // P57WP
    • [26]P58WP (def=0x0) // P58WP
    • [27]P59WP (def=0x0) // P59WP
    • [28]P60WP (def=0x0) // P60WP
    • [29]P61WP (def=0x0) // P61WP
    • [30]P62WP (def=0x0) // P62WP
    • [31]P63WP (def=0x0) // P63WP
  • 0x50026064RAM2ECCKEYR// RAMCFG SRAM x ECC key register

    • [0:7]ECCKEY (def=0x0) // ECCKEY
  • 0x50026068RAM2ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x50026080RAM3CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x50026084RAM3IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x50026088RAM3ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x5002608CRAM3SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x50026090RAM3DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x50026094RAM3ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
  • 0x500260A4RAM3ECCKEYR// RAMCFG SRAM x ECC key register

    • [0:7]ECCKEY (def=0x0) // ECCKEY
  • 0x500260A8RAM3ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x500260C0RAM4CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x500260C8RAM4ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x500260E8RAM4ERKEYR// RAMCFG SRAM x erase key register

    • [0:7]ERASEKEY (def=0x0) // ERASEKEY
  • 0x50026100RAM5CR// RAMCFG SRAM x control register

    • [0]ECCE (def=0x0) // ECCE
    • [4]ALE (def=0x0) // ALE
    • [8]SRAMER (def=0x0) // SRAMER
    • [16:18]WSC (def=0x0) // WSC
  • 0x50026104RAM5IER// RAMCFG SRAM x interrupt enable register

    • [0]SEIE (def=0x0) // SEIE
    • [1]DEIE (def=0x0) // DEIE
    • [3]ECCNMI (def=0x0) // ECCNMI
  • 0x50026108RAM5ISR// RAMCFG RAMx interrupt status register

    • [0]SEDC (def=0x0) // SEDC
    • [1]DED (def=0x0) // DED
    • [8]SRAMBUSY (def=0x0) // SRAMBUSY
  • 0x5002610CRAM5SEAR// RAMCFG RAM x ECC single error address register

    • [0:31]ESEA (def=0x0) // ESEA
  • 0x50026110RAM5DEAR// RAMCFG RAM x ECC double error address register

    • [0:31]EDEA (def=0x0) // EDEA
  • 0x50026114RAM5ICR// RAMCFG RAM x interrupt clear register x

    • [0]CSEDC (def=0x0) // CSEDC
    • [1]CDED (def=0x0) // CDED
• 0x4202C000DCMI// Digital camera interface

  • 0x4202C000CR// control register

    • [20]OELS (def=0x0) // Odd/Even Line Select (Line Select Start)
    • [19]LSM (def=0x0) // Line Select mode
    • [18]OEBS (def=0x0) // Odd/Even Byte Select (Byte Select Start)
    • [16:17]BSM (def=0x0) // Byte Select mode
    • [14]ENABLE (def=0x0) // DCMI enable
    • [10:11]EDM (def=0x0) // Extended data mode
    • [8:9]FCRC (def=0x0) // Frame capture rate control
    • [7]VSPOL (def=0x0) // Vertical synchronization polarity
    • [6]HSPOL (def=0x0) // Horizontal synchronization polarity
    • [5]PCKPOL (def=0x0) // Pixel clock polarity
    • [4]ESS (def=0x0) // Embedded synchronization select
    • [3]JPEG (def=0x0) // JPEG format
    • [2]CROP (def=0x0) // Crop feature
    • [1]CM (def=0x0) // Capture mode
    • [0]CAPTURE (def=0x0) // Capture enable
  • 0x4202C004SR// status register

    • [2]FNE (def=0x0) // FIFO not empty
    • [1]VSYNC (def=0x0) // Vertical synchronization
    • [0]HSYNC (def=0x0) // Horizontal synchronization
  • 0x4202C008RIS// raw interrupt status register

    • [4]LINE_RIS (def=0x0) // Line raw interrupt status
    • [3]VSYNC_RIS (def=0x0) // DCMI_VSYNC raw interrupt status
    • [2]ERR_RIS (def=0x0) // Synchronization error raw interrupt status
    • [1]OVR_RIS (def=0x0) // Overrun raw interrupt status
    • [0]FRAME_RIS (def=0x0) // Capture complete raw interrupt status
  • 0x4202C00CIER// interrupt enable register

    • [4]LINE_IE (def=0x0) // Line interrupt enable
    • [3]VSYNC_IE (def=0x0) // DCMI_VSYNC interrupt enable
    • [2]ERR_IE (def=0x0) // Synchronization error interrupt enable
    • [1]OVR_IE (def=0x0) // Overrun interrupt enable
    • [0]FRAME_IE (def=0x0) // Capture complete interrupt enable
  • 0x4202C010MIS// masked interrupt status register

    • [4]LINE_MIS (def=0x0) // Line masked interrupt status
    • [3]VSYNC_MIS (def=0x0) // VSYNC masked interrupt status
    • [2]ERR_MIS (def=0x0) // Synchronization error masked interrupt status
    • [1]OVR_MIS (def=0x0) // Overrun masked interrupt status
    • [0]FRAME_MIS (def=0x0) // Capture complete masked interrupt status
  • 0x4202C014ICR// interrupt clear register

    • [4]LINE_ISC (def=0x0) // line interrupt status clear
    • [3]VSYNC_ISC (def=0x0) // Vertical Synchronization interrupt status clear
    • [2]ERR_ISC (def=0x0) // Synchronization error interrupt status clear
    • [1]OVR_ISC (def=0x0) // Overrun interrupt status clear
    • [0]FRAME_ISC (def=0x0) // Capture complete interrupt status clear
  • 0x4202C018ESCR// background offset register

    • [24:31]FEC (def=0x0) // Frame end delimiter code
    • [16:23]LEC (def=0x0) // Line end delimiter code
    • [8:15]LSC (def=0x0) // Line start delimiter code
    • [0:7]FSC (def=0x0) // Frame start delimiter code
  • 0x4202C01CESUR// embedded synchronization unmask register

    • [24:31]FEU (def=0x0) // Frame end delimiter unmask
    • [16:23]LEU (def=0x0) // Line end delimiter unmask
    • [8:15]LSU (def=0x0) // Line start delimiter unmask
    • [0:7]FSU (def=0x0) // Frame start delimiter unmask
  • 0x4202C020CWSTRT// crop window start

    • [16:28]VST (def=0x0) // Vertical start line count
    • [0:13]HOFFCNT (def=0x0) // Horizontal offset count
  • 0x4202C024CWSIZE// crop window size

    • [16:29]VLINE (def=0x0) // Vertical line count
    • [0:13]CAPCNT (def=0x0) // Capture count
  • 0x4202C028DR// data register

    • [24:31]BYTE3 (def=0x0) // Data byte 3
    • [16:23]BYTE2 (def=0x0) // Data byte 2
    • [8:15]BYTE1 (def=0x0) // Data byte 1
    • [0:7]BYTE0 (def=0x0) // Data byte 0
  interrupts:
  • [119] DCMI // Digital camera interface
• 0x5202C000SEC_DCMI//

  • 0x5202C000CR// control register

    • [20]OELS (def=0x0) // Odd/Even Line Select (Line Select Start)
    • [19]LSM (def=0x0) // Line Select mode
    • [18]OEBS (def=0x0) // Odd/Even Byte Select (Byte Select Start)
    • [16:17]BSM (def=0x0) // Byte Select mode
    • [14]ENABLE (def=0x0) // DCMI enable
    • [10:11]EDM (def=0x0) // Extended data mode
    • [8:9]FCRC (def=0x0) // Frame capture rate control
    • [7]VSPOL (def=0x0) // Vertical synchronization polarity
    • [6]HSPOL (def=0x0) // Horizontal synchronization polarity
    • [5]PCKPOL (def=0x0) // Pixel clock polarity
    • [4]ESS (def=0x0) // Embedded synchronization select
    • [3]JPEG (def=0x0) // JPEG format
    • [2]CROP (def=0x0) // Crop feature
    • [1]CM (def=0x0) // Capture mode
    • [0]CAPTURE (def=0x0) // Capture enable
  • 0x5202C004SR// status register

    • [2]FNE (def=0x0) // FIFO not empty
    • [1]VSYNC (def=0x0) // Vertical synchronization
    • [0]HSYNC (def=0x0) // Horizontal synchronization
  • 0x5202C008RIS// raw interrupt status register

    • [4]LINE_RIS (def=0x0) // Line raw interrupt status
    • [3]VSYNC_RIS (def=0x0) // DCMI_VSYNC raw interrupt status
    • [2]ERR_RIS (def=0x0) // Synchronization error raw interrupt status
    • [1]OVR_RIS (def=0x0) // Overrun raw interrupt status
    • [0]FRAME_RIS (def=0x0) // Capture complete raw interrupt status
  • 0x5202C00CIER// interrupt enable register

    • [4]LINE_IE (def=0x0) // Line interrupt enable
    • [3]VSYNC_IE (def=0x0) // DCMI_VSYNC interrupt enable
    • [2]ERR_IE (def=0x0) // Synchronization error interrupt enable
    • [1]OVR_IE (def=0x0) // Overrun interrupt enable
    • [0]FRAME_IE (def=0x0) // Capture complete interrupt enable
  • 0x5202C010MIS// masked interrupt status register

    • [4]LINE_MIS (def=0x0) // Line masked interrupt status
    • [3]VSYNC_MIS (def=0x0) // VSYNC masked interrupt status
    • [2]ERR_MIS (def=0x0) // Synchronization error masked interrupt status
    • [1]OVR_MIS (def=0x0) // Overrun masked interrupt status
    • [0]FRAME_MIS (def=0x0) // Capture complete masked interrupt status
  • 0x5202C014ICR// interrupt clear register

    • [4]LINE_ISC (def=0x0) // line interrupt status clear
    • [3]VSYNC_ISC (def=0x0) // Vertical Synchronization interrupt status clear
    • [2]ERR_ISC (def=0x0) // Synchronization error interrupt status clear
    • [1]OVR_ISC (def=0x0) // Overrun interrupt status clear
    • [0]FRAME_ISC (def=0x0) // Capture complete interrupt status clear
  • 0x5202C018ESCR// background offset register

    • [24:31]FEC (def=0x0) // Frame end delimiter code
    • [16:23]LEC (def=0x0) // Line end delimiter code
    • [8:15]LSC (def=0x0) // Line start delimiter code
    • [0:7]FSC (def=0x0) // Frame start delimiter code
  • 0x5202C01CESUR// embedded synchronization unmask register

    • [24:31]FEU (def=0x0) // Frame end delimiter unmask
    • [16:23]LEU (def=0x0) // Line end delimiter unmask
    • [8:15]LSU (def=0x0) // Line start delimiter unmask
    • [0:7]FSU (def=0x0) // Frame start delimiter unmask
  • 0x5202C020CWSTRT// crop window start

    • [16:28]VST (def=0x0) // Vertical start line count
    • [0:13]HOFFCNT (def=0x0) // Horizontal offset count
  • 0x5202C024CWSIZE// crop window size

    • [16:29]VLINE (def=0x0) // Vertical line count
    • [0:13]CAPCNT (def=0x0) // Capture count
  • 0x5202C028DR// data register

    • [24:31]BYTE3 (def=0x0) // Data byte 3
    • [16:23]BYTE2 (def=0x0) // Data byte 2
    • [8:15]BYTE1 (def=0x0) // Data byte 1
    • [0:7]BYTE0 (def=0x0) // Data byte 0
• 0xE000EE08DCB// Debug Control Block

  • 0xE000EE08DSCSR// Debug Security Control and Status Register

    • [16]CDS (def=0x0) // Current domain Secure